Initial commit: Linux kernel 4.19 for Unplugged OS

include/dt-bindings/arm/ux500_pm_domains.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+
+#define DOMAIN_VAPE		0
+
+/* Number of PM domains. */
+#define NR_DOMAINS		(DOMAIN_VAPE + 1)
+
+#endif

include/dt-bindings/bus/ti-sysc.h

@@ -0,0 +1,24 @@
+/* TI sysc interconnect target module defines */
+
+/* Generic sysc found on omap2 and later, also known as type1 */
+#define SYSC_OMAP2_CLOCKACTIVITY	(3 << 8)
+#define SYSC_OMAP2_EMUFREE		(1 << 5)
+#define SYSC_OMAP2_ENAWAKEUP		(1 << 2)
+#define SYSC_OMAP2_SOFTRESET		(1 << 1)
+#define SYSC_OMAP2_AUTOIDLE		(1 << 0)
+
+/* Generic sysc found on omap4 and later, also known as type2 */
+#define SYSC_OMAP4_DMADISABLE		(1 << 16)
+#define SYSC_OMAP4_FREEEMU		(1 << 1)	/* Also known as EMUFREE */
+#define SYSC_OMAP4_SOFTRESET		(1 << 0)
+
+/* SmartReflex sysc found on 36xx and later */
+#define SYSC_OMAP3_SR_ENAWAKEUP		(1 << 26)
+
+#define SYSC_DRA7_MCAN_ENAWAKEUP	(1 << 4)
+
+/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
+#define SYSC_IDLE_FORCE			0
+#define SYSC_IDLE_NO			1
+#define SYSC_IDLE_SMART			2
+#define SYSC_IDLE_SMART_WKUP		3

include/dt-bindings/clk/ti-dra7-atl.h

@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for DRA7 ATL (Audio Tracking Logic)
+ *
+ * The constants defined in this header are used in dts files
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
+#define _DT_BINDINGS_CLK_DRA7_ATL_H
+
+#define DRA7_ATL_WS_MCASP1_FSR		0
+#define DRA7_ATL_WS_MCASP1_FSX		1
+#define DRA7_ATL_WS_MCASP2_FSR		2
+#define DRA7_ATL_WS_MCASP2_FSX		3
+#define DRA7_ATL_WS_MCASP3_FSX		4
+#define DRA7_ATL_WS_MCASP4_FSX		5
+#define DRA7_ATL_WS_MCASP5_FSX		6
+#define DRA7_ATL_WS_MCASP6_FSX		7
+#define DRA7_ATL_WS_MCASP7_FSX		8
+#define DRA7_ATL_WS_MCASP8_FSX		9
+#define DRA7_ATL_WS_MCASP8_AHCLKX	10
+#define DRA7_ATL_WS_XREF_CLK3		11
+#define DRA7_ATL_WS_XREF_CLK0		12
+#define DRA7_ATL_WS_XREF_CLK1		13
+#define DRA7_ATL_WS_XREF_CLK2		14
+#define DRA7_ATL_WS_OSC1_X1		15
+
+#endif

include/dt-bindings/clock/actions,s700-cmu.h

@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Device Tree binding constants for Actions Semi S700 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Author: Pathiban Nallathambi <pn@denx.de>
+ * Author: Saravanan Sekar <sravanhome@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE			0
+
+/* pll clocks */
+#define CLK_CORE_PLL			1
+#define CLK_DEV_PLL			2
+#define CLK_DDR_PLL			3
+#define CLK_NAND_PLL			4
+#define CLK_DISPLAY_PLL			5
+#define CLK_TVOUT_PLL			6
+#define CLK_CVBS_PLL			7
+#define CLK_AUDIO_PLL			8
+#define CLK_ETHERNET_PLL		9
+
+/* system clock */
+#define CLK_CPU				10
+#define CLK_DEV				11
+#define CLK_AHB				12
+#define CLK_APB				13
+#define CLK_DMAC			14
+#define CLK_NOC0_CLK_MUX		15
+#define CLK_NOC1_CLK_MUX		16
+#define CLK_HP_CLK_MUX			17
+#define CLK_HP_CLK_DIV			18
+#define CLK_NOC1_CLK_DIV		19
+#define CLK_NOC0			20
+#define CLK_NOC1			21
+#define CLK_SENOR_SRC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+#define CLK_TIMER			24
+#define CLK_DSI				25
+#define CLK_CSI				26
+#define CLK_SI				27
+#define CLK_DE				28
+#define CLK_HDE				29
+#define CLK_VDE				30
+#define CLK_VCE				31
+#define CLK_NAND			32
+#define CLK_SD0				33
+#define CLK_SD1				34
+#define CLK_SD2				35
+
+#define CLK_UART0			36
+#define CLK_UART1			37
+#define CLK_UART2			38
+#define CLK_UART3			39
+#define CLK_UART4			40
+#define CLK_UART5			41
+#define CLK_UART6			42
+
+#define CLK_PWM0			43
+#define CLK_PWM1			44
+#define CLK_PWM2			45
+#define CLK_PWM3			46
+#define CLK_PWM4			47
+#define CLK_PWM5			48
+#define CLK_GPU3D			49
+
+#define CLK_I2C0			50
+#define CLK_I2C1			51
+#define CLK_I2C2			52
+#define CLK_I2C3			53
+
+#define CLK_SPI0			54
+#define CLK_SPI1			55
+#define CLK_SPI2			56
+#define CLK_SPI3			57
+
+#define CLK_USB3_480MPLL0		58
+#define CLK_USB3_480MPHY0		59
+#define CLK_USB3_5GPHY			60
+#define CLK_USB3_CCE			61
+#define CLK_USB3_MAC			62
+
+#define CLK_LCD				63
+#define CLK_HDMI_AUDIO			64
+#define CLK_I2SRX			65
+#define CLK_I2STX			66
+
+#define CLK_SENSOR0			67
+#define CLK_SENSOR1			68
+
+#define CLK_HDMI_DEV			69
+
+#define CLK_ETHERNET			70
+#define CLK_RMII_REF			71
+
+#define CLK_USB2H0_PLLEN		72
+#define CLK_USB2H0_PHY			73
+#define CLK_USB2H0_CCE			74
+#define CLK_USB2H1_PLLEN		75
+#define CLK_USB2H1_PHY			76
+#define CLK_USB2H1_CCE			77
+
+#define CLK_TVOUT			78
+
+#define CLK_THERMAL_SENSOR		79
+
+#define CLK_IRC_SWITCH			80
+#define CLK_PCM1			81
+#define CLK_NR_CLKS			(CLK_PCM1 + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */

include/dt-bindings/clock/actions,s900-cmu.h

@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE			0
+
+/* fixed rate clocks */
+#define CLK_LOSC			1
+#define CLK_HOSC			2
+
+/* pll clocks */
+#define CLK_CORE_PLL			3
+#define CLK_DEV_PLL			4
+#define CLK_DDR_PLL			5
+#define CLK_NAND_PLL			6
+#define CLK_DISPLAY_PLL			7
+#define CLK_DSI_PLL			8
+#define CLK_ASSIST_PLL			9
+#define CLK_AUDIO_PLL			10
+
+/* system clock */
+#define CLK_CPU				15
+#define CLK_DEV				16
+#define CLK_NOC				17
+#define CLK_NOC_MUX			18
+#define CLK_NOC_DIV			19
+#define CLK_AHB				20
+#define CLK_APB				21
+#define CLK_DMAC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+
+#define CLK_BISP			24
+#define CLK_CSI0			25
+#define CLK_CSI1			26
+
+#define CLK_DE0				27
+#define CLK_DE1				28
+#define CLK_DE2				29
+#define CLK_DE3				30
+#define CLK_DSI				32
+
+#define CLK_GPU				33
+#define CLK_GPU_CORE			34
+#define CLK_GPU_MEM			35
+#define CLK_GPU_SYS			36
+
+#define CLK_HDE				37
+#define CLK_I2C0			38
+#define CLK_I2C1			39
+#define CLK_I2C2			40
+#define CLK_I2C3			41
+#define CLK_I2C4			42
+#define CLK_I2C5			43
+#define CLK_I2SRX			44
+#define CLK_I2STX			45
+#define CLK_IMX				46
+#define CLK_LCD				47
+#define CLK_NAND0			48
+#define CLK_NAND1			49
+#define CLK_PWM0			50
+#define CLK_PWM1			51
+#define CLK_PWM2			52
+#define CLK_PWM3			53
+#define CLK_PWM4			54
+#define CLK_PWM5			55
+#define CLK_SD0				56
+#define CLK_SD1				57
+#define CLK_SD2				58
+#define CLK_SD3				59
+#define CLK_SENSOR			60
+#define CLK_SPEED_SENSOR		61
+#define CLK_SPI0			62
+#define CLK_SPI1			63
+#define CLK_SPI2			64
+#define CLK_SPI3			65
+#define CLK_THERMAL_SENSOR		66
+#define CLK_UART0			67
+#define CLK_UART1			68
+#define CLK_UART2			69
+#define CLK_UART3			70
+#define CLK_UART4			71
+#define CLK_UART5			72
+#define CLK_UART6			73
+#define CLK_VCE				74
+#define CLK_VDE				75
+
+#define CLK_USB3_480MPLL0		76
+#define CLK_USB3_480MPHY0		77
+#define CLK_USB3_5GPHY			78
+#define CLK_USB3_CCE			79
+#define CLK_USB3_MAC			80
+
+#define CLK_TIMER			83
+
+#define CLK_HDMI_AUDIO			84
+
+#define CLK_24M				85
+
+#define CLK_EDP				86
+
+#define CLK_24M_EDP			87
+#define CLK_EDP_PLL			88
+#define CLK_EDP_LINK			89
+
+#define CLK_USB2H0_PLLEN		90
+#define CLK_USB2H0_PHY			91
+#define CLK_USB2H0_CCE			92
+#define CLK_USB2H1_PLLEN		93
+#define CLK_USB2H1_PHY			94
+#define CLK_USB2H1_CCE			95
+
+#define CLK_DDR0			96
+#define CLK_DDR1			97
+#define CLK_DMM				98
+
+#define CLK_ETH_MAC			99
+#define CLK_RMII_REF			100
+
+#define CLK_NR_CLKS			(CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */

include/dt-bindings/clock/alphascale,asm9260.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ASM9260_H
+#define _DT_BINDINGS_CLK_ASM9260_H
+
+/* ahb gate */
+#define CLKID_AHB_ROM		0
+#define CLKID_AHB_RAM		1
+#define CLKID_AHB_GPIO		2
+#define CLKID_AHB_MAC		3
+#define CLKID_AHB_EMI		4
+#define CLKID_AHB_USB0		5
+#define CLKID_AHB_USB1		6
+#define CLKID_AHB_DMA0		7
+#define CLKID_AHB_DMA1		8
+#define CLKID_AHB_UART0		9
+#define CLKID_AHB_UART1		10
+#define CLKID_AHB_UART2		11
+#define CLKID_AHB_UART3		12
+#define CLKID_AHB_UART4		13
+#define CLKID_AHB_UART5		14
+#define CLKID_AHB_UART6		15
+#define CLKID_AHB_UART7		16
+#define CLKID_AHB_UART8		17
+#define CLKID_AHB_UART9		18
+#define CLKID_AHB_I2S0		19
+#define CLKID_AHB_I2C0		20
+#define CLKID_AHB_I2C1		21
+#define CLKID_AHB_SSP0		22
+#define CLKID_AHB_IOCONFIG	23
+#define CLKID_AHB_WDT		24
+#define CLKID_AHB_CAN0		25
+#define CLKID_AHB_CAN1		26
+#define CLKID_AHB_MPWM		27
+#define CLKID_AHB_SPI0		28
+#define CLKID_AHB_SPI1		29
+#define CLKID_AHB_QEI		30
+#define CLKID_AHB_QUADSPI0	31
+#define CLKID_AHB_CAMIF		32
+#define CLKID_AHB_LCDIF		33
+#define CLKID_AHB_TIMER0	34
+#define CLKID_AHB_TIMER1	35
+#define CLKID_AHB_TIMER2	36
+#define CLKID_AHB_TIMER3	37
+#define CLKID_AHB_IRQ		38
+#define CLKID_AHB_RTC		39
+#define CLKID_AHB_NAND		40
+#define CLKID_AHB_ADC0		41
+#define CLKID_AHB_LED		42
+#define CLKID_AHB_DAC0		43
+#define CLKID_AHB_LCD		44
+#define CLKID_AHB_I2S1		45
+#define CLKID_AHB_MAC1		46
+
+/* devider */
+#define CLKID_SYS_CPU		47
+#define CLKID_SYS_AHB		48
+#define CLKID_SYS_I2S0M		49
+#define CLKID_SYS_I2S0S		50
+#define CLKID_SYS_I2S1M		51
+#define CLKID_SYS_I2S1S		52
+#define CLKID_SYS_UART0		53
+#define CLKID_SYS_UART1		54
+#define CLKID_SYS_UART2		55
+#define CLKID_SYS_UART3		56
+#define CLKID_SYS_UART4		56
+#define CLKID_SYS_UART5		57
+#define CLKID_SYS_UART6		58
+#define CLKID_SYS_UART7		59
+#define CLKID_SYS_UART8		60
+#define CLKID_SYS_UART9		61
+#define CLKID_SYS_SPI0		62
+#define CLKID_SYS_SPI1		63
+#define CLKID_SYS_QUADSPI	64
+#define CLKID_SYS_SSP0		65
+#define CLKID_SYS_NAND		66
+#define CLKID_SYS_TRACE		67
+#define CLKID_SYS_CAMM		68
+#define CLKID_SYS_WDT		69
+#define CLKID_SYS_CLKOUT	70
+#define CLKID_SYS_MAC		71
+#define CLKID_SYS_LCD		72
+#define CLKID_SYS_ADCANA	73
+
+#define MAX_CLKS		74
+#endif

include/dt-bindings/clock/am3.h

@@ -0,0 +1,108 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET	0x0
+#define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET	0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET	0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET	0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset)	((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL	AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET	0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL	AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET	0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL	AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+#endif

include/dt-bindings/clock/am4.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM4_H
+#define __DT_BINDINGS_CLK_AM4_H
+
+#define AM4_CLKCTRL_OFFSET	0x20
+#define AM4_CLKCTRL_INDEX(offset)	((offset) - AM4_CLKCTRL_OFFSET)
+
+/* l4_wkup clocks */
+#define AM4_ADC_TSC_CLKCTRL	AM4_CLKCTRL_INDEX(0x120)
+#define AM4_L4_WKUP_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
+#define AM4_WKUP_M3_CLKCTRL	AM4_CLKCTRL_INDEX(0x228)
+#define AM4_COUNTER_32K_CLKCTRL	AM4_CLKCTRL_INDEX(0x230)
+#define AM4_TIMER1_CLKCTRL	AM4_CLKCTRL_INDEX(0x328)
+#define AM4_WD_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x338)
+#define AM4_I2C1_CLKCTRL	AM4_CLKCTRL_INDEX(0x340)
+#define AM4_UART1_CLKCTRL	AM4_CLKCTRL_INDEX(0x348)
+#define AM4_SMARTREFLEX0_CLKCTRL	AM4_CLKCTRL_INDEX(0x350)
+#define AM4_SMARTREFLEX1_CLKCTRL	AM4_CLKCTRL_INDEX(0x358)
+#define AM4_CONTROL_CLKCTRL	AM4_CLKCTRL_INDEX(0x360)
+#define AM4_GPIO1_CLKCTRL	AM4_CLKCTRL_INDEX(0x368)
+
+/* mpu clocks */
+#define AM4_MPU_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* gfx_l3 clocks */
+#define AM4_GFX_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_rtc clocks */
+#define AM4_RTC_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_per clocks */
+#define AM4_L3_MAIN_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+#define AM4_AES_CLKCTRL	AM4_CLKCTRL_INDEX(0x28)
+#define AM4_DES_CLKCTRL	AM4_CLKCTRL_INDEX(0x30)
+#define AM4_L3_INSTR_CLKCTRL	AM4_CLKCTRL_INDEX(0x40)
+#define AM4_OCMCRAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x50)
+#define AM4_SHAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x58)
+#define AM4_VPFE0_CLKCTRL	AM4_CLKCTRL_INDEX(0x68)
+#define AM4_VPFE1_CLKCTRL	AM4_CLKCTRL_INDEX(0x70)
+#define AM4_TPCC_CLKCTRL	AM4_CLKCTRL_INDEX(0x78)
+#define AM4_TPTC0_CLKCTRL	AM4_CLKCTRL_INDEX(0x80)
+#define AM4_TPTC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x88)
+#define AM4_TPTC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x90)
+#define AM4_L4_HS_CLKCTRL	AM4_CLKCTRL_INDEX(0xa0)
+#define AM4_GPMC_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
+#define AM4_MCASP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x238)
+#define AM4_MCASP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x240)
+#define AM4_MMC3_CLKCTRL	AM4_CLKCTRL_INDEX(0x248)
+#define AM4_QSPI_CLKCTRL	AM4_CLKCTRL_INDEX(0x258)
+#define AM4_USB_OTG_SS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x260)
+#define AM4_USB_OTG_SS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x268)
+#define AM4_PRUSS_CLKCTRL	AM4_CLKCTRL_INDEX(0x320)
+#define AM4_L4_LS_CLKCTRL	AM4_CLKCTRL_INDEX(0x420)
+#define AM4_D_CAN0_CLKCTRL	AM4_CLKCTRL_INDEX(0x428)
+#define AM4_D_CAN1_CLKCTRL	AM4_CLKCTRL_INDEX(0x430)
+#define AM4_EPWMSS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x438)
+#define AM4_EPWMSS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x440)
+#define AM4_EPWMSS2_CLKCTRL	AM4_CLKCTRL_INDEX(0x448)
+#define AM4_EPWMSS3_CLKCTRL	AM4_CLKCTRL_INDEX(0x450)
+#define AM4_EPWMSS4_CLKCTRL	AM4_CLKCTRL_INDEX(0x458)
+#define AM4_EPWMSS5_CLKCTRL	AM4_CLKCTRL_INDEX(0x460)
+#define AM4_ELM_CLKCTRL	AM4_CLKCTRL_INDEX(0x468)
+#define AM4_GPIO2_CLKCTRL	AM4_CLKCTRL_INDEX(0x478)
+#define AM4_GPIO3_CLKCTRL	AM4_CLKCTRL_INDEX(0x480)
+#define AM4_GPIO4_CLKCTRL	AM4_CLKCTRL_INDEX(0x488)
+#define AM4_GPIO5_CLKCTRL	AM4_CLKCTRL_INDEX(0x490)
+#define AM4_GPIO6_CLKCTRL	AM4_CLKCTRL_INDEX(0x498)
+#define AM4_HDQ1W_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a0)
+#define AM4_I2C2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a8)
+#define AM4_I2C3_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b0)
+#define AM4_MAILBOX_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b8)
+#define AM4_MMC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c0)
+#define AM4_MMC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c8)
+#define AM4_RNG_CLKCTRL	AM4_CLKCTRL_INDEX(0x4e0)
+#define AM4_SPI0_CLKCTRL	AM4_CLKCTRL_INDEX(0x500)
+#define AM4_SPI1_CLKCTRL	AM4_CLKCTRL_INDEX(0x508)
+#define AM4_SPI2_CLKCTRL	AM4_CLKCTRL_INDEX(0x510)
+#define AM4_SPI3_CLKCTRL	AM4_CLKCTRL_INDEX(0x518)
+#define AM4_SPI4_CLKCTRL	AM4_CLKCTRL_INDEX(0x520)
+#define AM4_SPINLOCK_CLKCTRL	AM4_CLKCTRL_INDEX(0x528)
+#define AM4_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x530)
+#define AM4_TIMER3_CLKCTRL	AM4_CLKCTRL_INDEX(0x538)
+#define AM4_TIMER4_CLKCTRL	AM4_CLKCTRL_INDEX(0x540)
+#define AM4_TIMER5_CLKCTRL	AM4_CLKCTRL_INDEX(0x548)
+#define AM4_TIMER6_CLKCTRL	AM4_CLKCTRL_INDEX(0x550)
+#define AM4_TIMER7_CLKCTRL	AM4_CLKCTRL_INDEX(0x558)
+#define AM4_TIMER8_CLKCTRL	AM4_CLKCTRL_INDEX(0x560)
+#define AM4_TIMER9_CLKCTRL	AM4_CLKCTRL_INDEX(0x568)
+#define AM4_TIMER10_CLKCTRL	AM4_CLKCTRL_INDEX(0x570)
+#define AM4_TIMER11_CLKCTRL	AM4_CLKCTRL_INDEX(0x578)
+#define AM4_UART2_CLKCTRL	AM4_CLKCTRL_INDEX(0x580)
+#define AM4_UART3_CLKCTRL	AM4_CLKCTRL_INDEX(0x588)
+#define AM4_UART4_CLKCTRL	AM4_CLKCTRL_INDEX(0x590)
+#define AM4_UART5_CLKCTRL	AM4_CLKCTRL_INDEX(0x598)
+#define AM4_UART6_CLKCTRL	AM4_CLKCTRL_INDEX(0x5a0)
+#define AM4_OCP2SCP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x5b8)
+#define AM4_OCP2SCP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x5c0)
+#define AM4_EMIF_CLKCTRL	AM4_CLKCTRL_INDEX(0x720)
+#define AM4_DSS_CORE_CLKCTRL	AM4_CLKCTRL_INDEX(0xa20)
+#define AM4_CPGMAC0_CLKCTRL	AM4_CLKCTRL_INDEX(0xb20)
+
+#endif

include/dt-bindings/clock/aspeed-clock.h

@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_ASPEED_CLOCK_H
+#define DT_BINDINGS_ASPEED_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+#define ASPEED_CLK_GATE_MCLK		2
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+#define ASPEED_CLK_GATE_REFCLK		6
+#define ASPEED_CLK_GATE_USBPORT2CLK	7
+#define ASPEED_CLK_GATE_LCLK		8
+#define ASPEED_CLK_GATE_USBUHCICLK	9
+#define ASPEED_CLK_GATE_D1CLK		10
+#define ASPEED_CLK_GATE_YCLK		11
+#define ASPEED_CLK_GATE_USBPORT1CLK	12
+#define ASPEED_CLK_GATE_UART1CLK	13
+#define ASPEED_CLK_GATE_UART2CLK	14
+#define ASPEED_CLK_GATE_UART5CLK	15
+#define ASPEED_CLK_GATE_ESPICLK		16
+#define ASPEED_CLK_GATE_MAC1CLK		17
+#define ASPEED_CLK_GATE_MAC2CLK		18
+#define ASPEED_CLK_GATE_RSACLK		19
+#define ASPEED_CLK_GATE_UART3CLK	20
+#define ASPEED_CLK_GATE_UART4CLK	21
+#define ASPEED_CLK_GATE_SDCLK		22
+#define ASPEED_CLK_GATE_LHCCLK		23
+#define ASPEED_CLK_HPLL			24
+#define ASPEED_CLK_AHB			25
+#define ASPEED_CLK_APB			26
+#define ASPEED_CLK_UART			27
+#define ASPEED_CLK_SDIO			28
+#define ASPEED_CLK_ECLK			29
+#define ASPEED_CLK_ECLK_MUX		30
+#define ASPEED_CLK_LHCLK		31
+#define ASPEED_CLK_MAC			32
+#define ASPEED_CLK_BCLK			33
+#define ASPEED_CLK_MPLL			34
+#define ASPEED_CLK_24M			35
+
+#define ASPEED_RESET_XDMA		0
+#define ASPEED_RESET_MCTP		1
+#define ASPEED_RESET_ADC		2
+#define ASPEED_RESET_JTAG_MASTER	3
+#define ASPEED_RESET_MIC		4
+#define ASPEED_RESET_PWM		5
+#define ASPEED_RESET_PECI		6
+#define ASPEED_RESET_I2C		7
+#define ASPEED_RESET_AHB		8
+#define ASPEED_RESET_CRT1		9
+
+#endif

include/dt-bindings/clock/at91.h

@@ -0,0 +1,23 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+#define AT91_PMC_LOCKA		1		/* PLLA Lock */
+#define AT91_PMC_LOCKB		2		/* PLLB Lock */
+#define AT91_PMC_MCKRDY		3		/* Master Clock */
+#define AT91_PMC_LOCKU		6		/* UPLL Lock */
+#define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
+#define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
+#define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY		24		/* Generated Clocks */
+
+#endif

include/dt-bindings/clock/ath79-clk.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_CPU		0
+#define ATH79_CLK_DDR		1
+#define ATH79_CLK_AHB		2
+
+#define ATH79_CLK_END		3
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */

include/dt-bindings/clock/axg-aoclkc.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif

include/dt-bindings/clock/axg-audio-clkc.h

@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_SLV_SCLK0		9
+#define AUD_CLKID_SLV_SCLK1		10
+#define AUD_CLKID_SLV_SCLK2		11
+#define AUD_CLKID_SLV_SCLK3		12
+#define AUD_CLKID_SLV_SCLK4		13
+#define AUD_CLKID_SLV_SCLK5		14
+#define AUD_CLKID_SLV_SCLK6		15
+#define AUD_CLKID_SLV_SCLK7		16
+#define AUD_CLKID_SLV_SCLK8		17
+#define AUD_CLKID_SLV_SCLK9		18
+#define AUD_CLKID_SLV_LRCLK0		19
+#define AUD_CLKID_SLV_LRCLK1		20
+#define AUD_CLKID_SLV_LRCLK2		21
+#define AUD_CLKID_SLV_LRCLK3		22
+#define AUD_CLKID_SLV_LRCLK4		23
+#define AUD_CLKID_SLV_LRCLK5		24
+#define AUD_CLKID_SLV_LRCLK6		25
+#define AUD_CLKID_SLV_LRCLK7		26
+#define AUD_CLKID_SLV_LRCLK8		27
+#define AUD_CLKID_SLV_LRCLK9		28
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

include/dt-bindings/clock/axg-clkc.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_HIFI_PLL				69
+#define CLKID_PCIE_CML_EN0			79
+#define CLKID_PCIE_CML_EN1			80
+#define CLKID_MIPI_ENABLE			81
+#define CLKID_GEN_CLK				84
+
+#endif /* __AXG_CLKC_H */

include/dt-bindings/clock/axis,artpec6-clkctrl.h

@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU			0
+#define ARTPEC6_CLK_CPU_PERIPH		1
+#define ARTPEC6_CLK_NAND_CLKA		2
+#define ARTPEC6_CLK_NAND_CLKB		3
+#define ARTPEC6_CLK_ETH_ACLK		4
+#define ARTPEC6_CLK_DMA_ACLK		5
+#define ARTPEC6_CLK_PTP_REF		6
+#define ARTPEC6_CLK_SD_PCLK		7
+#define ARTPEC6_CLK_SD_IMCLK		8
+#define ARTPEC6_CLK_I2S_HST		9
+#define ARTPEC6_CLK_I2S0_CLK		10
+#define ARTPEC6_CLK_I2S1_CLK		11
+#define ARTPEC6_CLK_UART_PCLK		12
+#define ARTPEC6_CLK_UART_REFCLK		13
+#define ARTPEC6_CLK_I2C			14
+#define ARTPEC6_CLK_SPI_PCLK		15
+#define ARTPEC6_CLK_SPI_SSPCLK		16
+#define ARTPEC6_CLK_SYS_TIMER		17
+#define ARTPEC6_CLK_FRACDIV_IN		18
+#define ARTPEC6_CLK_DBG_PCLK		19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS		20
+
+#endif

include/dt-bindings/clock/bcm-cygnus.h

@@ -0,0 +1,74 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_CYGNUS_H
+#define _CLOCK_BCM_CYGNUS_H
+
+/* GENPLL clock ID */
+#define BCM_CYGNUS_GENPLL                     0
+#define BCM_CYGNUS_GENPLL_AXI21_CLK           1
+#define BCM_CYGNUS_GENPLL_250MHZ_CLK          2
+#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK       3
+#define BCM_CYGNUS_GENPLL_ENET_SW_CLK         4
+#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK       5
+#define BCM_CYGNUS_GENPLL_CAN_CLK             6
+
+/* LCPLL0 clock ID */
+#define BCM_CYGNUS_LCPLL0                     0
+#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK    1
+#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK         2
+#define BCM_CYGNUS_LCPLL0_SDIO_CLK            3
+#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK     4
+#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK      5
+#define BCM_CYGNUS_LCPLL0_CH5_UNUSED          6
+
+/* MIPI PLL clock ID */
+#define BCM_CYGNUS_MIPIPLL                    0
+#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED         1
+#define BCM_CYGNUS_MIPIPLL_CH1_LCD            2
+#define BCM_CYGNUS_MIPIPLL_CH2_V3D            3
+#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED         4
+#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED         5
+#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED         6
+
+/* ASIU clock ID */
+#define BCM_CYGNUS_ASIU_KEYPAD_CLK    0
+#define BCM_CYGNUS_ASIU_ADC_CLK       1
+#define BCM_CYGNUS_ASIU_PWM_CLK       2
+
+/* AUDIO clock ID */
+#define BCM_CYGNUS_AUDIOPLL           0
+#define BCM_CYGNUS_AUDIOPLL_CH0       1
+#define BCM_CYGNUS_AUDIOPLL_CH1       2
+#define BCM_CYGNUS_AUDIOPLL_CH2       3
+
+#endif /* _CLOCK_BCM_CYGNUS_H */

include/dt-bindings/clock/bcm-ns2.h

@@ -0,0 +1,72 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NS2_H
+#define _CLOCK_BCM_NS2_H
+
+/* GENPLL SCR clock channel ID */
+#define BCM_NS2_GENPLL_SCR		0
+#define BCM_NS2_GENPLL_SCR_SCR_CLK	1
+#define BCM_NS2_GENPLL_SCR_FS_CLK	2
+#define BCM_NS2_GENPLL_SCR_AUDIO_CLK	3
+#define BCM_NS2_GENPLL_SCR_CH3_UNUSED	4
+#define BCM_NS2_GENPLL_SCR_CH4_UNUSED	5
+#define BCM_NS2_GENPLL_SCR_CH5_UNUSED	6
+
+/* GENPLL SW clock channel ID */
+#define BCM_NS2_GENPLL_SW		0
+#define BCM_NS2_GENPLL_SW_RPE_CLK	1
+#define BCM_NS2_GENPLL_SW_250_CLK	2
+#define BCM_NS2_GENPLL_SW_NIC_CLK	3
+#define BCM_NS2_GENPLL_SW_CHIMP_CLK	4
+#define BCM_NS2_GENPLL_SW_PORT_CLK	5
+#define BCM_NS2_GENPLL_SW_SDIO_CLK	6
+
+/* LCPLL DDR clock channel ID */
+#define BCM_NS2_LCPLL_DDR		0
+#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK	1
+#define BCM_NS2_LCPLL_DDR_DDR_CLK	2
+#define BCM_NS2_LCPLL_DDR_CH2_UNUSED	3
+#define BCM_NS2_LCPLL_DDR_CH3_UNUSED	4
+#define BCM_NS2_LCPLL_DDR_CH4_UNUSED	5
+#define BCM_NS2_LCPLL_DDR_CH5_UNUSED	6
+
+/* LCPLL PORTS clock channel ID */
+#define BCM_NS2_LCPLL_PORTS		0
+#define BCM_NS2_LCPLL_PORTS_WAN_CLK	1
+#define BCM_NS2_LCPLL_PORTS_RGMII_CLK	2
+#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED	3
+#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED	4
+#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED	5
+#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED	6
+
+#endif /* _CLOCK_BCM_NS2_H */

include/dt-bindings/clock/bcm-nsp.h

@@ -0,0 +1,51 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *	* Redistributions of source code must retain the above copyright
+ *	  notice, this list of conditions and the following disclaimer.
+ *	* Redistributions in binary form must reproduce the above copyright
+ *	  notice, this list of conditions and the following disclaimer in
+ *	  the documentation and/or other materials provided with the
+ *	  distribution.
+ *	* Neither the name of Broadcom Corporation nor the names of its
+ *	  contributors may be used to endorse or promote products derived
+ *	  from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL			0
+#define BCM_NSP_GENPLL_PHY_CLK		1
+#define BCM_NSP_GENPLL_ENET_SW_CLK	2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK	4
+#define BCM_NSP_GENPLL_SATA1_CLK	5
+#define BCM_NSP_GENPLL_SATA2_CLK	6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0			0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1
+#define BCM_NSP_LCPLL0_SDIO_CLK		2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3
+
+#endif /* _CLOCK_BCM_NSP_H */

include/dt-bindings/clock/bcm-sr.h

@@ -0,0 +1,111 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_SR_H
+#define _CLOCK_BCM_SR_H
+
+/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
+#define BCM_SR_GENPLL0			0
+#define BCM_SR_GENPLL0_125M_CLK		1
+#define BCM_SR_GENPLL0_SCR_CLK		2
+#define BCM_SR_GENPLL0_250M_CLK		3
+#define BCM_SR_GENPLL0_PCIE_AXI_CLK	4
+#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK	5
+#define BCM_SR_GENPLL0_PAXC_AXI_CLK	6
+
+/* GENPLL 1 clock channel ID MHB PCIE NITRO */
+#define BCM_SR_GENPLL1			0
+#define BCM_SR_GENPLL1_PCIE_TL_CLK	1
+#define BCM_SR_GENPLL1_MHB_APB_CLK	2
+
+/* GENPLL 2 clock channel ID NITRO MHB*/
+#define BCM_SR_GENPLL2			0
+#define BCM_SR_GENPLL2_NIC_CLK		1
+#define BCM_SR_GENPLL2_TS_500_CLK	2
+#define BCM_SR_GENPLL2_125_NITRO_CLK	3
+#define BCM_SR_GENPLL2_CHIMP_CLK	4
+#define BCM_SR_GENPLL2_NIC_FLASH_CLK	5
+#define BCM_SR_GENPLL2_FS4_CLK		6
+
+/* GENPLL 3 HSLS clock channel ID */
+#define BCM_SR_GENPLL3			0
+#define BCM_SR_GENPLL3_HSLS_CLK		1
+#define BCM_SR_GENPLL3_SDIO_CLK		2
+
+/* GENPLL 4 SCR clock channel ID */
+#define BCM_SR_GENPLL4			0
+#define BCM_SR_GENPLL4_CCN_CLK		1
+#define BCM_SR_GENPLL4_TPIU_PLL_CLK	2
+#define BCM_SR_GENPLL4_NOC_CLK		3
+#define BCM_SR_GENPLL4_CHCLK_FS4_CLK	4
+#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK	5
+
+/* GENPLL 5 FS4 clock channel ID */
+#define BCM_SR_GENPLL5			0
+#define BCM_SR_GENPLL5_FS4_HF_CLK	1
+#define BCM_SR_GENPLL5_CRYPTO_AE_CLK	2
+#define BCM_SR_GENPLL5_RAID_AE_CLK	3
+
+/* GENPLL 6 NITRO clock channel ID */
+#define BCM_SR_GENPLL6			0
+#define BCM_SR_GENPLL6_48_USB_CLK	1
+
+/* LCPLL0  clock channel ID */
+#define BCM_SR_LCPLL0			0
+#define BCM_SR_LCPLL0_SATA_REFP_CLK	1
+#define BCM_SR_LCPLL0_SATA_REFN_CLK	2
+#define BCM_SR_LCPLL0_SATA_350_CLK	3
+#define BCM_SR_LCPLL0_SATA_500_CLK	4
+
+/* LCPLL1  clock channel ID */
+#define BCM_SR_LCPLL1			0
+#define BCM_SR_LCPLL1_WAN_CLK		1
+#define BCM_SR_LCPLL1_USB_REF_CLK	2
+#define BCM_SR_LCPLL1_CRMU_TS_CLK	3
+
+/* LCPLL PCIE  clock channel ID */
+#define BCM_SR_LCPLL_PCIE		0
+#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL0			0
+#define BCM_SR_EMEMPLL0_EMEM_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL1			0
+#define BCM_SR_EMEMPLL1_EMEM_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL2			0
+#define BCM_SR_EMEMPLL2_EMEM_CLK	1
+
+#endif /* _CLOCK_BCM_SR_H */

include/dt-bindings/clock/bcm21664.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM21664_H
+#define _CLOCK_BCM21664_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
+ */
+
+/* bcm21664 CCU device tree "compatible" strings */
+#define BCM21664_DT_ROOT_CCU_COMPAT	"brcm,bcm21664-root-ccu"
+#define BCM21664_DT_AON_CCU_COMPAT	"brcm,bcm21664-aon-ccu"
+#define BCM21664_DT_MASTER_CCU_COMPAT	"brcm,bcm21664-master-ccu"
+#define BCM21664_DT_SLAVE_CCU_COMPAT	"brcm,bcm21664-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM21664_ROOT_CCU_FRAC_1M		0
+#define BCM21664_ROOT_CCU_CLOCK_COUNT		1
+
+/* aon CCU clock ids */
+
+#define BCM21664_AON_CCU_HUB_TIMER		0
+#define BCM21664_AON_CCU_CLOCK_COUNT		1
+
+/* master CCU clock ids */
+
+#define BCM21664_MASTER_CCU_SDIO1		0
+#define BCM21664_MASTER_CCU_SDIO2		1
+#define BCM21664_MASTER_CCU_SDIO3		2
+#define BCM21664_MASTER_CCU_SDIO4		3
+#define BCM21664_MASTER_CCU_SDIO1_SLEEP		4
+#define BCM21664_MASTER_CCU_SDIO2_SLEEP		5
+#define BCM21664_MASTER_CCU_SDIO3_SLEEP		6
+#define BCM21664_MASTER_CCU_SDIO4_SLEEP		7
+#define BCM21664_MASTER_CCU_CLOCK_COUNT		8
+
+/* slave CCU clock ids */
+
+#define BCM21664_SLAVE_CCU_UARTB		0
+#define BCM21664_SLAVE_CCU_UARTB2		1
+#define BCM21664_SLAVE_CCU_UARTB3		2
+#define BCM21664_SLAVE_CCU_BSC1			3
+#define BCM21664_SLAVE_CCU_BSC2			4
+#define BCM21664_SLAVE_CCU_BSC3			5
+#define BCM21664_SLAVE_CCU_BSC4			6
+#define BCM21664_SLAVE_CCU_CLOCK_COUNT		7
+
+#endif /* _CLOCK_BCM21664_H */

include/dt-bindings/clock/bcm281xx.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM281XX_H
+#define _CLOCK_BCM281XX_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
+ */
+
+/*
+ * These are the bcm281xx CCU device tree "compatible" strings.
+ * We're stuck with using "bcm11351" in the string because wild
+ * cards aren't allowed, and that name was the first one defined
+ * in this family of devices.
+ */
+#define BCM281XX_DT_ROOT_CCU_COMPAT	"brcm,bcm11351-root-ccu"
+#define BCM281XX_DT_AON_CCU_COMPAT	"brcm,bcm11351-aon-ccu"
+#define BCM281XX_DT_HUB_CCU_COMPAT	"brcm,bcm11351-hub-ccu"
+#define BCM281XX_DT_MASTER_CCU_COMPAT	"brcm,bcm11351-master-ccu"
+#define BCM281XX_DT_SLAVE_CCU_COMPAT	"brcm,bcm11351-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM281XX_ROOT_CCU_FRAC_1M		0
+#define BCM281XX_ROOT_CCU_CLOCK_COUNT		1
+
+/* aon CCU clock ids */
+
+#define BCM281XX_AON_CCU_HUB_TIMER		0
+#define BCM281XX_AON_CCU_PMU_BSC		1
+#define BCM281XX_AON_CCU_PMU_BSC_VAR		2
+#define BCM281XX_AON_CCU_CLOCK_COUNT		3
+
+/* hub CCU clock ids */
+
+#define BCM281XX_HUB_CCU_TMON_1M		0
+#define BCM281XX_HUB_CCU_CLOCK_COUNT		1
+
+/* master CCU clock ids */
+
+#define BCM281XX_MASTER_CCU_SDIO1		0
+#define BCM281XX_MASTER_CCU_SDIO2		1
+#define BCM281XX_MASTER_CCU_SDIO3		2
+#define BCM281XX_MASTER_CCU_SDIO4		3
+#define BCM281XX_MASTER_CCU_USB_IC		4
+#define BCM281XX_MASTER_CCU_HSIC2_48M		5
+#define BCM281XX_MASTER_CCU_HSIC2_12M		6
+#define BCM281XX_MASTER_CCU_CLOCK_COUNT		7
+
+/* slave CCU clock ids */
+
+#define BCM281XX_SLAVE_CCU_UARTB		0
+#define BCM281XX_SLAVE_CCU_UARTB2		1
+#define BCM281XX_SLAVE_CCU_UARTB3		2
+#define BCM281XX_SLAVE_CCU_UARTB4		3
+#define BCM281XX_SLAVE_CCU_SSP0			4
+#define BCM281XX_SLAVE_CCU_SSP2			5
+#define BCM281XX_SLAVE_CCU_BSC1			6
+#define BCM281XX_SLAVE_CCU_BSC2			7
+#define BCM281XX_SLAVE_CCU_BSC3			8
+#define BCM281XX_SLAVE_CCU_PWM			9
+#define BCM281XX_SLAVE_CCU_CLOCK_COUNT		10
+
+#endif /* _CLOCK_BCM281XX_H */

include/dt-bindings/clock/bcm2835-aux.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BCM2835_AUX_CLOCK_UART		0
+#define BCM2835_AUX_CLOCK_SPI1		1
+#define BCM2835_AUX_CLOCK_SPI2		2
+#define BCM2835_AUX_CLOCK_COUNT		3

include/dt-bindings/clock/bcm2835.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BCM2835_PLLA			0
+#define BCM2835_PLLB			1
+#define BCM2835_PLLC			2
+#define BCM2835_PLLD			3
+#define BCM2835_PLLH			4
+
+#define BCM2835_PLLA_CORE		5
+#define BCM2835_PLLA_PER		6
+#define BCM2835_PLLB_ARM		7
+#define BCM2835_PLLC_CORE0		8
+#define BCM2835_PLLC_CORE1		9
+#define BCM2835_PLLC_CORE2		10
+#define BCM2835_PLLC_PER		11
+#define BCM2835_PLLD_CORE		12
+#define BCM2835_PLLD_PER		13
+#define BCM2835_PLLH_RCAL		14
+#define BCM2835_PLLH_AUX		15
+#define BCM2835_PLLH_PIX		16
+
+#define BCM2835_CLOCK_TIMER		17
+#define BCM2835_CLOCK_OTP		18
+#define BCM2835_CLOCK_UART		19
+#define BCM2835_CLOCK_VPU		20
+#define BCM2835_CLOCK_V3D		21
+#define BCM2835_CLOCK_ISP		22
+#define BCM2835_CLOCK_H264		23
+#define BCM2835_CLOCK_VEC		24
+#define BCM2835_CLOCK_HSM		25
+#define BCM2835_CLOCK_SDRAM		26
+#define BCM2835_CLOCK_TSENS		27
+#define BCM2835_CLOCK_EMMC		28
+#define BCM2835_CLOCK_PERI_IMAGE	29
+#define BCM2835_CLOCK_PWM		30
+#define BCM2835_CLOCK_PCM		31
+
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLD_DSI0		34
+#define BCM2835_PLLD_DSI1		35
+
+#define BCM2835_CLOCK_AVEO		36
+#define BCM2835_CLOCK_DFT		37
+#define BCM2835_CLOCK_GP0		38
+#define BCM2835_CLOCK_GP1		39
+#define BCM2835_CLOCK_GP2		40
+#define BCM2835_CLOCK_SLIM		41
+#define BCM2835_CLOCK_SMI		42
+#define BCM2835_CLOCK_TEC		43
+#define BCM2835_CLOCK_DPI		44
+#define BCM2835_CLOCK_CAM0		45
+#define BCM2835_CLOCK_CAM1		46
+#define BCM2835_CLOCK_DSI0E		47
+#define BCM2835_CLOCK_DSI1E		48
+#define BCM2835_CLOCK_DSI0P		49
+#define BCM2835_CLOCK_DSI1P		50

include/dt-bindings/clock/berlin2.h

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Berlin2 BG2/BG2CD clock tree IDs
+ */
+
+#define CLKID_SYS		0
+#define CLKID_CPU		1
+#define CLKID_DRMFIGO		2
+#define CLKID_CFG		3
+#define CLKID_GFX		4
+#define CLKID_ZSP		5
+#define CLKID_PERIF		6
+#define CLKID_PCUBE		7
+#define CLKID_VSCOPE		8
+#define CLKID_NFC_ECC		9
+#define CLKID_VPP		10
+#define CLKID_APP		11
+#define CLKID_AUDIO0		12
+#define CLKID_AUDIO2		13
+#define CLKID_AUDIO3		14
+#define CLKID_AUDIO1		15
+#define CLKID_GFX3D_CORE	16
+#define CLKID_GFX3D_SYS		17
+#define CLKID_ARC		18
+#define CLKID_VIP		19
+#define CLKID_SDIO0XIN		20
+#define CLKID_SDIO1XIN		21
+#define CLKID_GFX3D_EXTRA	22
+#define CLKID_GC360		23
+#define CLKID_SDIO_DLLMST	24
+#define CLKID_GETH0		25
+#define CLKID_GETH1		26
+#define CLKID_SATA		27
+#define CLKID_AHBAPB		28
+#define CLKID_USB0		29
+#define CLKID_USB1		30
+#define CLKID_PBRIDGE		31
+#define CLKID_SDIO0		32
+#define CLKID_SDIO1		33
+#define CLKID_NFC		34
+#define CLKID_SMEMC		35
+#define CLKID_AUDIOHD		36
+#define CLKID_VIDEO0		37
+#define CLKID_VIDEO1		38
+#define CLKID_VIDEO2		39
+#define CLKID_TWD		40

include/dt-bindings/clock/berlin2q.h

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Berlin2 BG2Q clock tree IDs
+ */
+
+#define CLKID_SYS		0
+#define CLKID_DRMFIGO		1
+#define CLKID_CFG		2
+#define CLKID_GFX2D		3
+#define CLKID_ZSP		4
+#define CLKID_PERIF		5
+#define CLKID_PCUBE		6
+#define CLKID_VSCOPE		7
+#define CLKID_NFC_ECC		8
+#define CLKID_VPP		9
+#define CLKID_APP		10
+#define CLKID_SDIO0XIN		11
+#define CLKID_SDIO1XIN		12
+#define CLKID_GFX2DAXI		13
+#define CLKID_GETH0		14
+#define CLKID_SATA		15
+#define CLKID_AHBAPB		16
+#define CLKID_USB0		17
+#define CLKID_USB1		18
+#define CLKID_USB2		19
+#define CLKID_USB3		20
+#define CLKID_PBRIDGE		21
+#define CLKID_SDIO		22
+#define CLKID_NFC		23
+#define CLKID_SMEMC		24
+#define CLKID_PCIE		25
+#define CLKID_TWD		26
+#define CLKID_CPU		27

include/dt-bindings/clock/boston-clock.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_INPUT 0
+#define BOSTON_CLK_SYS 1
+#define BOSTON_CLK_CPU 2
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */

include/dt-bindings/clock/clps711x-clock.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
+#define __DT_BINDINGS_CLOCK_CLPS711X_H
+
+#define CLPS711X_CLK_DUMMY	0
+#define CLPS711X_CLK_CPU	1
+#define CLPS711X_CLK_BUS	2
+#define CLPS711X_CLK_PLL	3
+#define CLPS711X_CLK_TIMERREF	4
+#define CLPS711X_CLK_TIMER1	5
+#define CLPS711X_CLK_TIMER2	6
+#define CLPS711X_CLK_PWM	7
+#define CLPS711X_CLK_SPIREF	8
+#define CLPS711X_CLK_SPI	9
+#define CLPS711X_CLK_UART	10
+#define CLPS711X_CLK_TICK	11
+#define CLPS711X_CLK_MAX	12
+
+#endif

include/dt-bindings/clock/cortina,gemini-clock.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+
+/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */
+#define GEMINI_NUM_CLKS 20
+
+#define GEMINI_CLK_RTC 0
+#define GEMINI_CLK_AHB 1
+#define GEMINI_CLK_APB 2
+#define GEMINI_CLK_CPU 3
+#define GEMINI_CLK_PCI 4
+#define GEMINI_CLK_TVC 5
+#define GEMINI_CLK_UART 6
+#define GEMINI_CLK_GATES 7
+#define GEMINI_CLK_GATE_SECURITY 7
+#define GEMINI_CLK_GATE_GMAC0 8
+#define GEMINI_CLK_GATE_GMAC1 9
+#define GEMINI_CLK_GATE_SATA0 10
+#define GEMINI_CLK_GATE_SATA1 11
+#define GEMINI_CLK_GATE_USB0 12
+#define GEMINI_CLK_GATE_USB1 13
+#define GEMINI_CLK_GATE_IDE 14
+#define GEMINI_CLK_GATE_PCI 15
+#define GEMINI_CLK_GATE_DDR 16
+#define GEMINI_CLK_GATE_FLASH 17
+#define GEMINI_CLK_GATE_TVC 18
+#define GEMINI_CLK_GATE_BOOT 19
+
+#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */

include/dt-bindings/clock/dm814.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM814_H
+#define __DT_BINDINGS_CLK_DM814_H
+
+#define DM814_CLKCTRL_OFFSET	0x0
+#define DM814_CLKCTRL_INDEX(offset)	((offset) - DM814_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM814_USB_OTG_HS_CLKCTRL	DM814_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM814_UART1_CLKCTRL	DM814_CLKCTRL_INDEX(0x150)
+#define DM814_UART2_CLKCTRL	DM814_CLKCTRL_INDEX(0x154)
+#define DM814_UART3_CLKCTRL	DM814_CLKCTRL_INDEX(0x158)
+#define DM814_GPIO1_CLKCTRL	DM814_CLKCTRL_INDEX(0x15c)
+#define DM814_GPIO2_CLKCTRL	DM814_CLKCTRL_INDEX(0x160)
+#define DM814_I2C1_CLKCTRL	DM814_CLKCTRL_INDEX(0x164)
+#define DM814_I2C2_CLKCTRL	DM814_CLKCTRL_INDEX(0x168)
+#define DM814_WD_TIMER_CLKCTRL	DM814_CLKCTRL_INDEX(0x18c)
+#define DM814_MCSPI1_CLKCTRL	DM814_CLKCTRL_INDEX(0x190)
+#define DM814_GPMC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d0)
+#define DM814_CPGMAC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d4)
+#define DM814_MPU_CLKCTRL	DM814_CLKCTRL_INDEX(0x1dc)
+#define DM814_RTC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f0)
+#define DM814_TPCC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f4)
+#define DM814_TPTC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f8)
+#define DM814_TPTC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x1fc)
+#define DM814_TPTC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x200)
+#define DM814_TPTC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x204)
+#define DM814_MMC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x21c)
+#define DM814_MMC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x220)
+#define DM814_MMC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x224)
+
+#endif

include/dt-bindings/clock/dm816.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM816_H
+#define __DT_BINDINGS_CLK_DM816_H
+
+#define DM816_CLKCTRL_OFFSET	0x0
+#define DM816_CLKCTRL_INDEX(offset)	((offset) - DM816_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM816_USB_OTG_HS_CLKCTRL	DM816_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM816_UART1_CLKCTRL	DM816_CLKCTRL_INDEX(0x150)
+#define DM816_UART2_CLKCTRL	DM816_CLKCTRL_INDEX(0x154)
+#define DM816_UART3_CLKCTRL	DM816_CLKCTRL_INDEX(0x158)
+#define DM816_GPIO1_CLKCTRL	DM816_CLKCTRL_INDEX(0x15c)
+#define DM816_GPIO2_CLKCTRL	DM816_CLKCTRL_INDEX(0x160)
+#define DM816_I2C1_CLKCTRL	DM816_CLKCTRL_INDEX(0x164)
+#define DM816_I2C2_CLKCTRL	DM816_CLKCTRL_INDEX(0x168)
+#define DM816_TIMER1_CLKCTRL	DM816_CLKCTRL_INDEX(0x170)
+#define DM816_TIMER2_CLKCTRL	DM816_CLKCTRL_INDEX(0x174)
+#define DM816_TIMER3_CLKCTRL	DM816_CLKCTRL_INDEX(0x178)
+#define DM816_TIMER4_CLKCTRL	DM816_CLKCTRL_INDEX(0x17c)
+#define DM816_TIMER5_CLKCTRL	DM816_CLKCTRL_INDEX(0x180)
+#define DM816_TIMER6_CLKCTRL	DM816_CLKCTRL_INDEX(0x184)
+#define DM816_TIMER7_CLKCTRL	DM816_CLKCTRL_INDEX(0x188)
+#define DM816_WD_TIMER_CLKCTRL	DM816_CLKCTRL_INDEX(0x18c)
+#define DM816_MCSPI1_CLKCTRL	DM816_CLKCTRL_INDEX(0x190)
+#define DM816_MAILBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x194)
+#define DM816_SPINBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x198)
+#define DM816_MMC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1b0)
+#define DM816_GPMC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d0)
+#define DM816_DAVINCI_MDIO_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d4)
+#define DM816_EMAC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d8)
+#define DM816_MPU_CLKCTRL	DM816_CLKCTRL_INDEX(0x1dc)
+#define DM816_RTC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f0)
+#define DM816_TPCC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f4)
+#define DM816_TPTC0_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f8)
+#define DM816_TPTC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1fc)
+#define DM816_TPTC2_CLKCTRL	DM816_CLKCTRL_INDEX(0x200)
+#define DM816_TPTC3_CLKCTRL	DM816_CLKCTRL_INDEX(0x204)
+
+#endif

include/dt-bindings/clock/dra7.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DRA7_H
+#define __DT_BINDINGS_CLK_DRA7_H
+
+#define DRA7_CLKCTRL_OFFSET	0x20
+#define DRA7_CLKCTRL_INDEX(offset)	((offset) - DRA7_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define DRA7_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define DRA7_IPU_CLKCTRL_OFFSET	0x40
+#define DRA7_IPU_CLKCTRL_INDEX(offset)	((offset) - DRA7_IPU_CLKCTRL_OFFSET)
+#define DRA7_MCASP1_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x50)
+#define DRA7_TIMER5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x58)
+#define DRA7_TIMER6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x60)
+#define DRA7_TIMER7_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x68)
+#define DRA7_TIMER8_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x70)
+#define DRA7_I2C5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x78)
+#define DRA7_UART6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x80)
+
+/* rtc clocks */
+#define DRA7_RTC_CLKCTRL_OFFSET	0x40
+#define DRA7_RTC_CLKCTRL_INDEX(offset)	((offset) - DRA7_RTC_CLKCTRL_OFFSET)
+#define DRA7_RTCSS_CLKCTRL	DRA7_RTC_CLKCTRL_INDEX(0x44)
+
+/* coreaon clocks */
+#define DRA7_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
+
+/* l3main1 clocks */
+#define DRA7_L3_MAIN_1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_GPMC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_TPCC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_TPTC0_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_TPTC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_VCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_VCP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
+
+/* dma clocks */
+#define DRA7_DMA_SYSTEM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define DRA7_DMM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* atl clocks */
+#define DRA7_ATL_CLKCTRL_OFFSET	0x0
+#define DRA7_ATL_CLKCTRL_INDEX(offset)	((offset) - DRA7_ATL_CLKCTRL_OFFSET)
+#define DRA7_ATL_CLKCTRL	DRA7_ATL_CLKCTRL_INDEX(0x0)
+
+/* l4cfg clocks */
+#define DRA7_L4_CFG_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_SPINLOCK_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MAILBOX1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_MAILBOX2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_MAILBOX3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_MAILBOX4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x58)
+#define DRA7_MAILBOX5_CLKCTRL	DRA7_CLKCTRL_INDEX(0x60)
+#define DRA7_MAILBOX6_CLKCTRL	DRA7_CLKCTRL_INDEX(0x68)
+#define DRA7_MAILBOX7_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_MAILBOX8_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_MAILBOX9_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_MAILBOX10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_MAILBOX11_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
+#define DRA7_MAILBOX12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x98)
+#define DRA7_MAILBOX13_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
+
+/* l3instr clocks */
+#define DRA7_L3_MAIN_2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L3_INSTR_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define DRA7_DSS_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_BB2D_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+
+/* l3init clocks */
+#define DRA7_MMC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MMC2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_USB_OTG_SS2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_USB_OTG_SS3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_USB_OTG_SS4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_SATA_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_PCIE1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xb0)
+#define DRA7_PCIE2_CLKCTRL	DRA7_CLKCTRL_INDEX(0xb8)
+#define DRA7_GMAC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xd0)
+#define DRA7_OCP2SCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe0)
+#define DRA7_OCP2SCP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe8)
+#define DRA7_USB_OTG_SS1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xf0)
+
+/* l4per clocks */
+#define DRA7_L4PER_CLKCTRL_OFFSET	0x0
+#define DRA7_L4PER_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
+#define DRA7_L4_PER2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc)
+#define DRA7_L4_PER3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x14)
+#define DRA7_TIMER10_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x28)
+#define DRA7_TIMER11_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x30)
+#define DRA7_TIMER2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x48)
+#define DRA7_TIMER9_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x50)
+#define DRA7_ELM_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x58)
+#define DRA7_GPIO2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x60)
+#define DRA7_GPIO3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x68)
+#define DRA7_GPIO4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x70)
+#define DRA7_GPIO5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x78)
+#define DRA7_GPIO6_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x80)
+#define DRA7_HDQ1W_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x88)
+#define DRA7_EPWMSS1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x90)
+#define DRA7_EPWMSS2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x98)
+#define DRA7_I2C1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa0)
+#define DRA7_I2C2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa8)
+#define DRA7_I2C3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb0)
+#define DRA7_I2C4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb8)
+#define DRA7_L4_PER1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc0)
+#define DRA7_EPWMSS0_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc4)
+#define DRA7_TIMER13_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc8)
+#define DRA7_TIMER14_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xd0)
+#define DRA7_TIMER15_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xd8)
+#define DRA7_MCSPI1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf0)
+#define DRA7_MCSPI2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf8)
+#define DRA7_MCSPI3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x100)
+#define DRA7_MCSPI4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x108)
+#define DRA7_GPIO7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x110)
+#define DRA7_GPIO8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x118)
+#define DRA7_MMC3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x120)
+#define DRA7_MMC4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x128)
+#define DRA7_TIMER16_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x130)
+#define DRA7_QSPI_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x138)
+#define DRA7_UART1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x140)
+#define DRA7_UART2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x148)
+#define DRA7_UART3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x150)
+#define DRA7_UART4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x158)
+#define DRA7_MCASP2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x160)
+#define DRA7_MCASP3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x168)
+#define DRA7_UART5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x170)
+#define DRA7_MCASP5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x178)
+#define DRA7_MCASP8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x190)
+#define DRA7_MCASP4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x198)
+#define DRA7_AES1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
+#define DRA7_AES2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
+#define DRA7_DES_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
+#define DRA7_RNG_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
+#define DRA7_SHAM_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
+#define DRA7_UART7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
+#define DRA7_UART8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
+#define DRA7_UART9_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
+#define DRA7_DCAN2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
+#define DRA7_MCASP6_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x204)
+#define DRA7_MCASP7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x208)
+
+/* wkupaon clocks */
+#define DRA7_L4_WKUP_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_WD_TIMER2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_GPIO1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_COUNTER_32K_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_UART10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_DCAN1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_ADC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
+
+#endif

include/dt-bindings/clock/efm32-cmu.h

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
+#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
+
+#define clk_HFXO		0
+#define clk_HFRCO		1
+#define clk_LFXO		2
+#define clk_LFRCO		3
+#define clk_ULFRCO		4
+#define clk_AUXHFRCO		5
+#define clk_HFCLKNODIV		6
+#define clk_HFCLK		7
+#define clk_HFPERCLK		8
+#define clk_HFCORECLK		9
+#define clk_LFACLK		10
+#define clk_LFBCLK		11
+#define clk_WDOGCLK		12
+#define clk_HFCORECLKDMA	13
+#define clk_HFCORECLKAES	14
+#define clk_HFCORECLKUSBC	15
+#define clk_HFCORECLKUSB	16
+#define clk_HFCORECLKLE		17
+#define clk_HFCORECLKEBI	18
+#define clk_HFPERCLKUSART0	19
+#define clk_HFPERCLKUSART1	20
+#define clk_HFPERCLKUSART2	21
+#define clk_HFPERCLKUART0	22
+#define clk_HFPERCLKUART1	23
+#define clk_HFPERCLKTIMER0	24
+#define clk_HFPERCLKTIMER1	25
+#define clk_HFPERCLKTIMER2	26
+#define clk_HFPERCLKTIMER3	27
+#define clk_HFPERCLKACMP0	28
+#define clk_HFPERCLKACMP1	29
+#define clk_HFPERCLKI2C0	30
+#define clk_HFPERCLKI2C1	31
+#define clk_HFPERCLKGPIO	32
+#define clk_HFPERCLKVCMP	33
+#define clk_HFPERCLKPRS		34
+#define clk_HFPERCLKADC0	35
+#define clk_HFPERCLKDAC0	36
+
+#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */

include/dt-bindings/clock/exynos-audss-clk.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS	0
+#define EXYNOS_MOUT_I2S	1
+#define EXYNOS_DOUT_SRP	2
+#define EXYNOS_DOUT_AUD_BUS	3
+#define EXYNOS_DOUT_I2S	4
+#define EXYNOS_SRP_CLK		5
+#define EXYNOS_I2S_BUS		6
+#define EXYNOS_SCLK_I2S	7
+#define EXYNOS_PCM_BUS		8
+#define EXYNOS_SCLK_PCM	9
+#define EXYNOS_ADMA		10
+
+#define EXYNOS_AUDSS_MAX_CLKS	11
+
+#endif

include/dt-bindings/clock/exynos3250.h

@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * 	Author: Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos3250 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL			1
+#define CLK_FIN_PLL			2
+#define CLK_FOUT_APLL			3
+#define CLK_FOUT_VPLL			4
+#define CLK_FOUT_UPLL			5
+#define CLK_FOUT_MPLL			6
+#define CLK_ARM_CLK			7
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L		16
+#define CLK_MOUT_GDL			17
+#define CLK_MOUT_MPLL_USER_R		18
+#define CLK_MOUT_GDR			19
+#define CLK_MOUT_EBI			20
+#define CLK_MOUT_ACLK_200		21
+#define CLK_MOUT_ACLK_160		22
+#define CLK_MOUT_ACLK_100		23
+#define CLK_MOUT_ACLK_266_1		24
+#define CLK_MOUT_ACLK_266_0		25
+#define CLK_MOUT_ACLK_266		26
+#define CLK_MOUT_VPLL			27
+#define CLK_MOUT_EPLL_USER		28
+#define CLK_MOUT_EBI_1			29
+#define CLK_MOUT_UPLL			30
+#define CLK_MOUT_ACLK_400_MCUISP_SUB	31
+#define CLK_MOUT_MPLL			32
+#define CLK_MOUT_ACLK_400_MCUISP	33
+#define CLK_MOUT_VPLLSRC		34
+#define CLK_MOUT_CAM1			35
+#define CLK_MOUT_CAM_BLK		36
+#define CLK_MOUT_MFC			37
+#define CLK_MOUT_MFC_1			38
+#define CLK_MOUT_MFC_0			39
+#define CLK_MOUT_G3D			40
+#define CLK_MOUT_G3D_1			41
+#define CLK_MOUT_G3D_0			42
+#define CLK_MOUT_MIPI0			43
+#define CLK_MOUT_FIMD0			44
+#define CLK_MOUT_UART_ISP		45
+#define CLK_MOUT_SPI1_ISP		46
+#define CLK_MOUT_SPI0_ISP		47
+#define CLK_MOUT_TSADC			48
+#define CLK_MOUT_MMC1			49
+#define CLK_MOUT_MMC0			50
+#define CLK_MOUT_UART1			51
+#define CLK_MOUT_UART0			52
+#define CLK_MOUT_SPI1			53
+#define CLK_MOUT_SPI0			54
+#define CLK_MOUT_AUDIO			55
+#define CLK_MOUT_MPLL_USER_C		56
+#define CLK_MOUT_HPM			57
+#define CLK_MOUT_CORE			58
+#define CLK_MOUT_APLL			59
+#define CLK_MOUT_ACLK_266_SUB		60
+#define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
+
+/* Dividers */
+#define CLK_DIV_GPL			64
+#define CLK_DIV_GDL			65
+#define CLK_DIV_GPR			66
+#define CLK_DIV_GDR			67
+#define CLK_DIV_MPLL_PRE		68
+#define CLK_DIV_ACLK_400_MCUISP		69
+#define CLK_DIV_EBI			70
+#define CLK_DIV_ACLK_200		71
+#define CLK_DIV_ACLK_160		72
+#define CLK_DIV_ACLK_100		73
+#define CLK_DIV_ACLK_266		74
+#define CLK_DIV_CAM1			75
+#define CLK_DIV_CAM_BLK			76
+#define CLK_DIV_MFC			77
+#define CLK_DIV_G3D			78
+#define CLK_DIV_MIPI0_PRE		79
+#define CLK_DIV_MIPI0			80
+#define CLK_DIV_FIMD0			81
+#define CLK_DIV_UART_ISP		82
+#define CLK_DIV_SPI1_ISP_PRE		83
+#define CLK_DIV_SPI1_ISP		84
+#define CLK_DIV_SPI0_ISP_PRE		85
+#define CLK_DIV_SPI0_ISP		86
+#define CLK_DIV_TSADC_PRE		87
+#define CLK_DIV_TSADC			88
+#define CLK_DIV_MMC1_PRE		89
+#define CLK_DIV_MMC1			90
+#define CLK_DIV_MMC0_PRE		91
+#define CLK_DIV_MMC0			92
+#define CLK_DIV_UART1			93
+#define CLK_DIV_UART0			94
+#define CLK_DIV_SPI1_PRE		95
+#define CLK_DIV_SPI1			96
+#define CLK_DIV_SPI0_PRE		97
+#define CLK_DIV_SPI0			98
+#define CLK_DIV_PCM			99
+#define CLK_DIV_AUDIO			100
+#define CLK_DIV_I2S			101
+#define CLK_DIV_CORE2			102
+#define CLK_DIV_APLL			103
+#define CLK_DIV_PCLK_DBG		104
+#define CLK_DIV_ATB			105
+#define CLK_DIV_COREM			106
+#define CLK_DIV_CORE			107
+#define CLK_DIV_HPM			108
+#define CLK_DIV_COPY			109
+#define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
+
+/* Gates */
+#define CLK_ASYNC_G3D			128
+#define CLK_ASYNC_MFCL			129
+#define CLK_PPMULEFT			130
+#define CLK_GPIO_LEFT			131
+#define CLK_ASYNC_ISPMX			132
+#define CLK_ASYNC_FSYSD			133
+#define CLK_ASYNC_LCD0X			134
+#define CLK_ASYNC_CAMX			135
+#define CLK_PPMURIGHT			136
+#define CLK_GPIO_RIGHT			137
+#define CLK_MONOCNT			138
+#define CLK_TZPC6			139
+#define CLK_PROVISIONKEY1		140
+#define CLK_PROVISIONKEY0		141
+#define CLK_CMU_ISPPART			142
+#define CLK_TMU_APBIF			143
+#define CLK_KEYIF			144
+#define CLK_RTC				145
+#define CLK_WDT				146
+#define CLK_MCT				147
+#define CLK_SECKEY			148
+#define CLK_TZPC5			149
+#define CLK_TZPC4			150
+#define CLK_TZPC3			151
+#define CLK_TZPC2			152
+#define CLK_TZPC1			153
+#define CLK_TZPC0			154
+#define CLK_CMU_COREPART		155
+#define CLK_CMU_TOPPART			156
+#define CLK_PMU_APBIF			157
+#define CLK_SYSREG			158
+#define CLK_CHIP_ID			159
+#define CLK_QEJPEG			160
+#define CLK_PIXELASYNCM1		161
+#define CLK_PIXELASYNCM0		162
+#define CLK_PPMUCAMIF			163
+#define CLK_QEM2MSCALER			164
+#define CLK_QEGSCALER1			165
+#define CLK_QEGSCALER0			166
+#define CLK_SMMUJPEG			167
+#define CLK_SMMUM2M2SCALER		168
+#define CLK_SMMUGSCALER1		169
+#define CLK_SMMUGSCALER0		170
+#define CLK_JPEG			171
+#define CLK_M2MSCALER			172
+#define CLK_GSCALER1			173
+#define CLK_GSCALER0			174
+#define CLK_QEMFC			175
+#define CLK_PPMUMFC_L			176
+#define CLK_SMMUMFC_L			177
+#define CLK_MFC				178
+#define CLK_SMMUG3D			179
+#define CLK_QEG3D			180
+#define CLK_PPMUG3D			181
+#define CLK_G3D				182
+#define CLK_QE_CH1_LCD			183
+#define CLK_QE_CH0_LCD			184
+#define CLK_PPMULCD0			185
+#define CLK_SMMUFIMD0			186
+#define CLK_DSIM0			187
+#define CLK_FIMD0			188
+#define CLK_CAM1			189
+#define CLK_UART_ISP_TOP		190
+#define CLK_SPI1_ISP_TOP		191
+#define CLK_SPI0_ISP_TOP		192
+#define CLK_TSADC			193
+#define CLK_PPMUFILE			194
+#define CLK_USBOTG			195
+#define CLK_USBHOST			196
+#define CLK_SROMC			197
+#define CLK_SDMMC1			198
+#define CLK_SDMMC0			199
+#define CLK_PDMA1			200
+#define CLK_PDMA0			201
+#define CLK_PWM				202
+#define CLK_PCM				203
+#define CLK_I2S				204
+#define CLK_SPI1			205
+#define CLK_SPI0			206
+#define CLK_I2C7			207
+#define CLK_I2C6			208
+#define CLK_I2C5			209
+#define CLK_I2C4			210
+#define CLK_I2C3			211
+#define CLK_I2C2			212
+#define CLK_I2C1			213
+#define CLK_I2C0			214
+#define CLK_UART1			215
+#define CLK_UART0			216
+#define CLK_BLOCK_LCD			217
+#define CLK_BLOCK_G3D			218
+#define CLK_BLOCK_MFC			219
+#define CLK_BLOCK_CAM			220
+#define CLK_SMIES			221
+#define CLK_UART2			222
+#define CLK_SDMMC2			223
+
+/* Special clocks */
+#define CLK_SCLK_JPEG			224
+#define CLK_SCLK_M2MSCALER		225
+#define CLK_SCLK_GSCALER1		226
+#define CLK_SCLK_GSCALER0		227
+#define CLK_SCLK_MFC			228
+#define CLK_SCLK_G3D			229
+#define CLK_SCLK_MIPIDPHY2L		230
+#define CLK_SCLK_MIPI0			231
+#define CLK_SCLK_FIMD0			232
+#define CLK_SCLK_CAM1			233
+#define CLK_SCLK_UART_ISP		234
+#define CLK_SCLK_SPI1_ISP		235
+#define CLK_SCLK_SPI0_ISP		236
+#define CLK_SCLK_UPLL			237
+#define CLK_SCLK_TSADC			238
+#define CLK_SCLK_EBI			239
+#define CLK_SCLK_MMC1			240
+#define CLK_SCLK_MMC0			241
+#define CLK_SCLK_I2S			242
+#define CLK_SCLK_PCM			243
+#define CLK_SCLK_SPI1			244
+#define CLK_SCLK_SPI0			245
+#define CLK_SCLK_UART1			246
+#define CLK_SCLK_UART0			247
+#define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS			250
+
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL			1
+#define CLK_FOUT_EPLL			2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF		8
+#define CLK_MOUT_BPLL			9
+#define CLK_MOUT_DPHY			10
+#define CLK_MOUT_DMC_BUS		11
+#define CLK_MOUT_EPLL			12
+
+/* Dividers */
+#define CLK_DIV_DMC			16
+#define CLK_DIV_DPHY			17
+#define CLK_DIV_DMC_PRE			18
+#define CLK_DIV_DMCP			19
+#define CLK_DIV_DMCD			20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC			21
+
+/*
+ * CMU ISP
+ */
+
+/* Dividers */
+
+#define CLK_DIV_ISP1			1
+#define CLK_DIV_ISP0			2
+#define CLK_DIV_MCUISP1			3
+#define CLK_DIV_MCUISP0			4
+#define CLK_DIV_MPWM			5
+
+/* Gates */
+
+#define CLK_UART_ISP			8
+#define CLK_WDT_ISP			9
+#define CLK_PWM_ISP			10
+#define CLK_I2C1_ISP			11
+#define CLK_I2C0_ISP			12
+#define CLK_MPWM_ISP			13
+#define CLK_MCUCTL_ISP			14
+#define CLK_PPMUISPX			15
+#define CLK_PPMUISPMX			16
+#define CLK_QE_LITE1			17
+#define CLK_QE_LITE0			18
+#define CLK_QE_FD			19
+#define CLK_QE_DRC			20
+#define CLK_QE_ISP			21
+#define CLK_CSIS1			22
+#define CLK_SMMU_LITE1			23
+#define CLK_SMMU_LITE0			24
+#define CLK_SMMU_FD			25
+#define CLK_SMMU_DRC			26
+#define CLK_SMMU_ISP			27
+#define CLK_GICISP			28
+#define CLK_CSIS0			29
+#define CLK_MCUISP			30
+#define CLK_LITE1			31
+#define CLK_LITE0			32
+#define CLK_FD				33
+#define CLK_DRC				34
+#define CLK_ISP				35
+#define CLK_QE_ISPCX			36
+#define CLK_QE_SCALERP			37
+#define CLK_QE_SCALERC			38
+#define CLK_SMMU_SCALERP		39
+#define CLK_SMMU_SCALERC		40
+#define CLK_SCALERP			41
+#define CLK_SCALERC			42
+#define CLK_SPI1_ISP			43
+#define CLK_SPI0_ISP			44
+#define CLK_SMMU_ISPCX			45
+#define CLK_ASYNCAXIM			46
+#define CLK_SCLK_MPWM_ISP		47
+
+/*
+ * Total number of clocks of CMU_ISP.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_ISP			48
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

include/dt-bindings/clock/exynos4.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos4 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
+
+/* core clocks */
+#define CLK_XXTI		1
+#define CLK_XUSBXTI		2
+#define CLK_FIN_PLL		3
+#define CLK_FOUT_APLL		4
+#define CLK_FOUT_MPLL		5
+#define CLK_FOUT_EPLL		6
+#define CLK_FOUT_VPLL		7
+#define CLK_SCLK_APLL		8
+#define CLK_SCLK_MPLL		9
+#define CLK_SCLK_EPLL		10
+#define CLK_SCLK_VPLL		11
+#define CLK_ARM_CLK		12
+#define CLK_ACLK200		13
+#define CLK_ACLK100		14
+#define CLK_ACLK160		15
+#define CLK_ACLK133		16
+#define CLK_MOUT_MPLL_USER_T	17 /* Exynos4x12 only */
+#define CLK_MOUT_MPLL_USER_C	18 /* Exynos4x12 only */
+#define CLK_MOUT_CORE		19
+#define CLK_MOUT_APLL		20
+#define CLK_SCLK_HDMIPHY	22
+#define CLK_OUT_DMC		23
+#define CLK_OUT_TOP		24
+#define CLK_OUT_LEFTBUS		25
+#define CLK_OUT_RIGHTBUS	26
+#define CLK_OUT_CPU		27
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_FIMC0		128
+#define CLK_SCLK_FIMC1		129
+#define CLK_SCLK_FIMC2		130
+#define CLK_SCLK_FIMC3		131
+#define CLK_SCLK_CAM0		132
+#define CLK_SCLK_CAM1		133
+#define CLK_SCLK_CSIS0		134
+#define CLK_SCLK_CSIS1		135
+#define CLK_SCLK_HDMI		136
+#define CLK_SCLK_MIXER		137
+#define CLK_SCLK_DAC		138
+#define CLK_SCLK_PIXEL		139
+#define CLK_SCLK_FIMD0		140
+#define CLK_SCLK_MDNIE0		141 /* Exynos4412 only */
+#define CLK_SCLK_MDNIE_PWM0	142
+#define CLK_SCLK_MIPI0		143
+#define CLK_SCLK_AUDIO0		144
+#define CLK_SCLK_MMC0		145
+#define CLK_SCLK_MMC1		146
+#define CLK_SCLK_MMC2		147
+#define CLK_SCLK_MMC3		148
+#define CLK_SCLK_MMC4		149
+#define CLK_SCLK_SATA		150 /* Exynos4210 only */
+#define CLK_SCLK_UART0		151
+#define CLK_SCLK_UART1		152
+#define CLK_SCLK_UART2		153
+#define CLK_SCLK_UART3		154
+#define CLK_SCLK_UART4		155
+#define CLK_SCLK_AUDIO1		156
+#define CLK_SCLK_AUDIO2		157
+#define CLK_SCLK_SPDIF		158
+#define CLK_SCLK_SPI0		159
+#define CLK_SCLK_SPI1		160
+#define CLK_SCLK_SPI2		161
+#define CLK_SCLK_SLIMBUS	162
+#define CLK_SCLK_FIMD1		163 /* Exynos4210 only */
+#define CLK_SCLK_MIPI1		164 /* Exynos4210 only */
+#define CLK_SCLK_PCM1		165
+#define CLK_SCLK_PCM2		166
+#define CLK_SCLK_I2S1		167
+#define CLK_SCLK_I2S2		168
+#define CLK_SCLK_MIPIHSI	169 /* Exynos4412 only */
+#define CLK_SCLK_MFC		170
+#define CLK_SCLK_PCM0		171
+#define CLK_SCLK_G3D		172
+#define CLK_SCLK_PWM_ISP	173 /* Exynos4x12 only */
+#define CLK_SCLK_SPI0_ISP	174 /* Exynos4x12 only */
+#define CLK_SCLK_SPI1_ISP	175 /* Exynos4x12 only */
+#define CLK_SCLK_UART_ISP	176 /* Exynos4x12 only */
+#define CLK_SCLK_FIMG2D		177
+
+/* gate clocks */
+#define CLK_SSS			255
+#define CLK_FIMC0		256
+#define CLK_FIMC1		257
+#define CLK_FIMC2		258
+#define CLK_FIMC3		259
+#define CLK_CSIS0		260
+#define CLK_CSIS1		261
+#define CLK_JPEG		262
+#define CLK_SMMU_FIMC0		263
+#define CLK_SMMU_FIMC1		264
+#define CLK_SMMU_FIMC2		265
+#define CLK_SMMU_FIMC3		266
+#define CLK_SMMU_JPEG		267
+#define CLK_VP			268
+#define CLK_MIXER		269
+#define CLK_TVENC		270 /* Exynos4210 only */
+#define CLK_HDMI		271
+#define CLK_SMMU_TV		272
+#define CLK_MFC			273
+#define CLK_SMMU_MFCL		274
+#define CLK_SMMU_MFCR		275
+#define CLK_G3D			276
+#define CLK_G2D			277
+#define CLK_ROTATOR		278
+#define CLK_MDMA		279
+#define CLK_SMMU_G2D		280
+#define CLK_SMMU_ROTATOR	281
+#define CLK_SMMU_MDMA		282
+#define CLK_FIMD0		283
+#define CLK_MIE0		284
+#define CLK_MDNIE0		285 /* Exynos4412 only */
+#define CLK_DSIM0		286
+#define CLK_SMMU_FIMD0		287
+#define CLK_FIMD1		288 /* Exynos4210 only */
+#define CLK_MIE1		289 /* Exynos4210 only */
+#define CLK_DSIM1		290 /* Exynos4210 only */
+#define CLK_SMMU_FIMD1		291 /* Exynos4210 only */
+#define CLK_PDMA0		292
+#define CLK_PDMA1		293
+#define CLK_PCIE_PHY		294
+#define CLK_SATA_PHY		295 /* Exynos4210 only */
+#define CLK_TSI			296
+#define CLK_SDMMC0		297
+#define CLK_SDMMC1		298
+#define CLK_SDMMC2		299
+#define CLK_SDMMC3		300
+#define CLK_SDMMC4		301
+#define CLK_SATA		302 /* Exynos4210 only */
+#define CLK_SROMC		303
+#define CLK_USB_HOST		304
+#define CLK_USB_DEVICE		305
+#define CLK_PCIE		306
+#define CLK_ONENAND		307
+#define CLK_NFCON		308
+#define CLK_SMMU_PCIE		309
+#define CLK_GPS			310
+#define CLK_SMMU_GPS		311
+#define CLK_UART0		312
+#define CLK_UART1		313
+#define CLK_UART2		314
+#define CLK_UART3		315
+#define CLK_UART4		316
+#define CLK_I2C0		317
+#define CLK_I2C1		318
+#define CLK_I2C2		319
+#define CLK_I2C3		320
+#define CLK_I2C4		321
+#define CLK_I2C5		322
+#define CLK_I2C6		323
+#define CLK_I2C7		324
+#define CLK_I2C_HDMI		325
+#define CLK_TSADC		326
+#define CLK_SPI0		327
+#define CLK_SPI1		328
+#define CLK_SPI2		329
+#define CLK_I2S1		330
+#define CLK_I2S2		331
+#define CLK_PCM0		332
+#define CLK_I2S0		333
+#define CLK_PCM1		334
+#define CLK_PCM2		335
+#define CLK_PWM			336
+#define CLK_SLIMBUS		337
+#define CLK_SPDIF		338
+#define CLK_AC97		339
+#define CLK_MODEMIF		340
+#define CLK_CHIPID		341
+#define CLK_SYSREG		342
+#define CLK_HDMI_CEC		343
+#define CLK_MCT			344
+#define CLK_WDT			345
+#define CLK_RTC			346
+#define CLK_KEYIF		347
+#define CLK_AUDSS		348
+#define CLK_MIPI_HSI		349 /* Exynos4210 only */
+#define CLK_PIXELASYNCM0	351
+#define CLK_PIXELASYNCM1	352
+#define CLK_FIMC_LITE0		353 /* Exynos4x12 only */
+#define CLK_FIMC_LITE1		354 /* Exynos4x12 only */
+#define CLK_PPMUISPX		355 /* Exynos4x12 only */
+#define CLK_PPMUISPMX		356 /* Exynos4x12 only */
+#define CLK_FIMC_ISP		357 /* Exynos4x12 only */
+#define CLK_FIMC_DRC		358 /* Exynos4x12 only */
+#define CLK_FIMC_FD		359 /* Exynos4x12 only */
+#define CLK_MCUISP		360 /* Exynos4x12 only */
+#define CLK_GICISP		361 /* Exynos4x12 only */
+#define CLK_SMMU_ISP		362 /* Exynos4x12 only */
+#define CLK_SMMU_DRC		363 /* Exynos4x12 only */
+#define CLK_SMMU_FD		364 /* Exynos4x12 only */
+#define CLK_SMMU_LITE0		365 /* Exynos4x12 only */
+#define CLK_SMMU_LITE1		366 /* Exynos4x12 only */
+#define CLK_MCUCTL_ISP		367 /* Exynos4x12 only */
+#define CLK_MPWM_ISP		368 /* Exynos4x12 only */
+#define CLK_I2C0_ISP		369 /* Exynos4x12 only */
+#define CLK_I2C1_ISP		370 /* Exynos4x12 only */
+#define CLK_MTCADC_ISP		371 /* Exynos4x12 only */
+#define CLK_PWM_ISP		372 /* Exynos4x12 only */
+#define CLK_WDT_ISP		373 /* Exynos4x12 only */
+#define CLK_UART_ISP		374 /* Exynos4x12 only */
+#define CLK_ASYNCAXIM		375 /* Exynos4x12 only */
+#define CLK_SMMU_ISPCX		376 /* Exynos4x12 only */
+#define CLK_SPI0_ISP		377 /* Exynos4x12 only */
+#define CLK_SPI1_ISP		378 /* Exynos4x12 only */
+#define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */
+#define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */
+#define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */
+#define CLK_UART_ISP_SCLK	382 /* Exynos4x12 only */
+#define CLK_TMU_APBIF		383
+
+/* mux clocks */
+#define CLK_MOUT_FIMC0		384
+#define CLK_MOUT_FIMC1		385
+#define CLK_MOUT_FIMC2		386
+#define CLK_MOUT_FIMC3		387
+#define CLK_MOUT_CAM0		388
+#define CLK_MOUT_CAM1		389
+#define CLK_MOUT_CSIS0		390
+#define CLK_MOUT_CSIS1		391
+#define CLK_MOUT_G3D0		392
+#define CLK_MOUT_G3D1		393
+#define CLK_MOUT_G3D		394
+#define CLK_ACLK400_MCUISP	395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI		396
+#define CLK_MOUT_MIXER		397
+
+/* gate clocks - ppmu */
+#define CLK_PPMULEFT		400
+#define CLK_PPMURIGHT		401
+#define CLK_PPMUCAMIF		402
+#define CLK_PPMUTV		403
+#define CLK_PPMUMFC_L		404
+#define CLK_PPMUMFC_R		405
+#define CLK_PPMUG3D		406
+#define CLK_PPMUIMAGE		407
+#define CLK_PPMULCD0		408
+#define CLK_PPMULCD1		409 /* Exynos4210 only */
+#define CLK_PPMUFILE		410
+#define CLK_PPMUGPS		411
+#define CLK_PPMUDMC0		412
+#define CLK_PPMUDMC1		413
+#define CLK_PPMUCPU		414
+#define CLK_PPMUACP		415
+
+/* div clocks */
+#define CLK_DIV_ISP0		450 /* Exynos4x12 only */
+#define CLK_DIV_ISP1		451 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP0		452 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP1		453 /* Exynos4x12 only */
+#define CLK_DIV_ACLK200		454 /* Exynos4x12 only */
+#define CLK_DIV_ACLK400_MCUISP	455 /* Exynos4x12 only */
+#define CLK_DIV_ACP		456
+#define CLK_DIV_DMC		457
+#define CLK_DIV_C2C		458 /* Exynos4x12 only */
+#define CLK_DIV_GDL		459
+#define CLK_DIV_GDR		460
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS		461
+
+/* Exynos4x12 ISP clocks */
+#define CLK_ISP_FIMC_ISP		 1
+#define CLK_ISP_FIMC_DRC		 2
+#define CLK_ISP_FIMC_FD			 3
+#define CLK_ISP_FIMC_LITE0		 4
+#define CLK_ISP_FIMC_LITE1		 5
+#define CLK_ISP_MCUISP			 6
+#define CLK_ISP_GICISP			 7
+#define CLK_ISP_SMMU_ISP		 8
+#define CLK_ISP_SMMU_DRC		 9
+#define CLK_ISP_SMMU_FD			10
+#define CLK_ISP_SMMU_LITE0		11
+#define CLK_ISP_SMMU_LITE1		12
+#define CLK_ISP_PPMUISPMX		13
+#define CLK_ISP_PPMUISPX		14
+#define CLK_ISP_MCUCTL_ISP		15
+#define CLK_ISP_MPWM_ISP		16
+#define CLK_ISP_I2C0_ISP		17
+#define CLK_ISP_I2C1_ISP		18
+#define CLK_ISP_MTCADC_ISP		19
+#define CLK_ISP_PWM_ISP			20
+#define CLK_ISP_WDT_ISP			21
+#define CLK_ISP_UART_ISP		22
+#define CLK_ISP_ASYNCAXIM		23
+#define CLK_ISP_SMMU_ISPCX		24
+#define CLK_ISP_SPI0_ISP		25
+#define CLK_ISP_SPI1_ISP		26
+
+#define CLK_ISP_DIV_ISP0		27
+#define CLK_ISP_DIV_ISP1		28
+#define CLK_ISP_DIV_MCUISP0		29
+#define CLK_ISP_DIV_MCUISP1		30
+
+#define CLK_NR_ISP_CLKS			31
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */

include/dt-bindings/clock/exynos5250.h

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5250 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_MPLL		3
+#define CLK_FOUT_BPLL		4
+#define CLK_FOUT_GPLL		5
+#define CLK_FOUT_CPLL		6
+#define CLK_FOUT_EPLL		7
+#define CLK_FOUT_VPLL		8
+#define CLK_ARM_CLK		9
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_CAM_BAYER	128
+#define CLK_SCLK_CAM0		129
+#define CLK_SCLK_CAM1		130
+#define CLK_SCLK_GSCL_WA	131
+#define CLK_SCLK_GSCL_WB	132
+#define CLK_SCLK_FIMD1		133
+#define CLK_SCLK_MIPI1		134
+#define CLK_SCLK_DP		135
+#define CLK_SCLK_HDMI		136
+#define CLK_SCLK_PIXEL		137
+#define CLK_SCLK_AUDIO0		138
+#define CLK_SCLK_MMC0		139
+#define CLK_SCLK_MMC1		140
+#define CLK_SCLK_MMC2		141
+#define CLK_SCLK_MMC3		142
+#define CLK_SCLK_SATA		143
+#define CLK_SCLK_USB3		144
+#define CLK_SCLK_JPEG		145
+#define CLK_SCLK_UART0		146
+#define CLK_SCLK_UART1		147
+#define CLK_SCLK_UART2		148
+#define CLK_SCLK_UART3		149
+#define CLK_SCLK_PWM		150
+#define CLK_SCLK_AUDIO1		151
+#define CLK_SCLK_AUDIO2		152
+#define CLK_SCLK_SPDIF		153
+#define CLK_SCLK_SPI0		154
+#define CLK_SCLK_SPI1		155
+#define CLK_SCLK_SPI2		156
+#define CLK_DIV_I2S1		157
+#define CLK_DIV_I2S2		158
+#define CLK_SCLK_HDMIPHY	159
+#define CLK_DIV_PCM0		160
+
+/* gate clocks */
+#define CLK_GSCL0		256
+#define CLK_GSCL1		257
+#define CLK_GSCL2		258
+#define CLK_GSCL3		259
+#define CLK_GSCL_WA		260
+#define CLK_GSCL_WB		261
+#define CLK_SMMU_GSCL0		262
+#define CLK_SMMU_GSCL1		263
+#define CLK_SMMU_GSCL2		264
+#define CLK_SMMU_GSCL3		265
+#define CLK_MFC			266
+#define CLK_SMMU_MFCL		267
+#define CLK_SMMU_MFCR		268
+#define CLK_ROTATOR		269
+#define CLK_JPEG		270
+#define CLK_MDMA1		271
+#define CLK_SMMU_ROTATOR	272
+#define CLK_SMMU_JPEG		273
+#define CLK_SMMU_MDMA1		274
+#define CLK_PDMA0		275
+#define CLK_PDMA1		276
+#define CLK_SATA		277
+#define CLK_USBOTG		278
+#define CLK_MIPI_HSI		279
+#define CLK_SDMMC0		280
+#define CLK_SDMMC1		281
+#define CLK_SDMMC2		282
+#define CLK_SDMMC3		283
+#define CLK_SROMC		284
+#define CLK_USB2		285
+#define CLK_USB3		286
+#define CLK_SATA_PHYCTRL	287
+#define CLK_SATA_PHYI2C		288
+#define CLK_UART0		289
+#define CLK_UART1		290
+#define CLK_UART2		291
+#define CLK_UART3		292
+#define CLK_UART4		293
+#define CLK_I2C0		294
+#define CLK_I2C1		295
+#define CLK_I2C2		296
+#define CLK_I2C3		297
+#define CLK_I2C4		298
+#define CLK_I2C5		299
+#define CLK_I2C6		300
+#define CLK_I2C7		301
+#define CLK_I2C_HDMI		302
+#define CLK_ADC			303
+#define CLK_SPI0		304
+#define CLK_SPI1		305
+#define CLK_SPI2		306
+#define CLK_I2S1		307
+#define CLK_I2S2		308
+#define CLK_PCM1		309
+#define CLK_PCM2		310
+#define CLK_PWM			311
+#define CLK_SPDIF		312
+#define CLK_AC97		313
+#define CLK_HSI2C0		314
+#define CLK_HSI2C1		315
+#define CLK_HSI2C2		316
+#define CLK_HSI2C3		317
+#define CLK_CHIPID		318
+#define CLK_SYSREG		319
+#define CLK_PMU			320
+#define CLK_CMU_TOP		321
+#define CLK_CMU_CORE		322
+#define CLK_CMU_MEM		323
+#define CLK_TZPC0		324
+#define CLK_TZPC1		325
+#define CLK_TZPC2		326
+#define CLK_TZPC3		327
+#define CLK_TZPC4		328
+#define CLK_TZPC5		329
+#define CLK_TZPC6		330
+#define CLK_TZPC7		331
+#define CLK_TZPC8		332
+#define CLK_TZPC9		333
+#define CLK_HDMI_CEC		334
+#define CLK_MCT			335
+#define CLK_WDT			336
+#define CLK_RTC			337
+#define CLK_TMU			338
+#define CLK_FIMD1		339
+#define CLK_MIE1		340
+#define CLK_DSIM0		341
+#define CLK_DP			342
+#define CLK_MIXER		343
+#define CLK_HDMI		344
+#define CLK_G2D			345
+#define CLK_MDMA0		346
+#define CLK_SMMU_MDMA0		347
+#define CLK_SSS			348
+#define CLK_G3D			349
+#define CLK_SMMU_TV		350
+#define CLK_SMMU_FIMD1		351
+#define CLK_SMMU_2D		352
+#define CLK_SMMU_FIMC_ISP	353
+#define CLK_SMMU_FIMC_DRC	354
+#define CLK_SMMU_FIMC_SCC	355
+#define CLK_SMMU_FIMC_SCP	356
+#define CLK_SMMU_FIMC_FD	357
+#define CLK_SMMU_FIMC_MCU	358
+#define CLK_SMMU_FIMC_ODC	359
+#define CLK_SMMU_FIMC_DIS0	360
+#define CLK_SMMU_FIMC_DIS1	361
+#define CLK_SMMU_FIMC_3DNR	362
+#define CLK_SMMU_FIMC_LITE0	363
+#define CLK_SMMU_FIMC_LITE1	364
+#define CLK_CAMIF_TOP		365
+
+/* mux clocks */
+#define CLK_MOUT_HDMI		1024
+#define CLK_MOUT_GPLL		1025
+#define CLK_MOUT_ACLK200_DISP1_SUB	1026
+#define CLK_MOUT_ACLK300_DISP1_SUB	1027
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS		1028
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

include/dt-bindings/clock/exynos5260-clk.h

@@ -0,0 +1,469 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Rahul Sharma <rahul.sharma@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/* Clock names: <cmu><type><IP> */
+
+/* List Of Clocks For CMU_TOP */
+
+#define TOP_FOUT_DISP_PLL				1
+#define TOP_FOUT_AUD_PLL				2
+#define TOP_MOUT_AUDTOP_PLL_USER			3
+#define TOP_MOUT_AUD_PLL				4
+#define TOP_MOUT_DISP_PLL				5
+#define TOP_MOUT_BUSTOP_PLL_USER			6
+#define TOP_MOUT_MEMTOP_PLL_USER			7
+#define TOP_MOUT_MEDIATOP_PLL_USER			8
+#define TOP_MOUT_DISP_DISP_333				9
+#define TOP_MOUT_ACLK_DISP_333				10
+#define TOP_MOUT_DISP_DISP_222				11
+#define TOP_MOUT_ACLK_DISP_222				12
+#define TOP_MOUT_DISP_MEDIA_PIXEL			13
+#define TOP_MOUT_FIMD1					14
+#define TOP_MOUT_SCLK_PERI_SPI0_CLK			15
+#define TOP_MOUT_SCLK_PERI_SPI1_CLK			16
+#define TOP_MOUT_SCLK_PERI_SPI2_CLK			17
+#define TOP_MOUT_SCLK_PERI_UART0_UCLK			18
+#define TOP_MOUT_SCLK_PERI_UART2_UCLK			19
+#define TOP_MOUT_SCLK_PERI_UART1_UCLK			20
+#define TOP_MOUT_BUS4_BUSTOP_100			21
+#define TOP_MOUT_BUS4_BUSTOP_400			22
+#define TOP_MOUT_BUS3_BUSTOP_100			23
+#define TOP_MOUT_BUS3_BUSTOP_400			24
+#define TOP_MOUT_BUS2_BUSTOP_400			25
+#define TOP_MOUT_BUS2_BUSTOP_100			26
+#define TOP_MOUT_BUS1_BUSTOP_100			27
+#define TOP_MOUT_BUS1_BUSTOP_400			28
+#define TOP_MOUT_SCLK_FSYS_USB				29
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A		30
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A		31
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A		32
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B		33
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B		34
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B		35
+#define TOP_MOUT_ACLK_ISP1_266				36
+#define TOP_MOUT_ISP1_MEDIA_266				37
+#define TOP_MOUT_ACLK_ISP1_400				38
+#define TOP_MOUT_ISP1_MEDIA_400				39
+#define TOP_MOUT_SCLK_ISP1_SPI0				40
+#define TOP_MOUT_SCLK_ISP1_SPI1				41
+#define TOP_MOUT_SCLK_ISP1_UART				42
+#define TOP_MOUT_SCLK_ISP1_SENSOR2			43
+#define TOP_MOUT_SCLK_ISP1_SENSOR1			44
+#define TOP_MOUT_SCLK_ISP1_SENSOR0			45
+#define TOP_MOUT_ACLK_MFC_333				46
+#define TOP_MOUT_MFC_BUSTOP_333				47
+#define TOP_MOUT_ACLK_G2D_333				48
+#define TOP_MOUT_G2D_BUSTOP_333				49
+#define TOP_MOUT_ACLK_GSCL_FIMC				50
+#define TOP_MOUT_GSCL_BUSTOP_FIMC			51
+#define TOP_MOUT_ACLK_GSCL_333				52
+#define TOP_MOUT_GSCL_BUSTOP_333			53
+#define TOP_MOUT_ACLK_GSCL_400				54
+#define TOP_MOUT_M2M_MEDIATOP_400			55
+#define TOP_DOUT_ACLK_MFC_333				56
+#define TOP_DOUT_ACLK_G2D_333				57
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_A			58
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_A			59
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_A			60
+#define TOP_DOUT_ACLK_GSCL_FIMC				61
+#define TOP_DOUT_ACLK_GSCL_400				62
+#define TOP_DOUT_ACLK_GSCL_333				63
+#define TOP_DOUT_SCLK_ISP1_SPI0_B			64
+#define TOP_DOUT_SCLK_ISP1_SPI0_A			65
+#define TOP_DOUT_ACLK_ISP1_400				66
+#define TOP_DOUT_ACLK_ISP1_266				67
+#define TOP_DOUT_SCLK_ISP1_UART				68
+#define TOP_DOUT_SCLK_ISP1_SPI1_B			69
+#define TOP_DOUT_SCLK_ISP1_SPI1_A			70
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_B			71
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_B			72
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_B			73
+#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK			74
+#define TOP_DOUT_SCLK_DISP_PIXEL			75
+#define TOP_DOUT_ACLK_DISP_222				76
+#define TOP_DOUT_ACLK_DISP_333				77
+#define TOP_DOUT_ACLK_BUS4_100				78
+#define TOP_DOUT_ACLK_BUS4_400				79
+#define TOP_DOUT_ACLK_BUS3_100				80
+#define TOP_DOUT_ACLK_BUS3_400				81
+#define TOP_DOUT_ACLK_BUS2_100				82
+#define TOP_DOUT_ACLK_BUS2_400				83
+#define TOP_DOUT_ACLK_BUS1_100				84
+#define TOP_DOUT_ACLK_BUS1_400				85
+#define TOP_DOUT_SCLK_PERI_SPI1_B			86
+#define TOP_DOUT_SCLK_PERI_SPI1_A			87
+#define TOP_DOUT_SCLK_PERI_SPI0_B			88
+#define TOP_DOUT_SCLK_PERI_SPI0_A			89
+#define TOP_DOUT_SCLK_PERI_UART0			90
+#define TOP_DOUT_SCLK_PERI_UART2			91
+#define TOP_DOUT_SCLK_PERI_UART1			92
+#define TOP_DOUT_SCLK_PERI_SPI2_B			93
+#define TOP_DOUT_SCLK_PERI_SPI2_A			94
+#define TOP_DOUT_ACLK_PERI_AUD				95
+#define TOP_DOUT_ACLK_PERI_66				96
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B		97
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A		98
+#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK		99
+#define TOP_DOUT_ACLK_FSYS_200				100
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B		101
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A		102
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B		103
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A		104
+#define TOP_SCLK_FIMD1					105
+#define TOP_SCLK_MMC2					106
+#define TOP_SCLK_MMC1					107
+#define TOP_SCLK_MMC0					108
+#define PHYCLK_DPTX_PHY_CH3_TXD_CLK			109
+#define PHYCLK_DPTX_PHY_CH2_TXD_CLK			110
+#define PHYCLK_DPTX_PHY_CH1_TXD_CLK			111
+#define PHYCLK_DPTX_PHY_CH0_TXD_CLK			112
+#define phyclk_hdmi_phy_tmds_clko			113
+#define PHYCLK_HDMI_PHY_PIXEL_CLKO			114
+#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI			115
+#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS		116
+#define PHYCLK_DPTX_PHY_O_REF_CLK_24M			117
+#define PHYCLK_DPTX_PHY_CLK_DIV2			118
+#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0			119
+#define PHYCLK_USBHOST20_PHY_PHYCLOCK			120
+#define PHYCLK_USBHOST20_PHY_FREECLK			121
+#define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
+#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
+#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
+#define TOP_NR_CLK					125
+
+
+/* List Of Clocks For CMU_EGL */
+
+#define EGL_FOUT_EGL_PLL				1
+#define EGL_FOUT_EGL_DPLL				2
+#define EGL_MOUT_EGL_B					3
+#define EGL_MOUT_EGL_PLL				4
+#define EGL_DOUT_EGL_PLL				5
+#define EGL_DOUT_EGL_PCLK_DBG				6
+#define EGL_DOUT_EGL_ATCLK				7
+#define EGL_DOUT_PCLK_EGL				8
+#define EGL_DOUT_ACLK_EGL				9
+#define EGL_DOUT_EGL2					10
+#define EGL_DOUT_EGL1					11
+#define EGL_NR_CLK					12
+
+
+/* List Of Clocks For CMU_KFC */
+
+#define KFC_FOUT_KFC_PLL				1
+#define KFC_MOUT_KFC_PLL				2
+#define KFC_MOUT_KFC					3
+#define KFC_DOUT_KFC_PLL				4
+#define KFC_DOUT_PCLK_KFC				5
+#define KFC_DOUT_ACLK_KFC				6
+#define KFC_DOUT_KFC_PCLK_DBG				7
+#define KFC_DOUT_KFC_ATCLK				8
+#define KFC_DOUT_KFC2					9
+#define KFC_DOUT_KFC1					10
+#define KFC_NR_CLK					11
+
+
+/* List Of Clocks For CMU_MIF */
+
+#define MIF_FOUT_MEM_PLL				1
+#define MIF_FOUT_MEDIA_PLL				2
+#define MIF_FOUT_BUS_PLL				3
+#define MIF_MOUT_CLK2X_PHY				4
+#define MIF_MOUT_MIF_DREX2X				5
+#define MIF_MOUT_CLKM_PHY				6
+#define MIF_MOUT_MIF_DREX				7
+#define MIF_MOUT_MEDIA_PLL				8
+#define MIF_MOUT_BUS_PLL				9
+#define MIF_MOUT_MEM_PLL				10
+#define MIF_DOUT_ACLK_BUS_100				11
+#define MIF_DOUT_ACLK_BUS_200				12
+#define MIF_DOUT_ACLK_MIF_466				13
+#define MIF_DOUT_CLK2X_PHY				14
+#define MIF_DOUT_CLKM_PHY				15
+#define MIF_DOUT_BUS_PLL				16
+#define MIF_DOUT_MEM_PLL				17
+#define MIF_DOUT_MEDIA_PLL				18
+#define MIF_CLK_LPDDR3PHY_WRAP1				19
+#define MIF_CLK_LPDDR3PHY_WRAP0				20
+#define MIF_CLK_MONOCNT					21
+#define MIF_CLK_MIF_RTC					22
+#define MIF_CLK_DREX1					23
+#define MIF_CLK_DREX0					24
+#define MIF_CLK_INTMEM					25
+#define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
+#define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
+#define MIF_NR_CLK					28
+
+
+/* List Of Clocks For CMU_G3D */
+
+#define G3D_FOUT_G3D_PLL				1
+#define G3D_MOUT_G3D_PLL				2
+#define G3D_DOUT_PCLK_G3D				3
+#define G3D_DOUT_ACLK_G3D				4
+#define G3D_CLK_G3D_HPM					5
+#define G3D_CLK_G3D					6
+#define G3D_NR_CLK					7
+
+
+/* List Of Clocks For CMU_AUD */
+
+#define AUD_MOUT_SCLK_AUD_PCM				1
+#define AUD_MOUT_SCLK_AUD_I2S				2
+#define AUD_MOUT_AUD_PLL_USER				3
+#define AUD_DOUT_ACLK_AUD_131				4
+#define AUD_DOUT_SCLK_AUD_UART				5
+#define AUD_DOUT_SCLK_AUD_PCM				6
+#define AUD_DOUT_SCLK_AUD_I2S				7
+#define AUD_CLK_AUD_UART				8
+#define AUD_CLK_PCM					9
+#define AUD_CLK_I2S					10
+#define AUD_CLK_DMAC					11
+#define AUD_CLK_SRAMC					12
+#define AUD_SCLK_AUD_UART				13
+#define AUD_SCLK_PCM					14
+#define AUD_SCLK_I2S					15
+#define AUD_NR_CLK					16
+
+
+/* List Of Clocks For CMU_MFC */
+
+#define MFC_MOUT_ACLK_MFC_333_USER			1
+#define MFC_DOUT_PCLK_MFC_83				2
+#define MFC_CLK_MFC					3
+#define MFC_CLK_SMMU2_MFCM1				4
+#define MFC_CLK_SMMU2_MFCM0				5
+#define MFC_NR_CLK					6
+
+
+/* List Of Clocks For CMU_GSCL */
+
+#define GSCL_MOUT_ACLK_CSIS				1
+#define GSCL_MOUT_ACLK_GSCL_FIMC_USER			2
+#define GSCL_MOUT_ACLK_M2M_400_USER			3
+#define GSCL_MOUT_ACLK_GSCL_333_USER			4
+#define GSCL_DOUT_ACLK_CSIS_200				5
+#define GSCL_DOUT_PCLK_M2M_100				6
+#define GSCL_CLK_PIXEL_GSCL1				7
+#define GSCL_CLK_PIXEL_GSCL0				8
+#define GSCL_CLK_MSCL1					9
+#define GSCL_CLK_MSCL0					10
+#define GSCL_CLK_GSCL1					11
+#define GSCL_CLK_GSCL0					12
+#define GSCL_CLK_FIMC_LITE_D				13
+#define GSCL_CLK_FIMC_LITE_B				14
+#define GSCL_CLK_FIMC_LITE_A				15
+#define GSCL_CLK_CSIS1					16
+#define GSCL_CLK_CSIS0					17
+#define GSCL_CLK_SMMU3_LITE_D				18
+#define GSCL_CLK_SMMU3_LITE_B				19
+#define GSCL_CLK_SMMU3_LITE_A				20
+#define GSCL_CLK_SMMU3_GSCL0				21
+#define GSCL_CLK_SMMU3_GSCL1				22
+#define GSCL_CLK_SMMU3_MSCL0				23
+#define GSCL_CLK_SMMU3_MSCL1				24
+#define GSCL_SCLK_CSIS1_WRAP				25
+#define GSCL_SCLK_CSIS0_WRAP				26
+#define GSCL_NR_CLK					27
+
+
+/* List Of Clocks For CMU_FSYS */
+
+#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER		1
+#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER		2
+#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER	3
+#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER	4
+#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER		5
+#define FSYS_CLK_TSI					6
+#define FSYS_CLK_USBLINK				7
+#define FSYS_CLK_USBHOST20				8
+#define FSYS_CLK_USBDRD30				9
+#define FSYS_CLK_SROMC					10
+#define FSYS_CLK_PDMA					11
+#define FSYS_CLK_MMC2					12
+#define FSYS_CLK_MMC1					13
+#define FSYS_CLK_MMC0					14
+#define FSYS_CLK_RTIC					15
+#define FSYS_CLK_SMMU_RTIC				16
+#define FSYS_PHYCLK_USBDRD30				17
+#define FSYS_PHYCLK_USBHOST20				18
+#define FSYS_NR_CLK					19
+
+
+/* List Of Clocks For CMU_PERI */
+
+#define PERI_MOUT_SCLK_SPDIF				1
+#define PERI_MOUT_SCLK_I2SCOD				2
+#define PERI_MOUT_SCLK_PCM				3
+#define PERI_DOUT_I2S					4
+#define PERI_DOUT_PCM					5
+#define PERI_CLK_WDT_KFC				6
+#define PERI_CLK_WDT_EGL				7
+#define PERI_CLK_HSIC3					8
+#define PERI_CLK_HSIC2					9
+#define PERI_CLK_HSIC1					10
+#define PERI_CLK_HSIC0					11
+#define PERI_CLK_PCM					12
+#define PERI_CLK_MCT					13
+#define PERI_CLK_I2S					14
+#define PERI_CLK_I2CHDMI				15
+#define PERI_CLK_I2C7					16
+#define PERI_CLK_I2C6					17
+#define PERI_CLK_I2C5					18
+#define PERI_CLK_I2C4					19
+#define PERI_CLK_I2C9					20
+#define PERI_CLK_I2C8					21
+#define PERI_CLK_I2C11					22
+#define PERI_CLK_I2C10					23
+#define PERI_CLK_HDMICEC				24
+#define PERI_CLK_EFUSE_WRITER				25
+#define PERI_CLK_ABB					26
+#define PERI_CLK_UART2					27
+#define PERI_CLK_UART1					28
+#define PERI_CLK_UART0					29
+#define PERI_CLK_ADC					30
+#define PERI_CLK_TMU4					31
+#define PERI_CLK_TMU3					32
+#define PERI_CLK_TMU2					33
+#define PERI_CLK_TMU1					34
+#define PERI_CLK_TMU0					35
+#define PERI_CLK_SPI2					36
+#define PERI_CLK_SPI1					37
+#define PERI_CLK_SPI0					38
+#define PERI_CLK_SPDIF					39
+#define PERI_CLK_PWM					40
+#define PERI_CLK_UART4					41
+#define PERI_CLK_CHIPID					42
+#define PERI_CLK_PROVKEY0				43
+#define PERI_CLK_PROVKEY1				44
+#define PERI_CLK_SECKEY					45
+#define PERI_CLK_TOP_RTC				46
+#define PERI_CLK_TZPC10					47
+#define PERI_CLK_TZPC9					48
+#define PERI_CLK_TZPC8					49
+#define PERI_CLK_TZPC7					50
+#define PERI_CLK_TZPC6					51
+#define PERI_CLK_TZPC5					52
+#define PERI_CLK_TZPC4					53
+#define PERI_CLK_TZPC3					54
+#define PERI_CLK_TZPC2					55
+#define PERI_CLK_TZPC1					56
+#define PERI_CLK_TZPC0					57
+#define PERI_SCLK_UART2					58
+#define PERI_SCLK_UART1					59
+#define PERI_SCLK_UART0					60
+#define PERI_SCLK_SPI2					61
+#define PERI_SCLK_SPI1					62
+#define PERI_SCLK_SPI0					63
+#define PERI_SCLK_SPDIF					64
+#define PERI_SCLK_I2S					65
+#define PERI_SCLK_PCM1					66
+#define PERI_NR_CLK					67
+
+
+/* List Of Clocks For CMU_DISP */
+
+#define DISP_MOUT_SCLK_HDMI_SPDIF			1
+#define DISP_MOUT_SCLK_HDMI_PIXEL			2
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER	3
+#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER	4
+#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER		5
+#define DISP_MOUT_HDMI_PHY_PIXEL			6
+#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER	7
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS	8
+#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER	9
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER		10
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER	11
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER	12
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER	13
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER	14
+#define DISP_MOUT_ACLK_DISP_222_USER			15
+#define DISP_MOUT_SCLK_DISP_PIXEL_USER			16
+#define DISP_MOUT_ACLK_DISP_333_USER			17
+#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI		18
+#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL			19
+#define DISP_DOUT_PCLK_DISP_111				20
+#define DISP_CLK_SMMU_TV				21
+#define DISP_CLK_SMMU_FIMD1M1				22
+#define DISP_CLK_SMMU_FIMD1M0				23
+#define DISP_CLK_PIXEL_MIXER				24
+#define DISP_CLK_PIXEL_DISP				25
+#define DISP_CLK_MIXER					26
+#define DISP_CLK_MIPIPHY				27
+#define DISP_CLK_HDMIPHY				28
+#define DISP_CLK_HDMI					29
+#define DISP_CLK_FIMD1					30
+#define DISP_CLK_DSIM1					31
+#define DISP_CLK_DPPHY					32
+#define DISP_CLK_DP					33
+#define DISP_SCLK_PIXEL					34
+#define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
+#define DISP_NR_CLK					36
+
+
+/* List Of Clocks For CMU_G2D */
+
+#define G2D_MOUT_ACLK_G2D_333_USER			1
+#define G2D_DOUT_PCLK_G2D_83				2
+#define G2D_CLK_SMMU3_JPEG				3
+#define G2D_CLK_MDMA					4
+#define G2D_CLK_JPEG					5
+#define G2D_CLK_G2D					6
+#define G2D_CLK_SSS					7
+#define G2D_CLK_SLIM_SSS				8
+#define G2D_CLK_SMMU_SLIM_SSS				9
+#define G2D_CLK_SMMU_SSS				10
+#define G2D_CLK_SMMU_MDMA				11
+#define G2D_CLK_SMMU3_G2D				12
+#define G2D_NR_CLK					13
+
+
+/* List Of Clocks For CMU_ISP */
+
+#define ISP_MOUT_ISP_400_USER				1
+#define ISP_MOUT_ISP_266_USER				2
+#define ISP_DOUT_SCLK_MPWM				3
+#define ISP_DOUT_CA5_PCLKDBG				4
+#define ISP_DOUT_CA5_ATCLKIN				5
+#define ISP_DOUT_PCLK_ISP_133				6
+#define ISP_DOUT_PCLK_ISP_66				7
+#define ISP_CLK_GIC					8
+#define ISP_CLK_WDT					9
+#define ISP_CLK_UART					10
+#define ISP_CLK_SPI1					11
+#define ISP_CLK_SPI0					12
+#define ISP_CLK_SMMU_SCALERP				13
+#define ISP_CLK_SMMU_SCALERC				14
+#define ISP_CLK_SMMU_ISPCX				15
+#define ISP_CLK_SMMU_ISP				16
+#define ISP_CLK_SMMU_FD					17
+#define ISP_CLK_SMMU_DRC				18
+#define ISP_CLK_PWM					19
+#define ISP_CLK_MTCADC					20
+#define ISP_CLK_MPWM					21
+#define ISP_CLK_MCUCTL					22
+#define ISP_CLK_I2C1					23
+#define ISP_CLK_I2C0					24
+#define ISP_CLK_FIMC_SCALERP				25
+#define ISP_CLK_FIMC_SCALERC				26
+#define ISP_CLK_FIMC					27
+#define ISP_CLK_FIMC_FD					28
+#define ISP_CLK_FIMC_DRC				29
+#define ISP_CLK_CA5					30
+#define ISP_SCLK_SPI0_EXT				31
+#define ISP_SCLK_SPI1_EXT				32
+#define ISP_SCLK_UART_EXT				33
+#define ISP_NR_CLK					34
+
+#endif

include/dt-bindings/clock/exynos5410.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5421 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_MPLL		4
+#define CLK_FOUT_BPLL		5
+#define CLK_FOUT_KPLL		6
+#define CLK_FOUT_EPLL		7
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_PWM		155
+
+/* gate clocks */
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_I2C0		261
+#define CLK_I2C1		262
+#define CLK_I2C2		263
+#define CLK_I2C3		264
+#define CLK_USI0		265
+#define CLK_USI1		266
+#define CLK_USI2		267
+#define CLK_USI3		268
+#define CLK_UART3		260
+#define CLK_PWM			279
+#define CLK_MCT			315
+#define CLK_WDT			316
+#define CLK_RTC			317
+#define CLK_TMU			318
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
+#define CLK_PDMA0		362
+#define CLK_PDMA1		363
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
+#define CLK_SSS			471
+
+#define CLK_NR_CLKS		512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */

include/dt-bindings/clock/exynos5420.h

@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5420 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_DPLL		4
+#define CLK_FOUT_EPLL		5
+#define CLK_FOUT_RPLL		6
+#define CLK_FOUT_IPLL		7
+#define CLK_FOUT_SPLL		8
+#define CLK_FOUT_VPLL		9
+#define CLK_FOUT_MPLL		10
+#define CLK_FOUT_BPLL		11
+#define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
+#define CLK_SCLK_SPI0		135
+#define CLK_SCLK_SPI1		136
+#define CLK_SCLK_SPI2		137
+#define CLK_SCLK_I2S1		138
+#define CLK_SCLK_I2S2		139
+#define CLK_SCLK_PCM1		140
+#define CLK_SCLK_PCM2		141
+#define CLK_SCLK_SPDIF		142
+#define CLK_SCLK_HDMI		143
+#define CLK_SCLK_PIXEL		144
+#define CLK_SCLK_DP1		145
+#define CLK_SCLK_MIPI1		146
+#define CLK_SCLK_FIMD1		147
+#define CLK_SCLK_MAUDIO0	148
+#define CLK_SCLK_MAUPCM0	149
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_UNIPRO		154
+#define CLK_SCLK_PWM		155
+#define CLK_SCLK_GSCL_WA	156
+#define CLK_SCLK_GSCL_WB	157
+#define CLK_SCLK_HDMIPHY	158
+#define CLK_MAU_EPLL		159
+#define CLK_SCLK_HSIC_12M	160
+#define CLK_SCLK_MPHY_IXTAL24	161
+
+/* gate clocks */
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_UART3		260
+#define CLK_I2C0		261
+#define CLK_I2C1		262
+#define CLK_I2C2		263
+#define CLK_I2C3		264
+#define CLK_USI0		265
+#define CLK_USI1		266
+#define CLK_USI2		267
+#define CLK_USI3		268
+#define CLK_I2C_HDMI		269
+#define CLK_TSADC		270
+#define CLK_SPI0		271
+#define CLK_SPI1		272
+#define CLK_SPI2		273
+#define CLK_KEYIF		274
+#define CLK_I2S1		275
+#define CLK_I2S2		276
+#define CLK_PCM1		277
+#define CLK_PCM2		278
+#define CLK_PWM			279
+#define CLK_SPDIF		280
+#define CLK_USI4		281
+#define CLK_USI5		282
+#define CLK_USI6		283
+#define CLK_ACLK66_PSGEN	300
+#define CLK_CHIPID		301
+#define CLK_SYSREG		302
+#define CLK_TZPC0		303
+#define CLK_TZPC1		304
+#define CLK_TZPC2		305
+#define CLK_TZPC3		306
+#define CLK_TZPC4		307
+#define CLK_TZPC5		308
+#define CLK_TZPC6		309
+#define CLK_TZPC7		310
+#define CLK_TZPC8		311
+#define CLK_TZPC9		312
+#define CLK_HDMI_CEC		313
+#define CLK_SECKEY		314
+#define CLK_MCT			315
+#define CLK_WDT			316
+#define CLK_RTC			317
+#define CLK_TMU			318
+#define CLK_TMU_GPU		319
+#define CLK_PCLK66_GPIO		330
+#define CLK_ACLK200_FSYS2	350
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
+#define CLK_SROMC		354
+#define CLK_UFS			355
+#define CLK_ACLK200_FSYS	360
+#define CLK_TSI			361
+#define CLK_PDMA0		362
+#define CLK_PDMA1		363
+#define CLK_RTIC		364
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
+#define CLK_ACLK400_MSCL	380
+#define CLK_MSCL0		381
+#define CLK_MSCL1		382
+#define CLK_MSCL2		383
+#define CLK_SMMU_MSCL0		384
+#define CLK_SMMU_MSCL1		385
+#define CLK_SMMU_MSCL2		386
+#define CLK_ACLK333		400
+#define CLK_MFC			401
+#define CLK_SMMU_MFCL		402
+#define CLK_SMMU_MFCR		403
+#define CLK_ACLK200_DISP1	410
+#define CLK_DSIM1		411
+#define CLK_DP1			412
+#define CLK_HDMI		413
+#define CLK_ACLK300_DISP1	420
+#define CLK_FIMD1		421
+#define CLK_SMMU_FIMD1M0	422
+#define CLK_SMMU_FIMD1M1	423
+#define CLK_ACLK166		430
+#define CLK_MIXER		431
+#define CLK_ACLK266		440
+#define CLK_ROTATOR		441
+#define CLK_MDMA1		442
+#define CLK_SMMU_ROTATOR	443
+#define CLK_SMMU_MDMA1		444
+#define CLK_ACLK300_JPEG	450
+#define CLK_JPEG		451
+#define CLK_JPEG2		452
+#define CLK_SMMU_JPEG		453
+#define CLK_SMMU_JPEG2		454
+#define CLK_ACLK300_GSCL	460
+#define CLK_SMMU_GSCL0		461
+#define CLK_SMMU_GSCL1		462
+#define CLK_GSCL_WA		463
+#define CLK_GSCL_WB		464
+#define CLK_GSCL0		465
+#define CLK_GSCL1		466
+#define CLK_FIMC_3AA		467
+#define CLK_ACLK266_G2D		470
+#define CLK_SSS			471
+#define CLK_SLIM_SSS		472
+#define CLK_MDMA0		473
+#define CLK_ACLK333_G2D		480
+#define CLK_G2D			481
+#define CLK_ACLK333_432_GSCL	490
+#define CLK_SMMU_3AA		491
+#define CLK_SMMU_FIMCL0		492
+#define CLK_SMMU_FIMCL1		493
+#define CLK_SMMU_FIMCL3		494
+#define CLK_FIMC_LITE3		495
+#define CLK_FIMC_LITE0		496
+#define CLK_FIMC_LITE1		497
+#define CLK_ACLK_G3D		500
+#define CLK_G3D			501
+#define CLK_SMMU_MIXER		502
+#define CLK_SMMU_G2D		503
+#define CLK_SMMU_MDMA0		504
+#define CLK_MC			505
+#define CLK_TOP_RTC		506
+#define CLK_SCLK_UART_ISP	510
+#define CLK_SCLK_SPI0_ISP	511
+#define CLK_SCLK_SPI1_ISP	512
+#define CLK_SCLK_PWM_ISP	513
+#define CLK_SCLK_ISP_SENSOR0	514
+#define CLK_SCLK_ISP_SENSOR1	515
+#define CLK_SCLK_ISP_SENSOR2	516
+#define CLK_ACLK432_SCALER	517
+#define CLK_ACLK432_CAM		518
+#define CLK_ACLK_FL1550_CAM	519
+#define CLK_ACLK550_CAM		520
+
+/* mux clocks */
+#define CLK_MOUT_HDMI		640
+#define CLK_MOUT_G3D		641
+#define CLK_MOUT_VPLL		642
+#define CLK_MOUT_MAUDIO0	643
+#define CLK_MOUT_USER_ACLK333	644
+#define CLK_MOUT_SW_ACLK333	645
+#define CLK_MOUT_USER_ACLK200_DISP1	646
+#define CLK_MOUT_SW_ACLK200	647
+#define CLK_MOUT_USER_ACLK300_DISP1     648
+#define CLK_MOUT_SW_ACLK300     649
+#define CLK_MOUT_USER_ACLK400_DISP1     650
+#define CLK_MOUT_SW_ACLK400     651
+#define CLK_MOUT_USER_ACLK300_GSCL	652
+#define CLK_MOUT_SW_ACLK300_GSCL	653
+#define CLK_MOUT_MCLK_CDREX	654
+#define CLK_MOUT_BPLL		655
+#define CLK_MOUT_MX_MSPLL_CCORE	656
+#define CLK_MOUT_EPLL		657
+#define CLK_MOUT_MAU_EPLL	658
+#define CLK_MOUT_USER_MAU_EPLL	659
+
+/* divider clocks */
+#define CLK_DOUT_PIXEL		768
+#define CLK_DOUT_ACLK400_WCORE	769
+#define CLK_DOUT_ACLK400_ISP	770
+#define CLK_DOUT_ACLK400_MSCL	771
+#define CLK_DOUT_ACLK200	772
+#define CLK_DOUT_ACLK200_FSYS2	773
+#define CLK_DOUT_ACLK100_NOC	774
+#define CLK_DOUT_PCLK200_FSYS	775
+#define CLK_DOUT_ACLK200_FSYS	776
+#define CLK_DOUT_ACLK333_432_GSCL	777
+#define CLK_DOUT_ACLK333_432_ISP	778
+#define CLK_DOUT_ACLK66		779
+#define CLK_DOUT_ACLK333_432_ISP0	780
+#define CLK_DOUT_ACLK266	781
+#define CLK_DOUT_ACLK166	782
+#define CLK_DOUT_ACLK333	783
+#define CLK_DOUT_ACLK333_G2D	784
+#define CLK_DOUT_ACLK266_G2D	785
+#define CLK_DOUT_ACLK_G3D	786
+#define CLK_DOUT_ACLK300_JPEG	787
+#define CLK_DOUT_ACLK300_DISP1	788
+#define CLK_DOUT_ACLK300_GSCL	789
+#define CLK_DOUT_ACLK400_DISP1	790
+#define CLK_DOUT_PCLK_CDREX	791
+#define CLK_DOUT_SCLK_CDREX	792
+#define CLK_DOUT_ACLK_CDREX1	793
+#define CLK_DOUT_CCLK_DREX0	794
+#define CLK_DOUT_CLK2X_PHY0	795
+#define CLK_DOUT_PCLK_CORE_MEM	796
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS		797
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */

include/dt-bindings/clock/exynos7-clk.h

@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define DOUT_SCLK_AUD_PLL		9
+#define FOUT_AUD_PLL			10
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define ACLK_CCORE_133			20
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define CLK_SCLK_SPI0			7
+#define CLK_SCLK_SPI1			8
+#define CLK_SCLK_SPI2			9
+#define CLK_SCLK_SPI3			10
+#define CLK_SCLK_SPI4			11
+#define CLK_SCLK_SPDIF			12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_ACLK_PERIC0_66		15
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define CLK_ACLK_FSYS0_200		9
+#define CLK_ACLK_FSYS1_200		10
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PCLK_SPI0			12
+#define PCLK_SPI1			13
+#define PCLK_SPI2			14
+#define PCLK_SPI3			15
+#define PCLK_SPI4			16
+#define SCLK_SPI0			17
+#define SCLK_SPI1			18
+#define SCLK_SPI2			19
+#define SCLK_SPI3			20
+#define SCLK_SPI4			21
+#define PCLK_I2S1			22
+#define PCLK_PCM1			23
+#define PCLK_SPDIF			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			26
+#define SCLK_SPDIF			27
+#define PERIC1_NR_CLK			28
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
+/* AUD */
+#define SCLK_I2S			1
+#define SCLK_PCM			2
+#define PCLK_I2S			3
+#define PCLK_PCM			4
+#define ACLK_ADMA			5
+#define AUD_NR_CLK			6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */

include/dt-bindings/clock/gxbb-aoclkc.h

@@ -0,0 +1,67 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_CEC_32K	6
+
+#endif

include/dt-bindings/clock/gxbb-clkc.h

@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * GXBB clock tree IDs
+ */
+
+#ifndef __GXBB_CLKC_H
+#define __GXBB_CLKC_H
+
+#define CLKID_SYS_PLL		0
+#define CLKID_HDMI_PLL		2
+#define CLKID_FIXED_PLL		3
+#define CLKID_FCLK_DIV2		4
+#define CLKID_FCLK_DIV3		5
+#define CLKID_FCLK_DIV4		6
+#define CLKID_FCLK_DIV5		7
+#define CLKID_FCLK_DIV7		8
+#define CLKID_GP0_PLL		9
+#define CLKID_CLK81		12
+#define CLKID_MPLL0		13
+#define CLKID_MPLL1		14
+#define CLKID_MPLL2		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_ETH		36
+#define CLKID_I2S_SPDIF		35
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT0	77
+#define CLKID_GCLK_VENCI_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCI_INT1	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
+#define CLKID_AO_I2C		93
+#define CLKID_SD_EMMC_A		94
+#define CLKID_SD_EMMC_B		95
+#define CLKID_SD_EMMC_C		96
+#define CLKID_SAR_ADC_CLK	97
+#define CLKID_SAR_ADC_SEL	98
+#define CLKID_MALI_0_SEL	100
+#define CLKID_MALI_0		102
+#define CLKID_MALI_1_SEL	103
+#define CLKID_MALI_1		105
+#define CLKID_MALI		106
+#define CLKID_CTS_AMCLK		107
+#define CLKID_CTS_MCLK_I958	110
+#define CLKID_CTS_I958		113
+#define CLKID_32K_CLK		114
+#define CLKID_SD_EMMC_A_CLK0	119
+#define CLKID_SD_EMMC_B_CLK0	122
+#define CLKID_SD_EMMC_C_CLK0	125
+#define CLKID_VPU_0_SEL		126
+#define CLKID_VPU_0		128
+#define CLKID_VPU_1_SEL		129
+#define CLKID_VPU_1		131
+#define CLKID_VPU		132
+#define CLKID_VAPB_0_SEL	133
+#define CLKID_VAPB_0		135
+#define CLKID_VAPB_1_SEL	136
+#define CLKID_VAPB_1		138
+#define CLKID_VAPB_SEL		139
+#define CLKID_VAPB		140
+#define CLKID_VDEC_1		153
+#define CLKID_VDEC_HEVC		156
+#define CLKID_GEN_CLK		159
+
+#endif /* __GXBB_CLKC_H */

include/dt-bindings/clock/hi3516cv300-clock.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3516CV300_CLOCK_H
+#define __DTS_HI3516CV300_CLOCK_H
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_APB_CLK		0
+#define HI3516CV300_UART0_CLK		1
+#define HI3516CV300_UART1_CLK		2
+#define HI3516CV300_UART2_CLK		3
+#define HI3516CV300_SPI0_CLK		4
+#define HI3516CV300_SPI1_CLK		5
+#define HI3516CV300_FMC_CLK		6
+#define HI3516CV300_MMC0_CLK		7
+#define HI3516CV300_MMC1_CLK		8
+#define HI3516CV300_MMC2_CLK		9
+#define HI3516CV300_MMC3_CLK		10
+#define HI3516CV300_ETH_CLK		11
+#define HI3516CV300_ETH_MACIF_CLK	12
+#define HI3516CV300_DMAC_CLK		13
+#define HI3516CV300_PWM_CLK		14
+#define HI3516CV300_USB2_BUS_CLK	15
+#define HI3516CV300_USB2_OHCI48M_CLK	16
+#define HI3516CV300_USB2_OHCI12M_CLK	17
+#define HI3516CV300_USB2_OTG_UTMI_CLK	18
+#define HI3516CV300_USB2_HST_PHY_CLK	19
+#define HI3516CV300_USB2_UTMI0_CLK	20
+#define HI3516CV300_USB2_PHY_CLK	21
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_WDT_CLK		1
+
+#endif	/* __DTS_HI3516CV300_CLOCK_H */

include/dt-bindings/clock/hi3519-clock.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FMC_CLK			1
+#define HI3519_SPI0_CLK			2
+#define HI3519_SPI1_CLK			3
+#define HI3519_SPI2_CLK			4
+#define HI3519_UART0_CLK		5
+#define HI3519_UART1_CLK		6
+#define HI3519_UART2_CLK		7
+#define HI3519_UART3_CLK		8
+#define HI3519_UART4_CLK		9
+#define HI3519_PWM_CLK			10
+#define HI3519_DMA_CLK			11
+#define HI3519_IR_CLK			12
+#define HI3519_ETH_PHY_CLK		13
+#define HI3519_ETH_MAC_CLK		14
+#define HI3519_ETH_MACIF_CLK		15
+#define HI3519_USB2_BUS_CLK		16
+#define HI3519_USB2_PORT_CLK		17
+#define HI3519_USB3_CLK			18
+
+#endif	/* __DTS_HI3519_CLOCK_H */

include/dt-bindings/clock/hi3620-clock.h

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *	   Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DTS_HI3620_CLOCK_H
+#define __DTS_HI3620_CLOCK_H
+
+#define HI3620_NONE_CLOCK	0
+
+/* fixed rate & fixed factor clocks */
+#define HI3620_OSC32K		1
+#define HI3620_OSC26M		2
+#define HI3620_PCLK		3
+#define HI3620_PLL_ARM0		4
+#define HI3620_PLL_ARM1		5
+#define HI3620_PLL_PERI		6
+#define HI3620_PLL_USB		7
+#define HI3620_PLL_HDMI		8
+#define HI3620_PLL_GPU		9
+#define HI3620_RCLK_TCXO	10
+#define HI3620_RCLK_CFGAXI	11
+#define HI3620_RCLK_PICO	12
+
+/* mux clocks */
+#define HI3620_TIMER0_MUX	32
+#define HI3620_TIMER1_MUX	33
+#define HI3620_TIMER2_MUX	34
+#define HI3620_TIMER3_MUX	35
+#define HI3620_TIMER4_MUX	36
+#define HI3620_TIMER5_MUX	37
+#define HI3620_TIMER6_MUX	38
+#define HI3620_TIMER7_MUX	39
+#define HI3620_TIMER8_MUX	40
+#define HI3620_TIMER9_MUX	41
+#define HI3620_UART0_MUX	42
+#define HI3620_UART1_MUX	43
+#define HI3620_UART2_MUX	44
+#define HI3620_UART3_MUX	45
+#define HI3620_UART4_MUX	46
+#define HI3620_SPI0_MUX		47
+#define HI3620_SPI1_MUX		48
+#define HI3620_SPI2_MUX		49
+#define HI3620_SAXI_MUX		50
+#define HI3620_PWM0_MUX		51
+#define HI3620_PWM1_MUX		52
+#define HI3620_SD_MUX		53
+#define HI3620_MMC1_MUX		54
+#define HI3620_MMC1_MUX2	55
+#define HI3620_G2D_MUX		56
+#define HI3620_VENC_MUX		57
+#define HI3620_VDEC_MUX		58
+#define HI3620_VPP_MUX		59
+#define HI3620_EDC0_MUX		60
+#define HI3620_LDI0_MUX		61
+#define HI3620_EDC1_MUX		62
+#define HI3620_LDI1_MUX		63
+#define HI3620_RCLK_HSIC	64
+#define HI3620_MMC2_MUX		65
+#define HI3620_MMC3_MUX		66
+
+/* divider clocks */
+#define HI3620_SHAREAXI_DIV	128
+#define HI3620_CFGAXI_DIV	129
+#define HI3620_SD_DIV		130
+#define HI3620_MMC1_DIV		131
+#define HI3620_HSIC_DIV		132
+#define HI3620_MMC2_DIV		133
+#define HI3620_MMC3_DIV		134
+
+/* gate clocks */
+#define HI3620_TIMERCLK01	160
+#define HI3620_TIMER_RCLK01	161
+#define HI3620_TIMERCLK23	162
+#define HI3620_TIMER_RCLK23	163
+#define HI3620_TIMERCLK45	164
+#define HI3620_TIMERCLK67	165
+#define HI3620_TIMERCLK89	166
+#define HI3620_RTCCLK		167
+#define HI3620_KPC_CLK		168
+#define HI3620_GPIOCLK0		169
+#define HI3620_GPIOCLK1		170
+#define HI3620_GPIOCLK2		171
+#define HI3620_GPIOCLK3		172
+#define HI3620_GPIOCLK4		173
+#define HI3620_GPIOCLK5		174
+#define HI3620_GPIOCLK6		175
+#define HI3620_GPIOCLK7		176
+#define HI3620_GPIOCLK8		177
+#define HI3620_GPIOCLK9		178
+#define HI3620_GPIOCLK10	179
+#define HI3620_GPIOCLK11	180
+#define HI3620_GPIOCLK12	181
+#define HI3620_GPIOCLK13	182
+#define HI3620_GPIOCLK14	183
+#define HI3620_GPIOCLK15	184
+#define HI3620_GPIOCLK16	185
+#define HI3620_GPIOCLK17	186
+#define HI3620_GPIOCLK18	187
+#define HI3620_GPIOCLK19	188
+#define HI3620_GPIOCLK20	189
+#define HI3620_GPIOCLK21	190
+#define HI3620_DPHY0_CLK	191
+#define HI3620_DPHY1_CLK	192
+#define HI3620_DPHY2_CLK	193
+#define HI3620_USBPHY_CLK	194
+#define HI3620_ACP_CLK		195
+#define HI3620_PWMCLK0		196
+#define HI3620_PWMCLK1		197
+#define HI3620_UARTCLK0		198
+#define HI3620_UARTCLK1		199
+#define HI3620_UARTCLK2		200
+#define HI3620_UARTCLK3		201
+#define HI3620_UARTCLK4		202
+#define HI3620_SPICLK0		203
+#define HI3620_SPICLK1		204
+#define HI3620_SPICLK2		205
+#define HI3620_I2CCLK0		206
+#define HI3620_I2CCLK1		207
+#define HI3620_I2CCLK2		208
+#define HI3620_I2CCLK3		209
+#define HI3620_SCI_CLK		210
+#define HI3620_DDRC_PER_CLK	211
+#define HI3620_DMAC_CLK		212
+#define HI3620_USB2DVC_CLK	213
+#define HI3620_SD_CLK		214
+#define HI3620_MMC_CLK1		215
+#define HI3620_MMC_CLK2		216
+#define HI3620_MMC_CLK3		217
+#define HI3620_MCU_CLK		218
+
+#define HI3620_SD_CIUCLK	0
+#define HI3620_MMC_CIUCLK1	1
+#define HI3620_MMC_CIUCLK2	2
+#define HI3620_MMC_CIUCLK3	3
+
+#define HI3620_NR_CLKS		219
+
+#endif	/* __DTS_HI3620_CLOCK_H */

include/dt-bindings/clock/hi3660-clock.h

@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DTS_HI3660_CLOCK_H
+#define __DTS_HI3660_CLOCK_H
+
+/* fixed rate clocks */
+#define HI3660_CLKIN_SYS		0
+#define HI3660_CLKIN_REF		1
+#define HI3660_CLK_FLL_SRC		2
+#define HI3660_CLK_PPLL0		3
+#define HI3660_CLK_PPLL1		4
+#define HI3660_CLK_PPLL2		5
+#define HI3660_CLK_PPLL3		6
+#define HI3660_CLK_SCPLL		7
+#define HI3660_PCLK			8
+#define HI3660_CLK_UART0_DBG		9
+#define HI3660_CLK_UART6		10
+#define HI3660_OSC32K			11
+#define HI3660_OSC19M			12
+#define HI3660_CLK_480M			13
+#define HI3660_CLK_INV			14
+
+/* clk in crgctrl */
+#define HI3660_FACTOR_UART3		15
+#define HI3660_CLK_FACTOR_MMC		16
+#define HI3660_CLK_GATE_I2C0		17
+#define HI3660_CLK_GATE_I2C1		18
+#define HI3660_CLK_GATE_I2C2		19
+#define HI3660_CLK_GATE_I2C6		20
+#define HI3660_CLK_DIV_SYSBUS		21
+#define HI3660_CLK_DIV_320M		22
+#define HI3660_CLK_DIV_A53		23
+#define HI3660_CLK_GATE_SPI0		24
+#define HI3660_CLK_GATE_SPI2		25
+#define HI3660_PCIEPHY_REF		26
+#define HI3660_CLK_ABB_USB		27
+#define HI3660_HCLK_GATE_SDIO0		28
+#define HI3660_HCLK_GATE_SD		29
+#define HI3660_CLK_GATE_AOMM		30
+#define HI3660_PCLK_GPIO0		31
+#define HI3660_PCLK_GPIO1		32
+#define HI3660_PCLK_GPIO2		33
+#define HI3660_PCLK_GPIO3		34
+#define HI3660_PCLK_GPIO4		35
+#define HI3660_PCLK_GPIO5		36
+#define HI3660_PCLK_GPIO6		37
+#define HI3660_PCLK_GPIO7		38
+#define HI3660_PCLK_GPIO8		39
+#define HI3660_PCLK_GPIO9		40
+#define HI3660_PCLK_GPIO10		41
+#define HI3660_PCLK_GPIO11		42
+#define HI3660_PCLK_GPIO12		43
+#define HI3660_PCLK_GPIO13		44
+#define HI3660_PCLK_GPIO14		45
+#define HI3660_PCLK_GPIO15		46
+#define HI3660_PCLK_GPIO16		47
+#define HI3660_PCLK_GPIO17		48
+#define HI3660_PCLK_GPIO18		49
+#define HI3660_PCLK_GPIO19		50
+#define HI3660_PCLK_GPIO20		51
+#define HI3660_PCLK_GPIO21		52
+#define HI3660_CLK_GATE_SPI3		53
+#define HI3660_CLK_GATE_I2C7		54
+#define HI3660_CLK_GATE_I2C3		55
+#define HI3660_CLK_GATE_SPI1		56
+#define HI3660_CLK_GATE_UART1		57
+#define HI3660_CLK_GATE_UART2		58
+#define HI3660_CLK_GATE_UART4		59
+#define HI3660_CLK_GATE_UART5		60
+#define HI3660_CLK_GATE_I2C4		61
+#define HI3660_CLK_GATE_DMAC		62
+#define HI3660_PCLK_GATE_DSS		63
+#define HI3660_ACLK_GATE_DSS		64
+#define HI3660_CLK_GATE_LDI1		65
+#define HI3660_CLK_GATE_LDI0		66
+#define HI3660_CLK_GATE_VIVOBUS		67
+#define HI3660_CLK_GATE_EDC0		68
+#define HI3660_CLK_GATE_TXDPHY0_CFG	69
+#define HI3660_CLK_GATE_TXDPHY0_REF	70
+#define HI3660_CLK_GATE_TXDPHY1_CFG	71
+#define HI3660_CLK_GATE_TXDPHY1_REF	72
+#define HI3660_ACLK_GATE_USB3OTG	73
+#define HI3660_CLK_GATE_SPI4		74
+#define HI3660_CLK_GATE_SD		75
+#define HI3660_CLK_GATE_SDIO0		76
+#define HI3660_CLK_GATE_UFS_SUBSYS	77
+#define HI3660_PCLK_GATE_DSI0		78
+#define HI3660_PCLK_GATE_DSI1		79
+#define HI3660_ACLK_GATE_PCIE		80
+#define HI3660_PCLK_GATE_PCIE_SYS       81
+#define HI3660_CLK_GATE_PCIEAUX		82
+#define HI3660_PCLK_GATE_PCIE_PHY	83
+#define HI3660_CLK_ANDGT_LDI0		84
+#define HI3660_CLK_ANDGT_LDI1		85
+#define HI3660_CLK_ANDGT_EDC0		86
+#define HI3660_CLK_GATE_UFSPHY_GT	87
+#define HI3660_CLK_ANDGT_MMC		88
+#define HI3660_CLK_ANDGT_SD		89
+#define HI3660_CLK_A53HPM_ANDGT		90
+#define HI3660_CLK_ANDGT_SDIO		91
+#define HI3660_CLK_ANDGT_UART0		92
+#define HI3660_CLK_ANDGT_UART1		93
+#define HI3660_CLK_ANDGT_UARTH		94
+#define HI3660_CLK_ANDGT_SPI		95
+#define HI3660_CLK_VIVOBUS_ANDGT	96
+#define HI3660_CLK_AOMM_ANDGT		97
+#define HI3660_CLK_320M_PLL_GT		98
+#define HI3660_AUTODIV_EMMC0BUS		99
+#define HI3660_AUTODIV_SYSBUS		100
+#define HI3660_CLK_GATE_UFSPHY_CFG	101
+#define HI3660_CLK_GATE_UFSIO_REF	102
+#define HI3660_CLK_MUX_SYSBUS		103
+#define HI3660_CLK_MUX_UART0		104
+#define HI3660_CLK_MUX_UART1		105
+#define HI3660_CLK_MUX_UARTH		106
+#define HI3660_CLK_MUX_SPI		107
+#define HI3660_CLK_MUX_I2C		108
+#define HI3660_CLK_MUX_MMC_PLL		109
+#define HI3660_CLK_MUX_LDI1		110
+#define HI3660_CLK_MUX_LDI0		111
+#define HI3660_CLK_MUX_SD_PLL		112
+#define HI3660_CLK_MUX_SD_SYS		113
+#define HI3660_CLK_MUX_EDC0		114
+#define HI3660_CLK_MUX_SDIO_SYS		115
+#define HI3660_CLK_MUX_SDIO_PLL		116
+#define HI3660_CLK_MUX_VIVOBUS		117
+#define HI3660_CLK_MUX_A53HPM		118
+#define HI3660_CLK_MUX_320M		119
+#define HI3660_CLK_MUX_IOPERI		120
+#define HI3660_CLK_DIV_UART0		121
+#define HI3660_CLK_DIV_UART1		122
+#define HI3660_CLK_DIV_UARTH		123
+#define HI3660_CLK_DIV_MMC		124
+#define HI3660_CLK_DIV_SD		125
+#define HI3660_CLK_DIV_EDC0		126
+#define HI3660_CLK_DIV_LDI0		127
+#define HI3660_CLK_DIV_SDIO		128
+#define HI3660_CLK_DIV_LDI1		129
+#define HI3660_CLK_DIV_SPI		130
+#define HI3660_CLK_DIV_VIVOBUS		131
+#define HI3660_CLK_DIV_I2C		132
+#define HI3660_CLK_DIV_UFSPHY		133
+#define HI3660_CLK_DIV_CFGBUS		134
+#define HI3660_CLK_DIV_MMC0BUS		135
+#define HI3660_CLK_DIV_MMC1BUS		136
+#define HI3660_CLK_DIV_UFSPERI		137
+#define HI3660_CLK_DIV_AOMM		138
+#define HI3660_CLK_DIV_IOPERI		139
+#define HI3660_VENC_VOLT_HOLD		140
+#define HI3660_PERI_VOLT_HOLD		141
+#define HI3660_CLK_GATE_VENC		142
+#define HI3660_CLK_GATE_VDEC		143
+#define HI3660_CLK_ANDGT_VENC		144
+#define HI3660_CLK_ANDGT_VDEC		145
+#define HI3660_CLK_MUX_VENC		146
+#define HI3660_CLK_MUX_VDEC		147
+#define HI3660_CLK_DIV_VENC		148
+#define HI3660_CLK_DIV_VDEC		149
+#define HI3660_CLK_FAC_ISP_SNCLK	150
+#define HI3660_CLK_GATE_ISP_SNCLK0	151
+#define HI3660_CLK_GATE_ISP_SNCLK1	152
+#define HI3660_CLK_GATE_ISP_SNCLK2	153
+#define HI3660_CLK_ANGT_ISP_SNCLK	154
+#define HI3660_CLK_MUX_ISP_SNCLK	155
+#define HI3660_CLK_DIV_ISP_SNCLK	156
+
+/* clk in pmuctrl */
+#define HI3660_GATE_ABB_192		0
+
+/* clk in pctrl */
+#define HI3660_GATE_UFS_TCXO_EN		0
+#define HI3660_GATE_USB_TCXO_EN		1
+
+/* clk in sctrl */
+#define HI3660_PCLK_AO_GPIO0		0
+#define HI3660_PCLK_AO_GPIO1		1
+#define HI3660_PCLK_AO_GPIO2		2
+#define HI3660_PCLK_AO_GPIO3		3
+#define HI3660_PCLK_AO_GPIO4		4
+#define HI3660_PCLK_AO_GPIO5		5
+#define HI3660_PCLK_AO_GPIO6		6
+#define HI3660_PCLK_GATE_MMBUF		7
+#define HI3660_CLK_GATE_DSS_AXI_MM	8
+#define HI3660_PCLK_MMBUF_ANDGT		9
+#define HI3660_CLK_MMBUF_PLL_ANDGT	10
+#define HI3660_CLK_FLL_MMBUF_ANDGT	11
+#define HI3660_CLK_SYS_MMBUF_ANDGT	12
+#define HI3660_CLK_GATE_PCIEPHY_GT	13
+#define HI3660_ACLK_MUX_MMBUF		14
+#define HI3660_CLK_SW_MMBUF		15
+#define HI3660_CLK_DIV_AOBUS		16
+#define HI3660_PCLK_DIV_MMBUF		17
+#define HI3660_ACLK_DIV_MMBUF		18
+#define HI3660_CLK_DIV_PCIEPHY		19
+
+/* clk in iomcu */
+#define HI3660_CLK_I2C0_IOMCU		0
+#define HI3660_CLK_I2C1_IOMCU		1
+#define HI3660_CLK_I2C2_IOMCU		2
+#define HI3660_CLK_I2C6_IOMCU		3
+#define HI3660_CLK_IOMCU_PERI0		4
+
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0	0
+#define HI3660_CLK_STUB_CLUSTER1	1
+#define HI3660_CLK_STUB_GPU		2
+#define HI3660_CLK_STUB_DDR		3
+#define HI3660_CLK_STUB_NUM		4
+
+#endif	/* __DTS_HI3660_CLOCK_H */

include/dt-bindings/clock/hi6220-clock.h

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK	0
+
+/* fixed rate clocks */
+#define HI6220_REF32K		1
+#define HI6220_CLK_TCXO		2
+#define HI6220_MMC1_PAD		3
+#define HI6220_MMC2_PAD		4
+#define HI6220_MMC0_PAD		5
+#define HI6220_PLL_BBP		6
+#define HI6220_PLL_GPU		7
+#define HI6220_PLL1_DDR		8
+#define HI6220_PLL_SYS		9
+#define HI6220_PLL_SYS_MEDIA	10
+#define HI6220_DDR_SRC		11
+#define HI6220_PLL_MEDIA	12
+#define HI6220_PLL_DDR		13
+
+/* fixed factor clocks */
+#define HI6220_300M		14
+#define HI6220_150M		15
+#define HI6220_PICOPHY_SRC	16
+#define HI6220_MMC0_SRC_SEL	17
+#define HI6220_MMC1_SRC_SEL	18
+#define HI6220_MMC2_SRC_SEL	19
+#define HI6220_VPU_CODEC	20
+#define HI6220_MMC0_SMP		21
+#define HI6220_MMC1_SMP		22
+#define HI6220_MMC2_SMP		23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK	24
+#define HI6220_WDT1_PCLK	25
+#define HI6220_WDT2_PCLK	26
+#define HI6220_TIMER0_PCLK	27
+#define HI6220_TIMER1_PCLK	28
+#define HI6220_TIMER2_PCLK	29
+#define HI6220_TIMER3_PCLK	30
+#define HI6220_TIMER4_PCLK	31
+#define HI6220_TIMER5_PCLK	32
+#define HI6220_TIMER6_PCLK	33
+#define HI6220_TIMER7_PCLK	34
+#define HI6220_TIMER8_PCLK	35
+#define HI6220_UART0_PCLK	36
+#define HI6220_RTC0_PCLK	37
+#define HI6220_RTC1_PCLK	38
+#define HI6220_AO_NR_CLKS	39
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK		1
+#define HI6220_MMC0_CIUCLK	2
+#define HI6220_MMC1_CLK		3
+#define HI6220_MMC1_CIUCLK	4
+#define HI6220_MMC2_CLK		5
+#define HI6220_MMC2_CIUCLK	6
+#define HI6220_USBOTG_HCLK	7
+#define HI6220_CLK_PICOPHY	8
+#define HI6220_HIFI		9
+#define HI6220_DACODEC_PCLK	10
+#define HI6220_EDMAC_ACLK	11
+#define HI6220_CS_ATB		12
+#define HI6220_I2C0_CLK		13
+#define HI6220_I2C1_CLK		14
+#define HI6220_I2C2_CLK		15
+#define HI6220_I2C3_CLK		16
+#define HI6220_UART1_PCLK	17
+#define HI6220_UART2_PCLK	18
+#define HI6220_UART3_PCLK	19
+#define HI6220_UART4_PCLK	20
+#define HI6220_SPI_CLK		21
+#define HI6220_TSENSOR_CLK	22
+#define HI6220_MMU_CLK		23
+#define HI6220_HIFI_SEL		24
+#define HI6220_MMC0_SYSPLL	25
+#define HI6220_MMC1_SYSPLL	26
+#define HI6220_MMC2_SYSPLL	27
+#define HI6220_MMC0_SEL		28
+#define HI6220_MMC1_SEL		29
+#define HI6220_BBPPLL_SEL	30
+#define HI6220_MEDIA_PLL_SRC	31
+#define HI6220_MMC2_SEL		32
+#define HI6220_CS_ATB_SYSPLL	33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC		34
+#define HI6220_MMC0_SMP_IN	35
+#define HI6220_MMC1_SRC		36
+#define HI6220_MMC1_SMP_IN	37
+#define HI6220_MMC2_SRC		38
+#define HI6220_MMC2_SMP_IN	39
+#define HI6220_HIFI_SRC		40
+#define HI6220_UART1_SRC	41
+#define HI6220_UART2_SRC	42
+#define HI6220_UART3_SRC	43
+#define HI6220_UART4_SRC	44
+#define HI6220_MMC0_MUX0	45
+#define HI6220_MMC1_MUX0	46
+#define HI6220_MMC2_MUX0	47
+#define HI6220_MMC0_MUX1	48
+#define HI6220_MMC1_MUX1	49
+#define HI6220_MMC2_MUX1	50
+
+/* divider clocks */
+#define HI6220_CLK_BUS		51
+#define HI6220_MMC0_DIV		52
+#define HI6220_MMC1_DIV		53
+#define HI6220_MMC2_DIV		54
+#define HI6220_HIFI_DIV		55
+#define HI6220_BBPPLL0_DIV	56
+#define HI6220_CS_DAPB		57
+#define HI6220_CS_ATB_DIV	58
+
+/* gate clock */
+#define HI6220_DAPB_CLK		59
+
+#define HI6220_SYS_NR_CLKS	60
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK		1
+#define HI6220_G3D_PCLK		2
+#define HI6220_ACLK_CODEC_VPU	3
+#define HI6220_ISP_SCLK		4
+#define HI6220_ADE_CORE		5
+#define HI6220_MED_MMU		6
+#define HI6220_CFG_CSI4PHY	7
+#define HI6220_CFG_CSI2PHY	8
+#define HI6220_ISP_SCLK_GATE	9
+#define HI6220_ISP_SCLK_GATE1	10
+#define HI6220_ADE_CORE_GATE	11
+#define HI6220_CODEC_VPU_GATE	12
+#define HI6220_MED_SYSPLL	13
+
+/* mux clocks */
+#define HI6220_1440_1200	14
+#define HI6220_1000_1200	15
+#define HI6220_1000_1440	16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG	17
+#define HI6220_ISP_SCLK_SRC	18
+#define HI6220_ISP_SCLK1	19
+#define HI6220_ADE_CORE_SRC	20
+#define HI6220_ADE_PIX_SRC	21
+#define HI6220_G3D_CLK		22
+#define HI6220_CODEC_VPU_SRC	23
+
+#define HI6220_MEDIA_NR_CLKS	24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE	1
+#define HI6220_PLL1_DDR_GATE	2
+#define HI6220_PLL_DDR_GATE	3
+#define HI6220_PLL_MEDIA_GATE	4
+#define HI6220_PLL0_BBP_GATE	5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC		6
+#define HI6220_DDRC_AXI1	7
+
+#define HI6220_POWER_NR_CLKS	8
+
+/* clk in Hi6220 acpu sctrl */
+#define HI6220_ACPU_SFT_AT_S		0
+
+#endif

include/dt-bindings/clock/hip04-clock.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DTS_HIP04_CLOCK_H
+#define __DTS_HIP04_CLOCK_H
+
+#define HIP04_NONE_CLOCK	0
+
+/* fixed rate & fixed factor clocks */
+#define HIP04_OSC50M		1
+#define HIP04_CLK_50M		2
+#define HIP04_CLK_168M		3
+
+#define HIP04_NR_CLKS		64
+
+#endif	/* __DTS_HIP04_CLOCK_H */

include/dt-bindings/clock/histb-clock.h

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK			0
+#define HISTB_APB_CLK			1
+#define HISTB_AHB_CLK			2
+#define HISTB_UART1_CLK			3
+#define HISTB_UART2_CLK			4
+#define HISTB_UART3_CLK			5
+#define HISTB_I2C0_CLK			6
+#define HISTB_I2C1_CLK			7
+#define HISTB_I2C2_CLK			8
+#define HISTB_I2C3_CLK			9
+#define HISTB_I2C4_CLK			10
+#define HISTB_I2C5_CLK			11
+#define HISTB_SPI0_CLK			12
+#define HISTB_SPI1_CLK			13
+#define HISTB_SPI2_CLK			14
+#define HISTB_SCI_CLK			15
+#define HISTB_FMC_CLK			16
+#define HISTB_MMC_BIU_CLK		17
+#define HISTB_MMC_CIU_CLK		18
+#define HISTB_MMC_DRV_CLK		19
+#define HISTB_MMC_SAMPLE_CLK		20
+#define HISTB_SDIO0_BIU_CLK		21
+#define HISTB_SDIO0_CIU_CLK		22
+#define HISTB_SDIO0_DRV_CLK		23
+#define HISTB_SDIO0_SAMPLE_CLK		24
+#define HISTB_PCIE_AUX_CLK		25
+#define HISTB_PCIE_PIPE_CLK		26
+#define HISTB_PCIE_SYS_CLK		27
+#define HISTB_PCIE_BUS_CLK		28
+#define HISTB_ETH0_MAC_CLK		29
+#define HISTB_ETH0_MACIF_CLK		30
+#define HISTB_ETH1_MAC_CLK		31
+#define HISTB_ETH1_MACIF_CLK		32
+#define HISTB_COMBPHY1_CLK		33
+#define HISTB_USB2_BUS_CLK		34
+#define HISTB_USB2_PHY_CLK		35
+#define HISTB_USB2_UTMI_CLK		36
+#define HISTB_USB2_12M_CLK		37
+#define HISTB_USB2_48M_CLK		38
+#define HISTB_USB2_OTG_UTMI_CLK		39
+#define HISTB_USB2_PHY1_REF_CLK		40
+#define HISTB_USB2_PHY2_REF_CLK		41
+#define HISTB_COMBPHY0_CLK		42
+#define HISTB_USB3_BUS_CLK		43
+#define HISTB_USB3_UTMI_CLK		44
+#define HISTB_USB3_PIPE_CLK		45
+#define HISTB_USB3_SUSPEND_CLK		46
+#define HISTB_USB3_BUS_CLK1		47
+#define HISTB_USB3_UTMI_CLK1		48
+#define HISTB_USB3_PIPE_CLK1		49
+#define HISTB_USB3_SUSPEND_CLK1		50
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK			1
+#define HISTB_IR_CLK			2
+#define HISTB_TIMER01_CLK		3
+#define HISTB_LEDC_CLK			4
+#define HISTB_UART0_CLK			5
+#define HISTB_LSADC_CLK			6
+
+#endif	/* __DTS_HISTB_CLOCK_H */

include/dt-bindings/clock/hix5hd2-clock.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_HIX5HD2_CLOCK_H
+#define __DTS_HIX5HD2_CLOCK_H
+
+/* fixed rate */
+#define HIX5HD2_FIXED_1200M		1
+#define HIX5HD2_FIXED_400M		2
+#define HIX5HD2_FIXED_48M		3
+#define HIX5HD2_FIXED_24M		4
+#define HIX5HD2_FIXED_600M		5
+#define HIX5HD2_FIXED_300M		6
+#define HIX5HD2_FIXED_75M		7
+#define HIX5HD2_FIXED_200M		8
+#define HIX5HD2_FIXED_100M		9
+#define HIX5HD2_FIXED_40M		10
+#define HIX5HD2_FIXED_150M		11
+#define HIX5HD2_FIXED_1728M		12
+#define HIX5HD2_FIXED_28P8M		13
+#define HIX5HD2_FIXED_432M		14
+#define HIX5HD2_FIXED_345P6M		15
+#define HIX5HD2_FIXED_288M		16
+#define HIX5HD2_FIXED_60M		17
+#define HIX5HD2_FIXED_750M		18
+#define HIX5HD2_FIXED_500M		19
+#define HIX5HD2_FIXED_54M		20
+#define HIX5HD2_FIXED_27M		21
+#define HIX5HD2_FIXED_1500M		22
+#define HIX5HD2_FIXED_375M		23
+#define HIX5HD2_FIXED_187M		24
+#define HIX5HD2_FIXED_250M		25
+#define HIX5HD2_FIXED_125M		26
+#define HIX5HD2_FIXED_2P02M		27
+#define HIX5HD2_FIXED_50M		28
+#define HIX5HD2_FIXED_25M		29
+#define HIX5HD2_FIXED_83M		30
+
+/* mux clocks */
+#define HIX5HD2_SFC_MUX			64
+#define HIX5HD2_MMC_MUX			65
+#define HIX5HD2_FEPHY_MUX		66
+#define HIX5HD2_SD_MUX			67
+
+/* gate clocks */
+#define HIX5HD2_SFC_RST			128
+#define HIX5HD2_SFC_CLK			129
+#define HIX5HD2_MMC_CIU_CLK		130
+#define HIX5HD2_MMC_BIU_CLK		131
+#define HIX5HD2_MMC_CIU_RST		132
+#define HIX5HD2_FWD_BUS_CLK		133
+#define HIX5HD2_FWD_SYS_CLK		134
+#define HIX5HD2_MAC0_PHY_CLK		135
+#define HIX5HD2_SD_CIU_CLK		136
+#define HIX5HD2_SD_BIU_CLK		137
+#define HIX5HD2_SD_CIU_RST		138
+#define HIX5HD2_WDG0_CLK		139
+#define HIX5HD2_WDG0_RST		140
+#define HIX5HD2_I2C0_CLK		141
+#define HIX5HD2_I2C0_RST		142
+#define HIX5HD2_I2C1_CLK		143
+#define HIX5HD2_I2C1_RST		144
+#define HIX5HD2_I2C2_CLK		145
+#define HIX5HD2_I2C2_RST		146
+#define HIX5HD2_I2C3_CLK		147
+#define HIX5HD2_I2C3_RST		148
+#define HIX5HD2_I2C4_CLK		149
+#define HIX5HD2_I2C4_RST		150
+#define HIX5HD2_I2C5_CLK		151
+#define HIX5HD2_I2C5_RST		152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK		192
+#define HIX5HD2_MAC1_CLK		193
+#define HIX5HD2_SATA_CLK		194
+#define HIX5HD2_USB_CLK			195
+
+#define HIX5HD2_NR_CLKS			256
+#endif	/* __DTS_HIX5HD2_CLOCK_H */

include/dt-bindings/clock/imx1-clock.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX1_H
+#define __DT_BINDINGS_CLOCK_IMX1_H
+
+#define IMX1_CLK_DUMMY		0
+#define IMX1_CLK_CLK32		1
+#define IMX1_CLK_CLK16M_EXT	2
+#define IMX1_CLK_CLK16M		3
+#define IMX1_CLK_CLK32_PREMULT	4
+#define IMX1_CLK_PREM		5
+#define IMX1_CLK_MPLL		6
+#define IMX1_CLK_MPLL_GATE	7
+#define IMX1_CLK_SPLL		8
+#define IMX1_CLK_SPLL_GATE	9
+#define IMX1_CLK_MCU		10
+#define IMX1_CLK_FCLK		11
+#define IMX1_CLK_HCLK		12
+#define IMX1_CLK_CLK48M		13
+#define IMX1_CLK_PER1		14
+#define IMX1_CLK_PER2		15
+#define IMX1_CLK_PER3		16
+#define IMX1_CLK_CLKO		17
+#define IMX1_CLK_UART3_GATE	18
+#define IMX1_CLK_SSI2_GATE	19
+#define IMX1_CLK_BROM_GATE	20
+#define IMX1_CLK_DMA_GATE	21
+#define IMX1_CLK_CSI_GATE	22
+#define IMX1_CLK_MMA_GATE	23
+#define IMX1_CLK_USBD_GATE	24
+#define IMX1_CLK_MAX		25
+
+#endif

include/dt-bindings/clock/imx21-clock.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX21_H
+#define __DT_BINDINGS_CLOCK_IMX21_H
+
+#define IMX21_CLK_DUMMY			0
+#define IMX21_CLK_CKIL			1
+#define IMX21_CLK_CKIH			2
+#define IMX21_CLK_FPM			3
+#define IMX21_CLK_CKIH_DIV1P5		4
+#define IMX21_CLK_MPLL_GATE		5
+#define IMX21_CLK_SPLL_GATE		6
+#define IMX21_CLK_FPM_GATE		7
+#define IMX21_CLK_CKIH_GATE		8
+#define IMX21_CLK_MPLL_OSC_SEL		9
+#define IMX21_CLK_IPG			10
+#define IMX21_CLK_HCLK			11
+#define IMX21_CLK_MPLL_SEL		12
+#define IMX21_CLK_SPLL_SEL		13
+#define IMX21_CLK_SSI1_SEL		14
+#define IMX21_CLK_SSI2_SEL		15
+#define IMX21_CLK_USB_DIV		16
+#define IMX21_CLK_FCLK			17
+#define IMX21_CLK_MPLL			18
+#define IMX21_CLK_SPLL			19
+#define IMX21_CLK_NFC_DIV		20
+#define IMX21_CLK_SSI1_DIV		21
+#define IMX21_CLK_SSI2_DIV		22
+#define IMX21_CLK_PER1			23
+#define IMX21_CLK_PER2			24
+#define IMX21_CLK_PER3			25
+#define IMX21_CLK_PER4			26
+#define IMX21_CLK_UART1_IPG_GATE	27
+#define IMX21_CLK_UART2_IPG_GATE	28
+#define IMX21_CLK_UART3_IPG_GATE	29
+#define IMX21_CLK_UART4_IPG_GATE	30
+#define IMX21_CLK_CSPI1_IPG_GATE	31
+#define IMX21_CLK_CSPI2_IPG_GATE	32
+#define IMX21_CLK_SSI1_GATE		33
+#define IMX21_CLK_SSI2_GATE		34
+#define IMX21_CLK_SDHC1_IPG_GATE	35
+#define IMX21_CLK_SDHC2_IPG_GATE	36
+#define IMX21_CLK_GPIO_GATE		37
+#define IMX21_CLK_I2C_GATE		38
+#define IMX21_CLK_DMA_GATE		39
+#define IMX21_CLK_USB_GATE		40
+#define IMX21_CLK_EMMA_GATE		41
+#define IMX21_CLK_SSI2_BAUD_GATE	42
+#define IMX21_CLK_SSI1_BAUD_GATE	43
+#define IMX21_CLK_LCDC_IPG_GATE		44
+#define IMX21_CLK_NFC_GATE		45
+#define IMX21_CLK_LCDC_HCLK_GATE	46
+#define IMX21_CLK_PER4_GATE		47
+#define IMX21_CLK_BMI_GATE		48
+#define IMX21_CLK_USB_HCLK_GATE		49
+#define IMX21_CLK_SLCDC_GATE		50
+#define IMX21_CLK_SLCDC_HCLK_GATE	51
+#define IMX21_CLK_EMMA_HCLK_GATE	52
+#define IMX21_CLK_BROM_GATE		53
+#define IMX21_CLK_DMA_HCLK_GATE		54
+#define IMX21_CLK_CSI_HCLK_GATE		55
+#define IMX21_CLK_CSPI3_IPG_GATE	56
+#define IMX21_CLK_WDOG_GATE		57
+#define IMX21_CLK_GPT1_IPG_GATE		58
+#define IMX21_CLK_GPT2_IPG_GATE		59
+#define IMX21_CLK_GPT3_IPG_GATE		60
+#define IMX21_CLK_PWM_IPG_GATE		61
+#define IMX21_CLK_RTC_GATE		62
+#define IMX21_CLK_KPP_GATE		63
+#define IMX21_CLK_OWIRE_GATE		64
+#define IMX21_CLK_MAX			65
+
+#endif

include/dt-bindings/clock/imx27-clock.h

@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX27_H
+#define __DT_BINDINGS_CLOCK_IMX27_H
+
+#define IMX27_CLK_DUMMY			0
+#define IMX27_CLK_CKIH			1
+#define IMX27_CLK_CKIL			2
+#define IMX27_CLK_MPLL			3
+#define IMX27_CLK_SPLL			4
+#define IMX27_CLK_MPLL_MAIN2		5
+#define IMX27_CLK_AHB			6
+#define IMX27_CLK_IPG			7
+#define IMX27_CLK_NFC_DIV		8
+#define IMX27_CLK_PER1_DIV		9
+#define IMX27_CLK_PER2_DIV		10
+#define IMX27_CLK_PER3_DIV		11
+#define IMX27_CLK_PER4_DIV		12
+#define IMX27_CLK_VPU_SEL		13
+#define IMX27_CLK_VPU_DIV		14
+#define IMX27_CLK_USB_DIV		15
+#define IMX27_CLK_CPU_SEL		16
+#define IMX27_CLK_CLKO_SEL		17
+#define IMX27_CLK_CPU_DIV		18
+#define IMX27_CLK_CLKO_DIV		19
+#define IMX27_CLK_SSI1_SEL		20
+#define IMX27_CLK_SSI2_SEL		21
+#define IMX27_CLK_SSI1_DIV		22
+#define IMX27_CLK_SSI2_DIV		23
+#define IMX27_CLK_CLKO_EN		24
+#define IMX27_CLK_SSI2_IPG_GATE		25
+#define IMX27_CLK_SSI1_IPG_GATE		26
+#define IMX27_CLK_SLCDC_IPG_GATE	27
+#define IMX27_CLK_SDHC3_IPG_GATE	28
+#define IMX27_CLK_SDHC2_IPG_GATE	29
+#define IMX27_CLK_SDHC1_IPG_GATE	30
+#define IMX27_CLK_SCC_IPG_GATE		31
+#define IMX27_CLK_SAHARA_IPG_GATE	32
+#define IMX27_CLK_RTC_IPG_GATE		33
+#define IMX27_CLK_PWM_IPG_GATE		34
+#define IMX27_CLK_OWIRE_IPG_GATE	35
+#define IMX27_CLK_LCDC_IPG_GATE		36
+#define IMX27_CLK_KPP_IPG_GATE		37
+#define IMX27_CLK_IIM_IPG_GATE		38
+#define IMX27_CLK_I2C2_IPG_GATE		39
+#define IMX27_CLK_I2C1_IPG_GATE		40
+#define IMX27_CLK_GPT6_IPG_GATE		41
+#define IMX27_CLK_GPT5_IPG_GATE		42
+#define IMX27_CLK_GPT4_IPG_GATE		43
+#define IMX27_CLK_GPT3_IPG_GATE		44
+#define IMX27_CLK_GPT2_IPG_GATE		45
+#define IMX27_CLK_GPT1_IPG_GATE		46
+#define IMX27_CLK_GPIO_IPG_GATE		47
+#define IMX27_CLK_FEC_IPG_GATE		48
+#define IMX27_CLK_EMMA_IPG_GATE		49
+#define IMX27_CLK_DMA_IPG_GATE		50
+#define IMX27_CLK_CSPI3_IPG_GATE	51
+#define IMX27_CLK_CSPI2_IPG_GATE	52
+#define IMX27_CLK_CSPI1_IPG_GATE	53
+#define IMX27_CLK_NFC_BAUD_GATE		54
+#define IMX27_CLK_SSI2_BAUD_GATE	55
+#define IMX27_CLK_SSI1_BAUD_GATE	56
+#define IMX27_CLK_VPU_BAUD_GATE		57
+#define IMX27_CLK_PER4_GATE		58
+#define IMX27_CLK_PER3_GATE		59
+#define IMX27_CLK_PER2_GATE		60
+#define IMX27_CLK_PER1_GATE		61
+#define IMX27_CLK_USB_AHB_GATE		62
+#define IMX27_CLK_SLCDC_AHB_GATE	63
+#define IMX27_CLK_SAHARA_AHB_GATE	64
+#define IMX27_CLK_LCDC_AHB_GATE		65
+#define IMX27_CLK_VPU_AHB_GATE		66
+#define IMX27_CLK_FEC_AHB_GATE		67
+#define IMX27_CLK_EMMA_AHB_GATE		68
+#define IMX27_CLK_EMI_AHB_GATE		69
+#define IMX27_CLK_DMA_AHB_GATE		70
+#define IMX27_CLK_CSI_AHB_GATE		71
+#define IMX27_CLK_BROM_AHB_GATE		72
+#define IMX27_CLK_ATA_AHB_GATE		73
+#define IMX27_CLK_WDOG_IPG_GATE		74
+#define IMX27_CLK_USB_IPG_GATE		75
+#define IMX27_CLK_UART6_IPG_GATE	76
+#define IMX27_CLK_UART5_IPG_GATE	77
+#define IMX27_CLK_UART4_IPG_GATE	78
+#define IMX27_CLK_UART3_IPG_GATE	79
+#define IMX27_CLK_UART2_IPG_GATE	80
+#define IMX27_CLK_UART1_IPG_GATE	81
+#define IMX27_CLK_CKIH_DIV1P5		82
+#define IMX27_CLK_FPM			83
+#define IMX27_CLK_MPLL_OSC_SEL		84
+#define IMX27_CLK_MPLL_SEL		85
+#define IMX27_CLK_SPLL_GATE		86
+#define IMX27_CLK_MSHC_DIV		87
+#define IMX27_CLK_RTIC_IPG_GATE		88
+#define IMX27_CLK_MSHC_IPG_GATE		89
+#define IMX27_CLK_RTIC_AHB_GATE		90
+#define IMX27_CLK_MSHC_BAUD_GATE	91
+#define IMX27_CLK_CKIH_GATE		92
+#define IMX27_CLK_MAX			93
+
+#endif

include/dt-bindings/clock/imx5-clock.h

@@ -0,0 +1,219 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY			0
+#define IMX5_CLK_CKIL			1
+#define IMX5_CLK_OSC			2
+#define IMX5_CLK_CKIH1			3
+#define IMX5_CLK_CKIH2			4
+#define IMX5_CLK_AHB			5
+#define IMX5_CLK_IPG			6
+#define IMX5_CLK_AXI_A			7
+#define IMX5_CLK_AXI_B			8
+#define IMX5_CLK_UART_PRED		9
+#define IMX5_CLK_UART_ROOT		10
+#define IMX5_CLK_ESDHC_A_PRED		11
+#define IMX5_CLK_ESDHC_B_PRED		12
+#define IMX5_CLK_ESDHC_C_SEL		13
+#define IMX5_CLK_ESDHC_D_SEL		14
+#define IMX5_CLK_EMI_SEL		15
+#define IMX5_CLK_EMI_SLOW_PODF		16
+#define IMX5_CLK_NFC_PODF		17
+#define IMX5_CLK_ECSPI_PRED		18
+#define IMX5_CLK_ECSPI_PODF		19
+#define IMX5_CLK_USBOH3_PRED		20
+#define IMX5_CLK_USBOH3_PODF		21
+#define IMX5_CLK_USB_PHY_PRED		22
+#define IMX5_CLK_USB_PHY_PODF		23
+#define IMX5_CLK_CPU_PODF		24
+#define IMX5_CLK_DI_PRED		25
+#define IMX5_CLK_TVE_SEL		27
+#define IMX5_CLK_UART1_IPG_GATE		28
+#define IMX5_CLK_UART1_PER_GATE		29
+#define IMX5_CLK_UART2_IPG_GATE		30
+#define IMX5_CLK_UART2_PER_GATE		31
+#define IMX5_CLK_UART3_IPG_GATE		32
+#define IMX5_CLK_UART3_PER_GATE		33
+#define IMX5_CLK_I2C1_GATE		34
+#define IMX5_CLK_I2C2_GATE		35
+#define IMX5_CLK_GPT_IPG_GATE		36
+#define IMX5_CLK_PWM1_IPG_GATE		37
+#define IMX5_CLK_PWM1_HF_GATE		38
+#define IMX5_CLK_PWM2_IPG_GATE		39
+#define IMX5_CLK_PWM2_HF_GATE		40
+#define IMX5_CLK_GPT_HF_GATE		41
+#define IMX5_CLK_FEC_GATE		42
+#define IMX5_CLK_USBOH3_PER_GATE	43
+#define IMX5_CLK_ESDHC1_IPG_GATE	44
+#define IMX5_CLK_ESDHC2_IPG_GATE	45
+#define IMX5_CLK_ESDHC3_IPG_GATE	46
+#define IMX5_CLK_ESDHC4_IPG_GATE	47
+#define IMX5_CLK_SSI1_IPG_GATE		48
+#define IMX5_CLK_SSI2_IPG_GATE		49
+#define IMX5_CLK_SSI3_IPG_GATE		50
+#define IMX5_CLK_ECSPI1_IPG_GATE	51
+#define IMX5_CLK_ECSPI1_PER_GATE	52
+#define IMX5_CLK_ECSPI2_IPG_GATE	53
+#define IMX5_CLK_ECSPI2_PER_GATE	54
+#define IMX5_CLK_CSPI_IPG_GATE		55
+#define IMX5_CLK_SDMA_GATE		56
+#define IMX5_CLK_EMI_SLOW_GATE		57
+#define IMX5_CLK_IPU_SEL		58
+#define IMX5_CLK_IPU_GATE		59
+#define IMX5_CLK_NFC_GATE		60
+#define IMX5_CLK_IPU_DI1_GATE		61
+#define IMX5_CLK_VPU_SEL		62
+#define IMX5_CLK_VPU_GATE		63
+#define IMX5_CLK_VPU_REFERENCE_GATE	64
+#define IMX5_CLK_UART4_IPG_GATE		65
+#define IMX5_CLK_UART4_PER_GATE		66
+#define IMX5_CLK_UART5_IPG_GATE		67
+#define IMX5_CLK_UART5_PER_GATE		68
+#define IMX5_CLK_TVE_GATE		69
+#define IMX5_CLK_TVE_PRED		70
+#define IMX5_CLK_ESDHC1_PER_GATE	71
+#define IMX5_CLK_ESDHC2_PER_GATE	72
+#define IMX5_CLK_ESDHC3_PER_GATE	73
+#define IMX5_CLK_ESDHC4_PER_GATE	74
+#define IMX5_CLK_USB_PHY_GATE		75
+#define IMX5_CLK_HSI2C_GATE		76
+#define IMX5_CLK_MIPI_HSC1_GATE		77
+#define IMX5_CLK_MIPI_HSC2_GATE		78
+#define IMX5_CLK_MIPI_ESC_GATE		79
+#define IMX5_CLK_MIPI_HSP_GATE		80
+#define IMX5_CLK_LDB_DI1_DIV_3_5	81
+#define IMX5_CLK_LDB_DI1_DIV		82
+#define IMX5_CLK_LDB_DI0_DIV_3_5	83
+#define IMX5_CLK_LDB_DI0_DIV		84
+#define IMX5_CLK_LDB_DI1_GATE		85
+#define IMX5_CLK_CAN2_SERIAL_GATE	86
+#define IMX5_CLK_CAN2_IPG_GATE		87
+#define IMX5_CLK_I2C3_GATE		88
+#define IMX5_CLK_LP_APM			89
+#define IMX5_CLK_PERIPH_APM		90
+#define IMX5_CLK_MAIN_BUS		91
+#define IMX5_CLK_AHB_MAX		92
+#define IMX5_CLK_AIPS_TZ1		93
+#define IMX5_CLK_AIPS_TZ2		94
+#define IMX5_CLK_TMAX1			95
+#define IMX5_CLK_TMAX2			96
+#define IMX5_CLK_TMAX3			97
+#define IMX5_CLK_SPBA			98
+#define IMX5_CLK_UART_SEL		99
+#define IMX5_CLK_ESDHC_A_SEL		100
+#define IMX5_CLK_ESDHC_B_SEL		101
+#define IMX5_CLK_ESDHC_A_PODF		102
+#define IMX5_CLK_ESDHC_B_PODF		103
+#define IMX5_CLK_ECSPI_SEL		104
+#define IMX5_CLK_USBOH3_SEL		105
+#define IMX5_CLK_USB_PHY_SEL		106
+#define IMX5_CLK_IIM_GATE		107
+#define IMX5_CLK_USBOH3_GATE		108
+#define IMX5_CLK_EMI_FAST_GATE		109
+#define IMX5_CLK_IPU_DI0_GATE		110
+#define IMX5_CLK_GPC_DVFS		111
+#define IMX5_CLK_PLL1_SW		112
+#define IMX5_CLK_PLL2_SW		113
+#define IMX5_CLK_PLL3_SW		114
+#define IMX5_CLK_IPU_DI0_SEL		115
+#define IMX5_CLK_IPU_DI1_SEL		116
+#define IMX5_CLK_TVE_EXT_SEL		117
+#define IMX5_CLK_MX51_MIPI		118
+#define IMX5_CLK_PLL4_SW		119
+#define IMX5_CLK_LDB_DI1_SEL		120
+#define IMX5_CLK_DI_PLL4_PODF		121
+#define IMX5_CLK_LDB_DI0_SEL		122
+#define IMX5_CLK_LDB_DI0_GATE		123
+#define IMX5_CLK_USB_PHY1_GATE		124
+#define IMX5_CLK_USB_PHY2_GATE		125
+#define IMX5_CLK_PER_LP_APM		126
+#define IMX5_CLK_PER_PRED1		127
+#define IMX5_CLK_PER_PRED2		128
+#define IMX5_CLK_PER_PODF		129
+#define IMX5_CLK_PER_ROOT		130
+#define IMX5_CLK_SSI_APM		131
+#define IMX5_CLK_SSI1_ROOT_SEL		132
+#define IMX5_CLK_SSI2_ROOT_SEL		133
+#define IMX5_CLK_SSI3_ROOT_SEL		134
+#define IMX5_CLK_SSI_EXT1_SEL		135
+#define IMX5_CLK_SSI_EXT2_SEL		136
+#define IMX5_CLK_SSI_EXT1_COM_SEL	137
+#define IMX5_CLK_SSI_EXT2_COM_SEL	138
+#define IMX5_CLK_SSI1_ROOT_PRED		139
+#define IMX5_CLK_SSI1_ROOT_PODF		140
+#define IMX5_CLK_SSI2_ROOT_PRED		141
+#define IMX5_CLK_SSI2_ROOT_PODF		142
+#define IMX5_CLK_SSI_EXT1_PRED		143
+#define IMX5_CLK_SSI_EXT1_PODF		144
+#define IMX5_CLK_SSI_EXT2_PRED		145
+#define IMX5_CLK_SSI_EXT2_PODF		146
+#define IMX5_CLK_SSI1_ROOT_GATE		147
+#define IMX5_CLK_SSI2_ROOT_GATE		148
+#define IMX5_CLK_SSI3_ROOT_GATE		149
+#define IMX5_CLK_SSI_EXT1_GATE		150
+#define IMX5_CLK_SSI_EXT2_GATE		151
+#define IMX5_CLK_EPIT1_IPG_GATE		152
+#define IMX5_CLK_EPIT1_HF_GATE		153
+#define IMX5_CLK_EPIT2_IPG_GATE		154
+#define IMX5_CLK_EPIT2_HF_GATE		155
+#define IMX5_CLK_CAN_SEL		156
+#define IMX5_CLK_CAN1_SERIAL_GATE	157
+#define IMX5_CLK_CAN1_IPG_GATE		158
+#define IMX5_CLK_OWIRE_GATE		159
+#define IMX5_CLK_GPU3D_SEL		160
+#define IMX5_CLK_GPU2D_SEL		161
+#define IMX5_CLK_GPU3D_GATE		162
+#define IMX5_CLK_GPU2D_GATE		163
+#define IMX5_CLK_GARB_GATE		164
+#define IMX5_CLK_CKO1_SEL		165
+#define IMX5_CLK_CKO1_PODF		166
+#define IMX5_CLK_CKO1			167
+#define IMX5_CLK_CKO2_SEL		168
+#define IMX5_CLK_CKO2_PODF		169
+#define IMX5_CLK_CKO2			170
+#define IMX5_CLK_SRTC_GATE		171
+#define IMX5_CLK_PATA_GATE		172
+#define IMX5_CLK_SATA_GATE		173
+#define IMX5_CLK_SPDIF_XTAL_SEL		174
+#define IMX5_CLK_SPDIF0_SEL		175
+#define IMX5_CLK_SPDIF1_SEL		176
+#define IMX5_CLK_SPDIF0_PRED		177
+#define IMX5_CLK_SPDIF0_PODF		178
+#define IMX5_CLK_SPDIF1_PRED		179
+#define IMX5_CLK_SPDIF1_PODF		180
+#define IMX5_CLK_SPDIF0_COM_SEL		181
+#define IMX5_CLK_SPDIF1_COM_SEL		182
+#define IMX5_CLK_SPDIF0_GATE		183
+#define IMX5_CLK_SPDIF1_GATE		184
+#define IMX5_CLK_SPDIF_IPG_GATE		185
+#define IMX5_CLK_OCRAM			186
+#define IMX5_CLK_SAHARA_IPG_GATE	187
+#define IMX5_CLK_SATA_REF		188
+#define IMX5_CLK_STEP_SEL		189
+#define IMX5_CLK_CPU_PODF_SEL		190
+#define IMX5_CLK_ARM			191
+#define IMX5_CLK_FIRI_PRED		192
+#define IMX5_CLK_FIRI_SEL		193
+#define IMX5_CLK_FIRI_PODF		194
+#define IMX5_CLK_FIRI_SERIAL_GATE	195
+#define IMX5_CLK_FIRI_IPG_GATE		196
+#define IMX5_CLK_CSI0_MCLK1_PRED	197
+#define IMX5_CLK_CSI0_MCLK1_SEL		198
+#define IMX5_CLK_CSI0_MCLK1_PODF	199
+#define IMX5_CLK_CSI0_MCLK1_GATE	200
+#define IMX5_CLK_IEEE1588_PRED		201
+#define IMX5_CLK_IEEE1588_SEL		202
+#define IMX5_CLK_IEEE1588_PODF		203
+#define IMX5_CLK_IEEE1588_GATE		204
+#define IMX5_CLK_END			205
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */

include/dt-bindings/clock/imx6qdl-clock.h

@@ -0,0 +1,278 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY			0
+#define IMX6QDL_CLK_CKIL			1
+#define IMX6QDL_CLK_CKIH			2
+#define IMX6QDL_CLK_OSC				3
+#define IMX6QDL_CLK_PLL2_PFD0_352M		4
+#define IMX6QDL_CLK_PLL2_PFD1_594M		5
+#define IMX6QDL_CLK_PLL2_PFD2_396M		6
+#define IMX6QDL_CLK_PLL3_PFD0_720M		7
+#define IMX6QDL_CLK_PLL3_PFD1_540M		8
+#define IMX6QDL_CLK_PLL3_PFD2_508M		9
+#define IMX6QDL_CLK_PLL3_PFD3_454M		10
+#define IMX6QDL_CLK_PLL2_198M			11
+#define IMX6QDL_CLK_PLL3_120M			12
+#define IMX6QDL_CLK_PLL3_80M			13
+#define IMX6QDL_CLK_PLL3_60M			14
+#define IMX6QDL_CLK_TWD				15
+#define IMX6QDL_CLK_STEP			16
+#define IMX6QDL_CLK_PLL1_SW			17
+#define IMX6QDL_CLK_PERIPH_PRE			18
+#define IMX6QDL_CLK_PERIPH2_PRE			19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
+#define IMX6QDL_CLK_AXI_SEL			22
+#define IMX6QDL_CLK_ESAI_SEL			23
+#define IMX6QDL_CLK_ASRC_SEL			24
+#define IMX6QDL_CLK_SPDIF_SEL			25
+#define IMX6QDL_CLK_GPU2D_AXI			26
+#define IMX6QDL_CLK_GPU3D_AXI			27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL		28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL		29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
+#define IMX6QDL_CLK_IPU1_SEL			31
+#define IMX6QDL_CLK_IPU2_SEL			32
+#define IMX6QDL_CLK_LDB_DI0_SEL			33
+#define IMX6QDL_CLK_LDB_DI1_SEL			34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
+#define IMX6QDL_CLK_IPU1_DI0_SEL		39
+#define IMX6QDL_CLK_IPU1_DI1_SEL		40
+#define IMX6QDL_CLK_IPU2_DI0_SEL		41
+#define IMX6QDL_CLK_IPU2_DI1_SEL		42
+#define IMX6QDL_CLK_HSI_TX_SEL			43
+#define IMX6QDL_CLK_PCIE_AXI_SEL		44
+#define IMX6QDL_CLK_SSI1_SEL			45
+#define IMX6QDL_CLK_SSI2_SEL			46
+#define IMX6QDL_CLK_SSI3_SEL			47
+#define IMX6QDL_CLK_USDHC1_SEL			48
+#define IMX6QDL_CLK_USDHC2_SEL			49
+#define IMX6QDL_CLK_USDHC3_SEL			50
+#define IMX6QDL_CLK_USDHC4_SEL			51
+#define IMX6QDL_CLK_ENFC_SEL			52
+#define IMX6QDL_CLK_EIM_SEL			53
+#define IMX6QDL_CLK_EIM_SLOW_SEL		54
+#define IMX6QDL_CLK_VDO_AXI_SEL			55
+#define IMX6QDL_CLK_VPU_AXI_SEL			56
+#define IMX6QDL_CLK_CKO1_SEL			57
+#define IMX6QDL_CLK_PERIPH			58
+#define IMX6QDL_CLK_PERIPH2			59
+#define IMX6QDL_CLK_PERIPH_CLK2			60
+#define IMX6QDL_CLK_PERIPH2_CLK2		61
+#define IMX6QDL_CLK_IPG				62
+#define IMX6QDL_CLK_IPG_PER			63
+#define IMX6QDL_CLK_ESAI_PRED			64
+#define IMX6QDL_CLK_ESAI_PODF			65
+#define IMX6QDL_CLK_ASRC_PRED			66
+#define IMX6QDL_CLK_ASRC_PODF			67
+#define IMX6QDL_CLK_SPDIF_PRED			68
+#define IMX6QDL_CLK_SPDIF_PODF			69
+#define IMX6QDL_CLK_CAN_ROOT			70
+#define IMX6QDL_CLK_ECSPI_ROOT			71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF		72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF		73
+#define IMX6QDL_CLK_GPU3D_SHADER		74
+#define IMX6QDL_CLK_IPU1_PODF			75
+#define IMX6QDL_CLK_IPU2_PODF			76
+#define IMX6QDL_CLK_LDB_DI0_PODF		77
+#define IMX6QDL_CLK_LDB_DI1_PODF		78
+#define IMX6QDL_CLK_IPU1_DI0_PRE		79
+#define IMX6QDL_CLK_IPU1_DI1_PRE		80
+#define IMX6QDL_CLK_IPU2_DI0_PRE		81
+#define IMX6QDL_CLK_IPU2_DI1_PRE		82
+#define IMX6QDL_CLK_HSI_TX_PODF			83
+#define IMX6QDL_CLK_SSI1_PRED			84
+#define IMX6QDL_CLK_SSI1_PODF			85
+#define IMX6QDL_CLK_SSI2_PRED			86
+#define IMX6QDL_CLK_SSI2_PODF			87
+#define IMX6QDL_CLK_SSI3_PRED			88
+#define IMX6QDL_CLK_SSI3_PODF			89
+#define IMX6QDL_CLK_UART_SERIAL_PODF		90
+#define IMX6QDL_CLK_USDHC1_PODF			91
+#define IMX6QDL_CLK_USDHC2_PODF			92
+#define IMX6QDL_CLK_USDHC3_PODF			93
+#define IMX6QDL_CLK_USDHC4_PODF			94
+#define IMX6QDL_CLK_ENFC_PRED			95
+#define IMX6QDL_CLK_ENFC_PODF			96
+#define IMX6QDL_CLK_EIM_PODF			97
+#define IMX6QDL_CLK_EIM_SLOW_PODF		98
+#define IMX6QDL_CLK_VPU_AXI_PODF		99
+#define IMX6QDL_CLK_CKO1_PODF			100
+#define IMX6QDL_CLK_AXI				101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
+#define IMX6QDL_CLK_ARM				104
+#define IMX6QDL_CLK_AHB				105
+#define IMX6QDL_CLK_APBH_DMA			106
+#define IMX6QDL_CLK_ASRC			107
+#define IMX6QDL_CLK_CAN1_IPG			108
+#define IMX6QDL_CLK_CAN1_SERIAL			109
+#define IMX6QDL_CLK_CAN2_IPG			110
+#define IMX6QDL_CLK_CAN2_SERIAL			111
+#define IMX6QDL_CLK_ECSPI1			112
+#define IMX6QDL_CLK_ECSPI2			113
+#define IMX6QDL_CLK_ECSPI3			114
+#define IMX6QDL_CLK_ECSPI4			115
+#define IMX6Q_CLK_ECSPI5			116
+#define IMX6DL_CLK_I2C4				116
+#define IMX6QDL_CLK_ENET			117
+#define IMX6QDL_CLK_ESAI_EXTAL			118
+#define IMX6QDL_CLK_GPT_IPG			119
+#define IMX6QDL_CLK_GPT_IPG_PER			120
+#define IMX6QDL_CLK_GPU2D_CORE			121
+#define IMX6QDL_CLK_GPU3D_CORE			122
+#define IMX6QDL_CLK_HDMI_IAHB			123
+#define IMX6QDL_CLK_HDMI_ISFR			124
+#define IMX6QDL_CLK_I2C1			125
+#define IMX6QDL_CLK_I2C2			126
+#define IMX6QDL_CLK_I2C3			127
+#define IMX6QDL_CLK_IIM				128
+#define IMX6QDL_CLK_ENFC			129
+#define IMX6QDL_CLK_IPU1			130
+#define IMX6QDL_CLK_IPU1_DI0			131
+#define IMX6QDL_CLK_IPU1_DI1			132
+#define IMX6QDL_CLK_IPU2			133
+#define IMX6QDL_CLK_IPU2_DI0			134
+#define IMX6QDL_CLK_LDB_DI0			135
+#define IMX6QDL_CLK_LDB_DI1			136
+#define IMX6QDL_CLK_IPU2_DI1			137
+#define IMX6QDL_CLK_HSI_TX			138
+#define IMX6QDL_CLK_MLB				139
+#define IMX6QDL_CLK_MMDC_CH0_AXI		140
+#define IMX6QDL_CLK_MMDC_CH1_AXI		141
+#define IMX6QDL_CLK_OCRAM			142
+#define IMX6QDL_CLK_OPENVG_AXI			143
+#define IMX6QDL_CLK_PCIE_AXI			144
+#define IMX6QDL_CLK_PWM1			145
+#define IMX6QDL_CLK_PWM2			146
+#define IMX6QDL_CLK_PWM3			147
+#define IMX6QDL_CLK_PWM4			148
+#define IMX6QDL_CLK_PER1_BCH			149
+#define IMX6QDL_CLK_GPMI_BCH_APB		150
+#define IMX6QDL_CLK_GPMI_BCH			151
+#define IMX6QDL_CLK_GPMI_IO			152
+#define IMX6QDL_CLK_GPMI_APB			153
+#define IMX6QDL_CLK_SATA			154
+#define IMX6QDL_CLK_SDMA			155
+#define IMX6QDL_CLK_SPBA			156
+#define IMX6QDL_CLK_SSI1			157
+#define IMX6QDL_CLK_SSI2			158
+#define IMX6QDL_CLK_SSI3			159
+#define IMX6QDL_CLK_UART_IPG			160
+#define IMX6QDL_CLK_UART_SERIAL			161
+#define IMX6QDL_CLK_USBOH3			162
+#define IMX6QDL_CLK_USDHC1			163
+#define IMX6QDL_CLK_USDHC2			164
+#define IMX6QDL_CLK_USDHC3			165
+#define IMX6QDL_CLK_USDHC4			166
+#define IMX6QDL_CLK_VDO_AXI			167
+#define IMX6QDL_CLK_VPU_AXI			168
+#define IMX6QDL_CLK_CKO1			169
+#define IMX6QDL_CLK_PLL1_SYS			170
+#define IMX6QDL_CLK_PLL2_BUS			171
+#define IMX6QDL_CLK_PLL3_USB_OTG		172
+#define IMX6QDL_CLK_PLL4_AUDIO			173
+#define IMX6QDL_CLK_PLL5_VIDEO			174
+#define IMX6QDL_CLK_PLL8_MLB			175
+#define IMX6QDL_CLK_PLL7_USB_HOST		176
+#define IMX6QDL_CLK_PLL6_ENET			177
+#define IMX6QDL_CLK_SSI1_IPG			178
+#define IMX6QDL_CLK_SSI2_IPG			179
+#define IMX6QDL_CLK_SSI3_IPG			180
+#define IMX6QDL_CLK_ROM				181
+#define IMX6QDL_CLK_USBPHY1			182
+#define IMX6QDL_CLK_USBPHY2			183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185
+#define IMX6QDL_CLK_SATA_REF			186
+#define IMX6QDL_CLK_SATA_REF_100M		187
+#define IMX6QDL_CLK_PCIE_REF			188
+#define IMX6QDL_CLK_PCIE_REF_125M		189
+#define IMX6QDL_CLK_ENET_REF			190
+#define IMX6QDL_CLK_USBPHY1_GATE		191
+#define IMX6QDL_CLK_USBPHY2_GATE		192
+#define IMX6QDL_CLK_PLL4_POST_DIV		193
+#define IMX6QDL_CLK_PLL5_POST_DIV		194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV		195
+#define IMX6QDL_CLK_EIM_SLOW			196
+#define IMX6QDL_CLK_SPDIF			197
+#define IMX6QDL_CLK_CKO2_SEL			198
+#define IMX6QDL_CLK_CKO2_PODF			199
+#define IMX6QDL_CLK_CKO2			200
+#define IMX6QDL_CLK_CKO				201
+#define IMX6QDL_CLK_VDOA			202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV		203
+#define IMX6QDL_CLK_LVDS1_SEL			204
+#define IMX6QDL_CLK_LVDS2_SEL			205
+#define IMX6QDL_CLK_LVDS1_GATE			206
+#define IMX6QDL_CLK_LVDS2_GATE			207
+#define IMX6QDL_CLK_ESAI_IPG			208
+#define IMX6QDL_CLK_ESAI_MEM			209
+#define IMX6QDL_CLK_ASRC_IPG			210
+#define IMX6QDL_CLK_ASRC_MEM			211
+#define IMX6QDL_CLK_LVDS1_IN			212
+#define IMX6QDL_CLK_LVDS2_IN			213
+#define IMX6QDL_CLK_ANACLK1			214
+#define IMX6QDL_CLK_ANACLK2			215
+#define IMX6QDL_PLL1_BYPASS_SRC			216
+#define IMX6QDL_PLL2_BYPASS_SRC			217
+#define IMX6QDL_PLL3_BYPASS_SRC			218
+#define IMX6QDL_PLL4_BYPASS_SRC			219
+#define IMX6QDL_PLL5_BYPASS_SRC			220
+#define IMX6QDL_PLL6_BYPASS_SRC			221
+#define IMX6QDL_PLL7_BYPASS_SRC			222
+#define IMX6QDL_CLK_PLL1			223
+#define IMX6QDL_CLK_PLL2			224
+#define IMX6QDL_CLK_PLL3			225
+#define IMX6QDL_CLK_PLL4			226
+#define IMX6QDL_CLK_PLL5			227
+#define IMX6QDL_CLK_PLL6			228
+#define IMX6QDL_CLK_PLL7			229
+#define IMX6QDL_PLL1_BYPASS			230
+#define IMX6QDL_PLL2_BYPASS			231
+#define IMX6QDL_PLL3_BYPASS			232
+#define IMX6QDL_PLL4_BYPASS			233
+#define IMX6QDL_PLL5_BYPASS			234
+#define IMX6QDL_PLL6_BYPASS			235
+#define IMX6QDL_PLL7_BYPASS			236
+#define IMX6QDL_CLK_GPT_3M			237
+#define IMX6QDL_CLK_VIDEO_27M			238
+#define IMX6QDL_CLK_MIPI_CORE_CFG		239
+#define IMX6QDL_CLK_MIPI_IPG			240
+#define IMX6QDL_CLK_CAAM_MEM			241
+#define IMX6QDL_CLK_CAAM_ACLK			242
+#define IMX6QDL_CLK_CAAM_IPG			243
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_MLB_SEL			259
+#define IMX6QDL_CLK_MLB_PODF			260
+#define IMX6QDL_CLK_EPIT1			261
+#define IMX6QDL_CLK_EPIT2			262
+#define IMX6QDL_CLK_END				263
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

include/dt-bindings/clock/imx6sl-clock.h

@@ -0,0 +1,180 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY		0
+#define IMX6SL_CLK_CKIL			1
+#define IMX6SL_CLK_OSC			2
+#define IMX6SL_CLK_PLL1_SYS		3
+#define IMX6SL_CLK_PLL2_BUS		4
+#define IMX6SL_CLK_PLL3_USB_OTG		5
+#define IMX6SL_CLK_PLL4_AUDIO		6
+#define IMX6SL_CLK_PLL5_VIDEO		7
+#define IMX6SL_CLK_PLL6_ENET		8
+#define IMX6SL_CLK_PLL7_USB_HOST	9
+#define IMX6SL_CLK_USBPHY1		10
+#define IMX6SL_CLK_USBPHY2		11
+#define IMX6SL_CLK_USBPHY1_GATE		12
+#define IMX6SL_CLK_USBPHY2_GATE		13
+#define IMX6SL_CLK_PLL4_POST_DIV	14
+#define IMX6SL_CLK_PLL5_POST_DIV	15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV	16
+#define IMX6SL_CLK_ENET_REF		17
+#define IMX6SL_CLK_PLL2_PFD0		18
+#define IMX6SL_CLK_PLL2_PFD1		19
+#define IMX6SL_CLK_PLL2_PFD2		20
+#define IMX6SL_CLK_PLL3_PFD0		21
+#define IMX6SL_CLK_PLL3_PFD1		22
+#define IMX6SL_CLK_PLL3_PFD2		23
+#define IMX6SL_CLK_PLL3_PFD3		24
+#define IMX6SL_CLK_PLL2_198M		25
+#define IMX6SL_CLK_PLL3_120M		26
+#define IMX6SL_CLK_PLL3_80M		27
+#define IMX6SL_CLK_PLL3_60M		28
+#define IMX6SL_CLK_STEP			29
+#define IMX6SL_CLK_PLL1_SW		30
+#define IMX6SL_CLK_OCRAM_ALT_SEL	31
+#define IMX6SL_CLK_OCRAM_SEL		32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL	33
+#define IMX6SL_CLK_PRE_PERIPH_SEL	34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL	35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL	36
+#define IMX6SL_CLK_CSI_SEL		37
+#define IMX6SL_CLK_LCDIF_AXI_SEL	38
+#define IMX6SL_CLK_USDHC1_SEL		39
+#define IMX6SL_CLK_USDHC2_SEL		40
+#define IMX6SL_CLK_USDHC3_SEL		41
+#define IMX6SL_CLK_USDHC4_SEL		42
+#define IMX6SL_CLK_SSI1_SEL		43
+#define IMX6SL_CLK_SSI2_SEL		44
+#define IMX6SL_CLK_SSI3_SEL		45
+#define IMX6SL_CLK_PERCLK_SEL		46
+#define IMX6SL_CLK_PXP_AXI_SEL		47
+#define IMX6SL_CLK_EPDC_AXI_SEL		48
+#define IMX6SL_CLK_GPU2D_OVG_SEL	49
+#define IMX6SL_CLK_GPU2D_SEL		50
+#define IMX6SL_CLK_LCDIF_PIX_SEL	51
+#define IMX6SL_CLK_EPDC_PIX_SEL		52
+#define IMX6SL_CLK_SPDIF0_SEL		53
+#define IMX6SL_CLK_SPDIF1_SEL		54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL	55
+#define IMX6SL_CLK_ECSPI_SEL		56
+#define IMX6SL_CLK_UART_SEL		57
+#define IMX6SL_CLK_PERIPH		58
+#define IMX6SL_CLK_PERIPH2		59
+#define IMX6SL_CLK_OCRAM_PODF		60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF	61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF	62
+#define IMX6SL_CLK_IPG			63
+#define IMX6SL_CLK_CSI_PODF		64
+#define IMX6SL_CLK_LCDIF_AXI_PODF	65
+#define IMX6SL_CLK_USDHC1_PODF		66
+#define IMX6SL_CLK_USDHC2_PODF		67
+#define IMX6SL_CLK_USDHC3_PODF		68
+#define IMX6SL_CLK_USDHC4_PODF		69
+#define IMX6SL_CLK_SSI1_PRED		70
+#define IMX6SL_CLK_SSI1_PODF		71
+#define IMX6SL_CLK_SSI2_PRED		72
+#define IMX6SL_CLK_SSI2_PODF		73
+#define IMX6SL_CLK_SSI3_PRED		74
+#define IMX6SL_CLK_SSI3_PODF		75
+#define IMX6SL_CLK_PERCLK		76
+#define IMX6SL_CLK_PXP_AXI_PODF		77
+#define IMX6SL_CLK_EPDC_AXI_PODF	78
+#define IMX6SL_CLK_GPU2D_OVG_PODF	79
+#define IMX6SL_CLK_GPU2D_PODF		80
+#define IMX6SL_CLK_LCDIF_PIX_PRED	81
+#define IMX6SL_CLK_EPDC_PIX_PRED	82
+#define IMX6SL_CLK_LCDIF_PIX_PODF	83
+#define IMX6SL_CLK_EPDC_PIX_PODF	84
+#define IMX6SL_CLK_SPDIF0_PRED		85
+#define IMX6SL_CLK_SPDIF0_PODF		86
+#define IMX6SL_CLK_SPDIF1_PRED		87
+#define IMX6SL_CLK_SPDIF1_PODF		88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED	89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF	90
+#define IMX6SL_CLK_ECSPI_ROOT		91
+#define IMX6SL_CLK_UART_ROOT		92
+#define IMX6SL_CLK_AHB			93
+#define IMX6SL_CLK_MMDC_ROOT		94
+#define IMX6SL_CLK_ARM			95
+#define IMX6SL_CLK_ECSPI1		96
+#define IMX6SL_CLK_ECSPI2		97
+#define IMX6SL_CLK_ECSPI3		98
+#define IMX6SL_CLK_ECSPI4		99
+#define IMX6SL_CLK_EPIT1		100
+#define IMX6SL_CLK_EPIT2		101
+#define IMX6SL_CLK_EXTERN_AUDIO		102
+#define IMX6SL_CLK_GPT			103
+#define IMX6SL_CLK_GPT_SERIAL		104
+#define IMX6SL_CLK_GPU2D_OVG		105
+#define IMX6SL_CLK_I2C1			106
+#define IMX6SL_CLK_I2C2			107
+#define IMX6SL_CLK_I2C3			108
+#define IMX6SL_CLK_OCOTP		109
+#define IMX6SL_CLK_CSI			110
+#define IMX6SL_CLK_PXP_AXI		111
+#define IMX6SL_CLK_EPDC_AXI		112
+#define IMX6SL_CLK_LCDIF_AXI		113
+#define IMX6SL_CLK_LCDIF_PIX		114
+#define IMX6SL_CLK_EPDC_PIX		115
+#define IMX6SL_CLK_OCRAM		116
+#define IMX6SL_CLK_PWM1			117
+#define IMX6SL_CLK_PWM2			118
+#define IMX6SL_CLK_PWM3			119
+#define IMX6SL_CLK_PWM4			120
+#define IMX6SL_CLK_SDMA			121
+#define IMX6SL_CLK_SPDIF		122
+#define IMX6SL_CLK_SSI1			123
+#define IMX6SL_CLK_SSI2			124
+#define IMX6SL_CLK_SSI3			125
+#define IMX6SL_CLK_UART			126
+#define IMX6SL_CLK_UART_SERIAL		127
+#define IMX6SL_CLK_USBOH3		128
+#define IMX6SL_CLK_USDHC1		129
+#define IMX6SL_CLK_USDHC2		130
+#define IMX6SL_CLK_USDHC3		131
+#define IMX6SL_CLK_USDHC4		132
+#define IMX6SL_CLK_PLL4_AUDIO_DIV	133
+#define IMX6SL_CLK_SPBA			134
+#define IMX6SL_CLK_ENET			135
+#define IMX6SL_CLK_LVDS1_SEL		136
+#define IMX6SL_CLK_LVDS1_OUT		137
+#define IMX6SL_CLK_LVDS1_IN		138
+#define IMX6SL_CLK_ANACLK1		139
+#define IMX6SL_PLL1_BYPASS_SRC		140
+#define IMX6SL_PLL2_BYPASS_SRC		141
+#define IMX6SL_PLL3_BYPASS_SRC		142
+#define IMX6SL_PLL4_BYPASS_SRC		143
+#define IMX6SL_PLL5_BYPASS_SRC		144
+#define IMX6SL_PLL6_BYPASS_SRC		145
+#define IMX6SL_PLL7_BYPASS_SRC		146
+#define IMX6SL_CLK_PLL1			147
+#define IMX6SL_CLK_PLL2			148
+#define IMX6SL_CLK_PLL3			149
+#define IMX6SL_CLK_PLL4			150
+#define IMX6SL_CLK_PLL5			151
+#define IMX6SL_CLK_PLL6			152
+#define IMX6SL_CLK_PLL7			153
+#define IMX6SL_PLL1_BYPASS		154
+#define IMX6SL_PLL2_BYPASS		155
+#define IMX6SL_PLL3_BYPASS		156
+#define IMX6SL_PLL4_BYPASS		157
+#define IMX6SL_PLL5_BYPASS		158
+#define IMX6SL_PLL6_BYPASS		159
+#define IMX6SL_PLL7_BYPASS		160
+#define IMX6SL_CLK_SSI1_IPG		161
+#define IMX6SL_CLK_SSI2_IPG		162
+#define IMX6SL_CLK_SSI3_IPG		163
+#define IMX6SL_CLK_SPDIF_GCLK		164
+#define IMX6SL_CLK_END			165
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

include/dt-bindings/clock/imx6sll-clock.h

@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY		0
+#define IMX6SLL_CLK_CKIL		1
+#define IMX6SLL_CLK_OSC			2
+#define IMX6SLL_PLL1_BYPASS_SRC		3
+#define IMX6SLL_PLL2_BYPASS_SRC		4
+#define IMX6SLL_PLL3_BYPASS_SRC		5
+#define IMX6SLL_PLL4_BYPASS_SRC		6
+#define IMX6SLL_PLL5_BYPASS_SRC		7
+#define IMX6SLL_PLL6_BYPASS_SRC		8
+#define IMX6SLL_PLL7_BYPASS_SRC		9
+#define IMX6SLL_CLK_PLL1		10
+#define IMX6SLL_CLK_PLL2		11
+#define IMX6SLL_CLK_PLL3		12
+#define IMX6SLL_CLK_PLL4		13
+#define IMX6SLL_CLK_PLL5		14
+#define IMX6SLL_CLK_PLL6		15
+#define IMX6SLL_CLK_PLL7		16
+#define IMX6SLL_PLL1_BYPASS		17
+#define IMX6SLL_PLL2_BYPASS		18
+#define IMX6SLL_PLL3_BYPASS		19
+#define IMX6SLL_PLL4_BYPASS		20
+#define IMX6SLL_PLL5_BYPASS		21
+#define IMX6SLL_PLL6_BYPASS		22
+#define IMX6SLL_PLL7_BYPASS		23
+#define IMX6SLL_CLK_PLL1_SYS		24
+#define IMX6SLL_CLK_PLL2_BUS		25
+#define IMX6SLL_CLK_PLL3_USB_OTG	26
+#define IMX6SLL_CLK_PLL4_AUDIO		27
+#define IMX6SLL_CLK_PLL5_VIDEO		28
+#define IMX6SLL_CLK_PLL6_ENET		29
+#define IMX6SLL_CLK_PLL7_USB_HOST	30
+#define IMX6SLL_CLK_USBPHY1		31
+#define IMX6SLL_CLK_USBPHY2		32
+#define IMX6SLL_CLK_USBPHY1_GATE	33
+#define IMX6SLL_CLK_USBPHY2_GATE	34
+#define IMX6SLL_CLK_PLL2_PFD0		35
+#define IMX6SLL_CLK_PLL2_PFD1		36
+#define IMX6SLL_CLK_PLL2_PFD2		37
+#define IMX6SLL_CLK_PLL2_PFD3		38
+#define IMX6SLL_CLK_PLL3_PFD0		39
+#define IMX6SLL_CLK_PLL3_PFD1		40
+#define IMX6SLL_CLK_PLL3_PFD2		41
+#define IMX6SLL_CLK_PLL3_PFD3		42
+#define IMX6SLL_CLK_PLL4_POST_DIV	43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV	44
+#define IMX6SLL_CLK_PLL5_POST_DIV	45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV	46
+#define IMX6SLL_CLK_PLL2_198M		47
+#define IMX6SLL_CLK_PLL3_120M		48
+#define IMX6SLL_CLK_PLL3_80M		49
+#define IMX6SLL_CLK_PLL3_60M		50
+#define IMX6SLL_CLK_STEP		51
+#define IMX6SLL_CLK_PLL1_SW		52
+#define IMX6SLL_CLK_AXI_ALT_SEL		53
+#define IMX6SLL_CLK_AXI_SEL		54
+#define IMX6SLL_CLK_PERIPH_PRE		55
+#define IMX6SLL_CLK_PERIPH2_PRE		56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL	57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL	58
+#define IMX6SLL_CLK_PERCLK_SEL		59
+#define IMX6SLL_CLK_USDHC1_SEL		60
+#define IMX6SLL_CLK_USDHC2_SEL		61
+#define IMX6SLL_CLK_USDHC3_SEL		62
+#define IMX6SLL_CLK_SSI1_SEL		63
+#define IMX6SLL_CLK_SSI2_SEL		64
+#define IMX6SLL_CLK_SSI3_SEL		65
+#define IMX6SLL_CLK_PXP_SEL		66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL	67
+#define IMX6SLL_CLK_LCDIF_SEL		68
+#define IMX6SLL_CLK_EPDC_PRE_SEL	69
+#define IMX6SLL_CLK_SPDIF_SEL		70
+#define IMX6SLL_CLK_ECSPI_SEL		71
+#define IMX6SLL_CLK_UART_SEL		72
+#define IMX6SLL_CLK_ARM			73
+#define IMX6SLL_CLK_PERIPH		74
+#define IMX6SLL_CLK_PERIPH2		75
+#define IMX6SLL_CLK_PERIPH2_CLK2	76
+#define IMX6SLL_CLK_PERIPH_CLK2		77
+#define IMX6SLL_CLK_MMDC_PODF		78
+#define IMX6SLL_CLK_AXI_PODF		79
+#define IMX6SLL_CLK_AHB			80
+#define IMX6SLL_CLK_IPG			81
+#define IMX6SLL_CLK_PERCLK		82
+#define IMX6SLL_CLK_USDHC1_PODF		83
+#define IMX6SLL_CLK_USDHC2_PODF		84
+#define IMX6SLL_CLK_USDHC3_PODF		85
+#define IMX6SLL_CLK_SSI1_PRED		86
+#define IMX6SLL_CLK_SSI2_PRED		87
+#define IMX6SLL_CLK_SSI3_PRED		88
+#define IMX6SLL_CLK_SSI1_PODF		89
+#define IMX6SLL_CLK_SSI2_PODF		90
+#define IMX6SLL_CLK_SSI3_PODF		91
+#define IMX6SLL_CLK_PXP_PODF		92
+#define IMX6SLL_CLK_LCDIF_PRED		93
+#define IMX6SLL_CLK_LCDIF_PODF		94
+#define IMX6SLL_CLK_EPDC_SEL		95
+#define IMX6SLL_CLK_EPDC_PODF		96
+#define IMX6SLL_CLK_SPDIF_PRED		97
+#define IMX6SLL_CLK_SPDIF_PODF		98
+#define IMX6SLL_CLK_ECSPI_PODF		99
+#define IMX6SLL_CLK_UART_PODF		100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1		101
+#define IMX6SLL_CLK_AIPSTZ2		102
+#define IMX6SLL_CLK_DCP			103
+#define IMX6SLL_CLK_UART2_IPG		104
+#define IMX6SLL_CLK_UART2_SERIAL	105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1		106
+#define IMX6SLL_CLK_ECSPI2		107
+#define IMX6SLL_CLK_ECSPI3		108
+#define IMX6SLL_CLK_ECSPI4		109
+#define IMX6SLL_CLK_UART3_IPG		110
+#define IMX6SLL_CLK_UART3_SERIAL	111
+#define IMX6SLL_CLK_UART4_IPG		112
+#define IMX6SLL_CLK_UART4_SERIAL	113
+#define IMX6SLL_CLK_EPIT1		114
+#define IMX6SLL_CLK_EPIT2		115
+#define IMX6SLL_CLK_GPT_BUS		116
+#define IMX6SLL_CLK_GPT_SERIAL		117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI			118
+#define IMX6SLL_CLK_I2C1		119
+#define IMX6SLL_CLK_I2C2		120
+#define IMX6SLL_CLK_I2C3		121
+#define IMX6SLL_CLK_OCOTP		122
+#define IMX6SLL_CLK_LCDIF_APB		123
+#define IMX6SLL_CLK_PXP			124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG		125
+#define IMX6SLL_CLK_UART5_SERIAL	126
+#define IMX6SLL_CLK_EPDC_AXI		127
+#define IMX6SLL_CLK_EPDC_PIX		128
+#define IMX6SLL_CLK_LCDIF_PIX		129
+#define IMX6SLL_CLK_WDOG1		130
+#define IMX6SLL_CLK_MMDC_P0_FAST	131
+#define IMX6SLL_CLK_MMDC_P0_IPG		132
+#define IMX6SLL_CLK_OCRAM		133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1		134
+#define IMX6SLL_CLK_PWM2		135
+#define IMX6SLL_CLK_PWM3		136
+#define IMX6SLL_CLK_PWM4		137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM			138
+#define IMX6SLL_CLK_SDMA		139
+#define IMX6SLL_CLK_KPP			140
+#define IMX6SLL_CLK_WDOG2		141
+#define IMX6SLL_CLK_SPBA		142
+#define IMX6SLL_CLK_SPDIF		143
+#define IMX6SLL_CLK_SPDIF_GCLK		144
+#define IMX6SLL_CLK_SSI1		145
+#define IMX6SLL_CLK_SSI1_IPG		146
+#define IMX6SLL_CLK_SSI2		147
+#define IMX6SLL_CLK_SSI2_IPG		148
+#define IMX6SLL_CLK_SSI3		149
+#define IMX6SLL_CLK_SSI3_IPG		150
+#define IMX6SLL_CLK_UART1_IPG		151
+#define IMX6SLL_CLK_UART1_SERIAL	152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3		153
+#define IMX6SLL_CLK_USDHC1		154
+#define IMX6SLL_CLK_USDHC2		155
+#define IMX6SLL_CLK_USDHC3		156
+
+#define IMX6SLL_CLK_IPP_DI0		157
+#define IMX6SLL_CLK_IPP_DI1		158
+#define IMX6SLL_CLK_LDB_DI0_SEL		159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5	160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7	161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL	162
+#define IMX6SLL_CLK_LDB_DI0		163
+#define IMX6SLL_CLK_LDB_DI1_SEL		164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5	165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7	166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL	167
+#define IMX6SLL_CLK_LDB_DI1		168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL    169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED   170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
+#define IMX6SLL_CLK_EXTERN_AUDIO        172
+
+#define IMX6SLL_CLK_GPIO1               173
+#define IMX6SLL_CLK_GPIO2               174
+#define IMX6SLL_CLK_GPIO3               175
+#define IMX6SLL_CLK_GPIO4               176
+#define IMX6SLL_CLK_GPIO5               177
+#define IMX6SLL_CLK_GPIO6               178
+
+#define IMX6SLL_CLK_END			179
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */

include/dt-bindings/clock/imx6sx-clock.h

@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
+#define __DT_BINDINGS_CLOCK_IMX6SX_H
+
+#define IMX6SX_CLK_DUMMY		0
+#define IMX6SX_CLK_CKIL			1
+#define IMX6SX_CLK_CKIH			2
+#define IMX6SX_CLK_OSC			3
+#define IMX6SX_CLK_PLL1_SYS		4
+#define IMX6SX_CLK_PLL2_BUS		5
+#define IMX6SX_CLK_PLL3_USB_OTG		6
+#define IMX6SX_CLK_PLL4_AUDIO		7
+#define IMX6SX_CLK_PLL5_VIDEO		8
+#define IMX6SX_CLK_PLL6_ENET		9
+#define IMX6SX_CLK_PLL7_USB_HOST	10
+#define IMX6SX_CLK_USBPHY1		11
+#define IMX6SX_CLK_USBPHY2		12
+#define IMX6SX_CLK_USBPHY1_GATE		13
+#define IMX6SX_CLK_USBPHY2_GATE		14
+#define IMX6SX_CLK_PCIE_REF		15
+#define IMX6SX_CLK_PCIE_REF_125M	16
+#define IMX6SX_CLK_ENET_REF		17
+#define IMX6SX_CLK_PLL2_PFD0		18
+#define IMX6SX_CLK_PLL2_PFD1		19
+#define IMX6SX_CLK_PLL2_PFD2		20
+#define IMX6SX_CLK_PLL2_PFD3		21
+#define IMX6SX_CLK_PLL3_PFD0		22
+#define IMX6SX_CLK_PLL3_PFD1		23
+#define IMX6SX_CLK_PLL3_PFD2		24
+#define IMX6SX_CLK_PLL3_PFD3		25
+#define IMX6SX_CLK_PLL2_198M		26
+#define IMX6SX_CLK_PLL3_120M		27
+#define IMX6SX_CLK_PLL3_80M		28
+#define IMX6SX_CLK_PLL3_60M		29
+#define IMX6SX_CLK_TWD			30
+#define IMX6SX_CLK_PLL4_POST_DIV	31
+#define IMX6SX_CLK_PLL4_AUDIO_DIV	32
+#define IMX6SX_CLK_PLL5_POST_DIV	33
+#define IMX6SX_CLK_PLL5_VIDEO_DIV	34
+#define IMX6SX_CLK_STEP			35
+#define IMX6SX_CLK_PLL1_SW		36
+#define IMX6SX_CLK_OCRAM_SEL		37
+#define IMX6SX_CLK_PERIPH_PRE		38
+#define IMX6SX_CLK_PERIPH2_PRE		39
+#define IMX6SX_CLK_PERIPH_CLK2_SEL	40
+#define IMX6SX_CLK_PERIPH2_CLK2_SEL	41
+#define IMX6SX_CLK_PCIE_AXI_SEL		42
+#define IMX6SX_CLK_GPU_AXI_SEL		43
+#define IMX6SX_CLK_GPU_CORE_SEL		44
+#define IMX6SX_CLK_EIM_SLOW_SEL		45
+#define IMX6SX_CLK_USDHC1_SEL		46
+#define IMX6SX_CLK_USDHC2_SEL		47
+#define IMX6SX_CLK_USDHC3_SEL		48
+#define IMX6SX_CLK_USDHC4_SEL		49
+#define IMX6SX_CLK_SSI1_SEL		50
+#define IMX6SX_CLK_SSI2_SEL		51
+#define IMX6SX_CLK_SSI3_SEL		52
+#define IMX6SX_CLK_QSPI1_SEL		53
+#define IMX6SX_CLK_PERCLK_SEL		54
+#define IMX6SX_CLK_VID_SEL		55
+#define IMX6SX_CLK_ESAI_SEL		56
+#define IMX6SX_CLK_LDB_DI0_DIV_SEL	57
+#define IMX6SX_CLK_LDB_DI1_DIV_SEL	58
+#define IMX6SX_CLK_CAN_SEL		59
+#define IMX6SX_CLK_UART_SEL		60
+#define IMX6SX_CLK_QSPI2_SEL		61
+#define IMX6SX_CLK_LDB_DI1_SEL		62
+#define IMX6SX_CLK_LDB_DI0_SEL		63
+#define IMX6SX_CLK_SPDIF_SEL		64
+#define IMX6SX_CLK_AUDIO_SEL		65
+#define IMX6SX_CLK_ENET_PRE_SEL		66
+#define IMX6SX_CLK_ENET_SEL		67
+#define IMX6SX_CLK_M4_PRE_SEL		68
+#define IMX6SX_CLK_M4_SEL		69
+#define IMX6SX_CLK_ECSPI_SEL		70
+#define IMX6SX_CLK_LCDIF1_PRE_SEL	71
+#define IMX6SX_CLK_LCDIF2_PRE_SEL	72
+#define IMX6SX_CLK_LCDIF1_SEL		73
+#define IMX6SX_CLK_LCDIF2_SEL		74
+#define IMX6SX_CLK_DISPLAY_SEL		75
+#define IMX6SX_CLK_CSI_SEL		76
+#define IMX6SX_CLK_CKO1_SEL		77
+#define IMX6SX_CLK_CKO2_SEL		78
+#define IMX6SX_CLK_CKO			79
+#define IMX6SX_CLK_PERIPH_CLK2		80
+#define IMX6SX_CLK_PERIPH2_CLK2		81
+#define IMX6SX_CLK_IPG			82
+#define IMX6SX_CLK_GPU_CORE_PODF	83
+#define IMX6SX_CLK_GPU_AXI_PODF		84
+#define IMX6SX_CLK_LCDIF1_PODF		85
+#define IMX6SX_CLK_QSPI1_PODF		86
+#define IMX6SX_CLK_EIM_SLOW_PODF	87
+#define IMX6SX_CLK_LCDIF2_PODF		88
+#define IMX6SX_CLK_PERCLK		89
+#define IMX6SX_CLK_VID_PODF		90
+#define IMX6SX_CLK_CAN_PODF		91
+#define IMX6SX_CLK_USDHC1_PODF		92
+#define IMX6SX_CLK_USDHC2_PODF		93
+#define IMX6SX_CLK_USDHC3_PODF		94
+#define IMX6SX_CLK_USDHC4_PODF		95
+#define IMX6SX_CLK_UART_PODF		96
+#define IMX6SX_CLK_ESAI_PRED		97
+#define IMX6SX_CLK_ESAI_PODF		98
+#define IMX6SX_CLK_SSI3_PRED		99
+#define IMX6SX_CLK_SSI3_PODF		100
+#define IMX6SX_CLK_SSI1_PRED		101
+#define IMX6SX_CLK_SSI1_PODF		102
+#define IMX6SX_CLK_QSPI2_PRED		103
+#define IMX6SX_CLK_QSPI2_PODF		104
+#define IMX6SX_CLK_SSI2_PRED		105
+#define IMX6SX_CLK_SSI2_PODF		106
+#define IMX6SX_CLK_SPDIF_PRED		107
+#define IMX6SX_CLK_SPDIF_PODF		108
+#define IMX6SX_CLK_AUDIO_PRED		109
+#define IMX6SX_CLK_AUDIO_PODF		110
+#define IMX6SX_CLK_ENET_PODF		111
+#define IMX6SX_CLK_M4_PODF		112
+#define IMX6SX_CLK_ECSPI_PODF		113
+#define IMX6SX_CLK_LCDIF1_PRED		114
+#define IMX6SX_CLK_LCDIF2_PRED		115
+#define IMX6SX_CLK_DISPLAY_PODF		116
+#define IMX6SX_CLK_CSI_PODF		117
+#define IMX6SX_CLK_LDB_DI0_DIV_3_5	118
+#define IMX6SX_CLK_LDB_DI0_DIV_7	119
+#define IMX6SX_CLK_LDB_DI1_DIV_3_5	120
+#define IMX6SX_CLK_LDB_DI1_DIV_7	121
+#define IMX6SX_CLK_CKO1_PODF		122
+#define IMX6SX_CLK_CKO2_PODF		123
+#define IMX6SX_CLK_PERIPH		124
+#define IMX6SX_CLK_PERIPH2		125
+#define IMX6SX_CLK_OCRAM		126
+#define IMX6SX_CLK_AHB			127
+#define IMX6SX_CLK_MMDC_PODF		128
+#define IMX6SX_CLK_ARM			129
+#define IMX6SX_CLK_AIPS_TZ1		130
+#define IMX6SX_CLK_AIPS_TZ2		131
+#define IMX6SX_CLK_APBH_DMA		132
+#define IMX6SX_CLK_ASRC_GATE		133
+#define IMX6SX_CLK_CAAM_MEM		134
+#define IMX6SX_CLK_CAAM_ACLK		135
+#define IMX6SX_CLK_CAAM_IPG		136
+#define IMX6SX_CLK_CAN1_IPG		137
+#define IMX6SX_CLK_CAN1_SERIAL		138
+#define IMX6SX_CLK_CAN2_IPG		139
+#define IMX6SX_CLK_CAN2_SERIAL		140
+#define IMX6SX_CLK_CPU_DEBUG		141
+#define IMX6SX_CLK_DCIC1		142
+#define IMX6SX_CLK_DCIC2		143
+#define IMX6SX_CLK_AIPS_TZ3		144
+#define IMX6SX_CLK_ECSPI1		145
+#define IMX6SX_CLK_ECSPI2		146
+#define IMX6SX_CLK_ECSPI3		147
+#define IMX6SX_CLK_ECSPI4		148
+#define IMX6SX_CLK_ECSPI5		149
+#define IMX6SX_CLK_EPIT1		150
+#define IMX6SX_CLK_EPIT2		151
+#define IMX6SX_CLK_ESAI_EXTAL		152
+#define IMX6SX_CLK_WAKEUP		153
+#define IMX6SX_CLK_GPT_BUS		154
+#define IMX6SX_CLK_GPT_SERIAL		155
+#define IMX6SX_CLK_GPU			156
+#define IMX6SX_CLK_OCRAM_S		157
+#define IMX6SX_CLK_CANFD		158
+#define IMX6SX_CLK_CSI			159
+#define IMX6SX_CLK_I2C1			160
+#define IMX6SX_CLK_I2C2			161
+#define IMX6SX_CLK_I2C3			162
+#define IMX6SX_CLK_OCOTP		163
+#define IMX6SX_CLK_IOMUXC		164
+#define IMX6SX_CLK_IPMUX1		165
+#define IMX6SX_CLK_IPMUX2		166
+#define IMX6SX_CLK_IPMUX3		167
+#define IMX6SX_CLK_TZASC1		168
+#define IMX6SX_CLK_LCDIF_APB		169
+#define IMX6SX_CLK_PXP_AXI		170
+#define IMX6SX_CLK_M4			171
+#define IMX6SX_CLK_ENET			172
+#define IMX6SX_CLK_DISPLAY_AXI		173
+#define IMX6SX_CLK_LCDIF2_PIX		174
+#define IMX6SX_CLK_LCDIF1_PIX		175
+#define IMX6SX_CLK_LDB_DI0		176
+#define IMX6SX_CLK_QSPI1		177
+#define IMX6SX_CLK_MLB			178
+#define IMX6SX_CLK_MMDC_P0_FAST		179
+#define IMX6SX_CLK_MMDC_P0_IPG		180
+#define IMX6SX_CLK_AXI			181
+#define IMX6SX_CLK_PCIE_AXI		182
+#define IMX6SX_CLK_QSPI2		183
+#define IMX6SX_CLK_PER1_BCH		184
+#define IMX6SX_CLK_PER2_MAIN		185
+#define IMX6SX_CLK_PWM1			186
+#define IMX6SX_CLK_PWM2			187
+#define IMX6SX_CLK_PWM3			188
+#define IMX6SX_CLK_PWM4			189
+#define IMX6SX_CLK_GPMI_BCH_APB		190
+#define IMX6SX_CLK_GPMI_BCH		191
+#define IMX6SX_CLK_GPMI_IO		192
+#define IMX6SX_CLK_GPMI_APB		193
+#define IMX6SX_CLK_ROM			194
+#define IMX6SX_CLK_SDMA			195
+#define IMX6SX_CLK_SPBA			196
+#define IMX6SX_CLK_SPDIF		197
+#define IMX6SX_CLK_SSI1_IPG		198
+#define IMX6SX_CLK_SSI2_IPG		199
+#define IMX6SX_CLK_SSI3_IPG		200
+#define IMX6SX_CLK_SSI1			201
+#define IMX6SX_CLK_SSI2			202
+#define IMX6SX_CLK_SSI3			203
+#define IMX6SX_CLK_UART_IPG		204
+#define IMX6SX_CLK_UART_SERIAL		205
+#define IMX6SX_CLK_SAI1			206
+#define IMX6SX_CLK_SAI2			207
+#define IMX6SX_CLK_USBOH3		208
+#define IMX6SX_CLK_USDHC1		209
+#define IMX6SX_CLK_USDHC2		210
+#define IMX6SX_CLK_USDHC3		211
+#define IMX6SX_CLK_USDHC4		212
+#define IMX6SX_CLK_EIM_SLOW		213
+#define IMX6SX_CLK_PWM8			214
+#define IMX6SX_CLK_VADC			215
+#define IMX6SX_CLK_GIS			216
+#define IMX6SX_CLK_I2C4			217
+#define IMX6SX_CLK_PWM5			218
+#define IMX6SX_CLK_PWM6			219
+#define IMX6SX_CLK_PWM7			220
+#define IMX6SX_CLK_CKO1			221
+#define IMX6SX_CLK_CKO2			222
+#define IMX6SX_CLK_IPP_DI0		223
+#define IMX6SX_CLK_IPP_DI1		224
+#define IMX6SX_CLK_ENET_AHB		225
+#define IMX6SX_CLK_OCRAM_PODF		226
+#define IMX6SX_CLK_GPT_3M		227
+#define IMX6SX_CLK_ENET_PTP		228
+#define IMX6SX_CLK_ENET_PTP_REF		229
+#define IMX6SX_CLK_ENET2_REF		230
+#define IMX6SX_CLK_ENET2_REF_125M	231
+#define IMX6SX_CLK_AUDIO		232
+#define IMX6SX_CLK_LVDS1_SEL		233
+#define IMX6SX_CLK_LVDS1_OUT		234
+#define IMX6SX_CLK_ASRC_IPG		235
+#define IMX6SX_CLK_ASRC_MEM		236
+#define IMX6SX_CLK_SAI1_IPG		237
+#define IMX6SX_CLK_SAI2_IPG		238
+#define IMX6SX_CLK_ESAI_IPG		239
+#define IMX6SX_CLK_ESAI_MEM		240
+#define IMX6SX_CLK_LVDS1_IN		241
+#define IMX6SX_CLK_ANACLK1		242
+#define IMX6SX_PLL1_BYPASS_SRC		243
+#define IMX6SX_PLL2_BYPASS_SRC		244
+#define IMX6SX_PLL3_BYPASS_SRC		245
+#define IMX6SX_PLL4_BYPASS_SRC		246
+#define IMX6SX_PLL5_BYPASS_SRC		247
+#define IMX6SX_PLL6_BYPASS_SRC		248
+#define IMX6SX_PLL7_BYPASS_SRC		249
+#define IMX6SX_CLK_PLL1			250
+#define IMX6SX_CLK_PLL2			251
+#define IMX6SX_CLK_PLL3			252
+#define IMX6SX_CLK_PLL4			253
+#define IMX6SX_CLK_PLL5			254
+#define IMX6SX_CLK_PLL6			255
+#define IMX6SX_CLK_PLL7			256
+#define IMX6SX_PLL1_BYPASS		257
+#define IMX6SX_PLL2_BYPASS		258
+#define IMX6SX_PLL3_BYPASS		259
+#define IMX6SX_PLL4_BYPASS		260
+#define IMX6SX_PLL5_BYPASS		261
+#define IMX6SX_PLL6_BYPASS		262
+#define IMX6SX_PLL7_BYPASS		263
+#define IMX6SX_CLK_SPDIF_GCLK		264
+#define IMX6SX_CLK_LVDS2_SEL		265
+#define IMX6SX_CLK_LVDS2_OUT		266
+#define IMX6SX_CLK_LVDS2_IN		267
+#define IMX6SX_CLK_ANACLK2		268
+#define IMX6SX_CLK_CLK_END		269
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

include/dt-bindings/clock/imx6ul-clock.h

@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
+#define __DT_BINDINGS_CLOCK_IMX6UL_H
+
+#define IMX6UL_CLK_DUMMY		0
+#define IMX6UL_CLK_CKIL			1
+#define IMX6UL_CLK_CKIH			2
+#define IMX6UL_CLK_OSC			3
+#define IMX6UL_PLL1_BYPASS_SRC		4
+#define IMX6UL_PLL2_BYPASS_SRC		5
+#define IMX6UL_PLL3_BYPASS_SRC		6
+#define IMX6UL_PLL4_BYPASS_SRC		7
+#define IMX6UL_PLL5_BYPASS_SRC		8
+#define IMX6UL_PLL6_BYPASS_SRC		9
+#define IMX6UL_PLL7_BYPASS_SRC		10
+#define IMX6UL_CLK_PLL1			11
+#define IMX6UL_CLK_PLL2			12
+#define IMX6UL_CLK_PLL3			13
+#define IMX6UL_CLK_PLL4			14
+#define IMX6UL_CLK_PLL5			15
+#define IMX6UL_CLK_PLL6			16
+#define IMX6UL_CLK_PLL7			17
+#define IMX6UL_PLL1_BYPASS		18
+#define IMX6UL_PLL2_BYPASS		19
+#define IMX6UL_PLL3_BYPASS		20
+#define IMX6UL_PLL4_BYPASS		21
+#define IMX6UL_PLL5_BYPASS		22
+#define IMX6UL_PLL6_BYPASS		23
+#define IMX6UL_PLL7_BYPASS		24
+#define IMX6UL_CLK_PLL1_SYS		25
+#define IMX6UL_CLK_PLL2_BUS		26
+#define IMX6UL_CLK_PLL3_USB_OTG		27
+#define IMX6UL_CLK_PLL4_AUDIO		28
+#define IMX6UL_CLK_PLL5_VIDEO		29
+#define IMX6UL_CLK_PLL6_ENET		30
+#define IMX6UL_CLK_PLL7_USB_HOST	31
+#define IMX6UL_CLK_USBPHY1		32
+#define IMX6UL_CLK_USBPHY2		33
+#define IMX6UL_CLK_USBPHY1_GATE		34
+#define IMX6UL_CLK_USBPHY2_GATE		35
+#define IMX6UL_CLK_PLL2_PFD0		36
+#define IMX6UL_CLK_PLL2_PFD1		37
+#define IMX6UL_CLK_PLL2_PFD2		38
+#define IMX6UL_CLK_PLL2_PFD3		39
+#define IMX6UL_CLK_PLL3_PFD0		40
+#define IMX6UL_CLK_PLL3_PFD1		41
+#define IMX6UL_CLK_PLL3_PFD2		42
+#define IMX6UL_CLK_PLL3_PFD3		43
+#define IMX6UL_CLK_ENET_REF		44
+#define IMX6UL_CLK_ENET2_REF		45
+#define IMX6UL_CLK_ENET2_REF_125M	46
+#define IMX6UL_CLK_ENET_PTP_REF		47
+#define IMX6UL_CLK_ENET_PTP		48
+#define IMX6UL_CLK_PLL4_POST_DIV	49
+#define IMX6UL_CLK_PLL4_AUDIO_DIV	50
+#define IMX6UL_CLK_PLL5_POST_DIV	51
+#define IMX6UL_CLK_PLL5_VIDEO_DIV	52
+#define IMX6UL_CLK_PLL2_198M		53
+#define IMX6UL_CLK_PLL3_80M		54
+#define IMX6UL_CLK_PLL3_60M		55
+#define IMX6UL_CLK_STEP			56
+#define IMX6UL_CLK_PLL1_SW		57
+#define IMX6UL_CLK_AXI_ALT_SEL		58
+#define IMX6UL_CLK_AXI_SEL		59
+#define IMX6UL_CLK_PERIPH_PRE		60
+#define IMX6UL_CLK_PERIPH2_PRE		61
+#define IMX6UL_CLK_PERIPH_CLK2_SEL	62
+#define IMX6UL_CLK_PERIPH2_CLK2_SEL	63
+#define IMX6UL_CLK_USDHC1_SEL		64
+#define IMX6UL_CLK_USDHC2_SEL		65
+#define IMX6UL_CLK_BCH_SEL		66
+#define IMX6UL_CLK_GPMI_SEL		67
+#define IMX6UL_CLK_EIM_SLOW_SEL		68
+#define IMX6UL_CLK_SPDIF_SEL		69
+#define IMX6UL_CLK_SAI1_SEL		70
+#define IMX6UL_CLK_SAI2_SEL		71
+#define IMX6UL_CLK_SAI3_SEL		72
+#define IMX6UL_CLK_LCDIF_PRE_SEL	73
+#define IMX6UL_CLK_SIM_PRE_SEL		74
+#define IMX6UL_CLK_LDB_DI0_SEL		75
+#define IMX6UL_CLK_LDB_DI1_SEL		76
+#define IMX6UL_CLK_ENFC_SEL		77
+#define IMX6UL_CLK_CAN_SEL		78
+#define IMX6UL_CLK_ECSPI_SEL		79
+#define IMX6UL_CLK_UART_SEL		80
+#define IMX6UL_CLK_QSPI1_SEL		81
+#define IMX6UL_CLK_PERCLK_SEL		82
+#define IMX6UL_CLK_LCDIF_SEL		83
+#define IMX6UL_CLK_SIM_SEL		84
+#define IMX6UL_CLK_PERIPH		85
+#define IMX6UL_CLK_PERIPH2		86
+#define IMX6UL_CLK_LDB_DI0_DIV_3_5	87
+#define IMX6UL_CLK_LDB_DI0_DIV_7	88
+#define IMX6UL_CLK_LDB_DI1_DIV_3_5	89
+#define IMX6UL_CLK_LDB_DI1_DIV_7	90
+#define IMX6UL_CLK_LDB_DI0_DIV_SEL	91
+#define IMX6UL_CLK_LDB_DI1_DIV_SEL	92
+#define IMX6UL_CLK_ARM			93
+#define IMX6UL_CLK_PERIPH_CLK2		94
+#define IMX6UL_CLK_PERIPH2_CLK2		95
+#define IMX6UL_CLK_AHB			96
+#define IMX6UL_CLK_MMDC_PODF		97
+#define IMX6UL_CLK_AXI_PODF		98
+#define IMX6UL_CLK_PERCLK		99
+#define IMX6UL_CLK_IPG			100
+#define IMX6UL_CLK_USDHC1_PODF		101
+#define IMX6UL_CLK_USDHC2_PODF		102
+#define IMX6UL_CLK_BCH_PODF		103
+#define IMX6UL_CLK_GPMI_PODF		104
+#define IMX6UL_CLK_EIM_SLOW_PODF	105
+#define IMX6UL_CLK_SPDIF_PRED		106
+#define IMX6UL_CLK_SPDIF_PODF		107
+#define IMX6UL_CLK_SAI1_PRED		108
+#define IMX6UL_CLK_SAI1_PODF		109
+#define IMX6UL_CLK_SAI2_PRED		110
+#define IMX6UL_CLK_SAI2_PODF		111
+#define IMX6UL_CLK_SAI3_PRED		112
+#define IMX6UL_CLK_SAI3_PODF		113
+#define IMX6UL_CLK_LCDIF_PRED		114
+#define IMX6UL_CLK_LCDIF_PODF		115
+#define IMX6UL_CLK_SIM_PODF		116
+#define IMX6UL_CLK_QSPI1_PDOF		117
+#define IMX6UL_CLK_ENFC_PRED		118
+#define IMX6UL_CLK_ENFC_PODF		119
+#define IMX6UL_CLK_CAN_PODF		120
+#define IMX6UL_CLK_ECSPI_PODF		121
+#define IMX6UL_CLK_UART_PODF		122
+#define IMX6UL_CLK_ADC1			123
+#define IMX6UL_CLK_ADC2			124
+#define IMX6UL_CLK_AIPSTZ1		125
+#define IMX6UL_CLK_AIPSTZ2		126
+#define IMX6UL_CLK_AIPSTZ3		127
+#define IMX6UL_CLK_APBHDMA		128
+#define IMX6UL_CLK_ASRC_IPG		129
+#define IMX6UL_CLK_ASRC_MEM		130
+#define IMX6UL_CLK_GPMI_BCH_APB		131
+#define IMX6UL_CLK_GPMI_BCH		132
+#define IMX6UL_CLK_GPMI_IO		133
+#define IMX6UL_CLK_GPMI_APB		134
+#define IMX6UL_CLK_CAAM_MEM		135
+#define IMX6UL_CLK_CAAM_ACLK		136
+#define IMX6UL_CLK_CAAM_IPG		137
+#define IMX6UL_CLK_CSI			138
+#define IMX6UL_CLK_ECSPI1		139
+#define IMX6UL_CLK_ECSPI2		140
+#define IMX6UL_CLK_ECSPI3		141
+#define IMX6UL_CLK_ECSPI4		142
+#define IMX6UL_CLK_EIM			143
+#define IMX6UL_CLK_ENET			144
+#define IMX6UL_CLK_ENET_AHB		145
+#define IMX6UL_CLK_EPIT1		146
+#define IMX6UL_CLK_EPIT2		147
+#define IMX6UL_CLK_CAN1_IPG		148
+#define IMX6UL_CLK_CAN1_SERIAL		149
+#define IMX6UL_CLK_CAN2_IPG		150
+#define IMX6UL_CLK_CAN2_SERIAL		151
+#define IMX6UL_CLK_GPT1_BUS		152
+#define IMX6UL_CLK_GPT1_SERIAL		153
+#define IMX6UL_CLK_GPT2_BUS		154
+#define IMX6UL_CLK_GPT2_SERIAL		155
+#define IMX6UL_CLK_I2C1			156
+#define IMX6UL_CLK_I2C2			157
+#define IMX6UL_CLK_I2C3			158
+#define IMX6UL_CLK_I2C4			159
+#define IMX6UL_CLK_IOMUXC		160
+#define IMX6UL_CLK_LCDIF_APB		161
+#define IMX6UL_CLK_LCDIF_PIX		162
+#define IMX6UL_CLK_MMDC_P0_FAST		163
+#define IMX6UL_CLK_MMDC_P0_IPG		164
+#define IMX6UL_CLK_OCOTP		165
+#define IMX6UL_CLK_OCRAM		166
+#define IMX6UL_CLK_PWM1			167
+#define IMX6UL_CLK_PWM2			168
+#define IMX6UL_CLK_PWM3			169
+#define IMX6UL_CLK_PWM4			170
+#define IMX6UL_CLK_PWM5			171
+#define IMX6UL_CLK_PWM6			172
+#define IMX6UL_CLK_PWM7			173
+#define IMX6UL_CLK_PWM8			174
+#define IMX6UL_CLK_PXP			175
+#define IMX6UL_CLK_QSPI			176
+#define IMX6UL_CLK_ROM			177
+#define IMX6UL_CLK_SAI1			178
+#define IMX6UL_CLK_SAI1_IPG		179
+#define IMX6UL_CLK_SAI2			180
+#define IMX6UL_CLK_SAI2_IPG		181
+#define IMX6UL_CLK_SAI3			182
+#define IMX6UL_CLK_SAI3_IPG		183
+#define IMX6UL_CLK_SDMA			184
+#define IMX6UL_CLK_SIM			185
+#define IMX6UL_CLK_SIM_S		186
+#define IMX6UL_CLK_SPBA			187
+#define IMX6UL_CLK_SPDIF		188
+#define IMX6UL_CLK_UART1_IPG		189
+#define IMX6UL_CLK_UART1_SERIAL		190
+#define IMX6UL_CLK_UART2_IPG		191
+#define IMX6UL_CLK_UART2_SERIAL		192
+#define IMX6UL_CLK_UART3_IPG		193
+#define IMX6UL_CLK_UART3_SERIAL		194
+#define IMX6UL_CLK_UART4_IPG		195
+#define IMX6UL_CLK_UART4_SERIAL		196
+#define IMX6UL_CLK_UART5_IPG		197
+#define IMX6UL_CLK_UART5_SERIAL		198
+#define IMX6UL_CLK_UART6_IPG		199
+#define IMX6UL_CLK_UART6_SERIAL		200
+#define IMX6UL_CLK_UART7_IPG		201
+#define IMX6UL_CLK_UART7_SERIAL		202
+#define IMX6UL_CLK_UART8_IPG		203
+#define IMX6UL_CLK_UART8_SERIAL		204
+#define IMX6UL_CLK_USBOH3		205
+#define IMX6UL_CLK_USDHC1		206
+#define IMX6UL_CLK_USDHC2		207
+#define IMX6UL_CLK_WDOG1		208
+#define IMX6UL_CLK_WDOG2		209
+#define IMX6UL_CLK_WDOG3		210
+#define IMX6UL_CLK_LDB_DI0		211
+#define IMX6UL_CLK_AXI			212
+#define IMX6UL_CLK_SPDIF_GCLK		213
+#define IMX6UL_CLK_GPT_3M		214
+#define IMX6UL_CLK_SIM2			215
+#define IMX6UL_CLK_SIM1			216
+#define IMX6UL_CLK_IPP_DI0		217
+#define IMX6UL_CLK_IPP_DI1		218
+#define IMX6UL_CA7_SECONDARY_SEL	219
+#define IMX6UL_CLK_PER_BCH		220
+#define IMX6UL_CLK_CSI_SEL		221
+#define IMX6UL_CLK_CSI_PODF		222
+#define IMX6UL_CLK_PLL3_120M		223
+#define IMX6UL_CLK_KPP			224
+#define IMX6ULL_CLK_ESAI_PRED		225
+#define IMX6ULL_CLK_ESAI_PODF		226
+#define IMX6ULL_CLK_ESAI_EXTAL		227
+#define IMX6ULL_CLK_ESAI_MEM		228
+#define IMX6ULL_CLK_ESAI_IPG		229
+#define IMX6ULL_CLK_DCP_CLK		230
+#define IMX6ULL_CLK_EPDC_PRE_SEL	231
+#define IMX6ULL_CLK_EPDC_SEL		232
+#define IMX6ULL_CLK_EPDC_PODF		233
+#define IMX6ULL_CLK_EPDC_ACLK		234
+#define IMX6ULL_CLK_EPDC_PIX		235
+#define IMX6ULL_CLK_ESAI_SEL		236
+#define IMX6UL_CLK_CKO1_SEL		237
+#define IMX6UL_CLK_CKO1_PODF		238
+#define IMX6UL_CLK_CKO1			239
+#define IMX6UL_CLK_CKO2_SEL		240
+#define IMX6UL_CLK_CKO2_PODF		241
+#define IMX6UL_CLK_CKO2			242
+#define IMX6UL_CLK_CKO			243
+#define IMX6UL_CLK_GPIO1		244
+#define IMX6UL_CLK_GPIO2		245
+#define IMX6UL_CLK_GPIO3		246
+#define IMX6UL_CLK_GPIO4		247
+#define IMX6UL_CLK_GPIO5		248
+
+#define IMX6UL_CLK_END			249
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */

include/dt-bindings/clock/imx7d-clock.h

@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
+#define __DT_BINDINGS_CLOCK_IMX7D_H
+
+#define IMX7D_OSC_24M_CLK		0
+#define IMX7D_PLL_ARM_MAIN		1
+#define IMX7D_PLL_ARM_MAIN_CLK		2
+#define IMX7D_PLL_ARM_MAIN_SRC		3
+#define IMX7D_PLL_ARM_MAIN_BYPASS	4
+#define IMX7D_PLL_SYS_MAIN		5
+#define IMX7D_PLL_SYS_MAIN_CLK		6
+#define IMX7D_PLL_SYS_MAIN_SRC		7
+#define IMX7D_PLL_SYS_MAIN_BYPASS	8
+#define IMX7D_PLL_SYS_MAIN_480M		9
+#define IMX7D_PLL_SYS_MAIN_240M		10
+#define IMX7D_PLL_SYS_MAIN_120M		11
+#define IMX7D_PLL_SYS_MAIN_480M_CLK	12
+#define IMX7D_PLL_SYS_MAIN_240M_CLK	13
+#define IMX7D_PLL_SYS_MAIN_120M_CLK	14
+#define IMX7D_PLL_SYS_PFD0_392M_CLK	15
+#define IMX7D_PLL_SYS_PFD0_196M		16
+#define IMX7D_PLL_SYS_PFD0_196M_CLK	17
+#define IMX7D_PLL_SYS_PFD1_332M_CLK	18
+#define IMX7D_PLL_SYS_PFD1_166M		19
+#define IMX7D_PLL_SYS_PFD1_166M_CLK	20
+#define IMX7D_PLL_SYS_PFD2_270M_CLK	21
+#define IMX7D_PLL_SYS_PFD2_135M		22
+#define IMX7D_PLL_SYS_PFD2_135M_CLK	23
+#define IMX7D_PLL_SYS_PFD3_CLK		24
+#define IMX7D_PLL_SYS_PFD4_CLK		25
+#define IMX7D_PLL_SYS_PFD5_CLK		26
+#define IMX7D_PLL_SYS_PFD6_CLK		27
+#define IMX7D_PLL_SYS_PFD7_CLK		28
+#define IMX7D_PLL_ENET_MAIN		29
+#define IMX7D_PLL_ENET_MAIN_CLK		30
+#define IMX7D_PLL_ENET_MAIN_SRC		31
+#define IMX7D_PLL_ENET_MAIN_BYPASS	32
+#define IMX7D_PLL_ENET_MAIN_500M	33
+#define IMX7D_PLL_ENET_MAIN_250M	34
+#define IMX7D_PLL_ENET_MAIN_125M	35
+#define IMX7D_PLL_ENET_MAIN_100M	36
+#define IMX7D_PLL_ENET_MAIN_50M		37
+#define IMX7D_PLL_ENET_MAIN_40M		38
+#define IMX7D_PLL_ENET_MAIN_25M		39
+#define IMX7D_PLL_ENET_MAIN_500M_CLK	40
+#define IMX7D_PLL_ENET_MAIN_250M_CLK	41
+#define IMX7D_PLL_ENET_MAIN_125M_CLK	42
+#define IMX7D_PLL_ENET_MAIN_100M_CLK	43
+#define IMX7D_PLL_ENET_MAIN_50M_CLK	44
+#define IMX7D_PLL_ENET_MAIN_40M_CLK	45
+#define IMX7D_PLL_ENET_MAIN_25M_CLK	46
+#define IMX7D_PLL_DRAM_MAIN		47
+#define IMX7D_PLL_DRAM_MAIN_CLK		48
+#define IMX7D_PLL_DRAM_MAIN_SRC		49
+#define IMX7D_PLL_DRAM_MAIN_BYPASS	50
+#define IMX7D_PLL_DRAM_MAIN_533M	51
+#define IMX7D_PLL_DRAM_MAIN_533M_CLK	52
+#define IMX7D_PLL_AUDIO_MAIN		53
+#define IMX7D_PLL_AUDIO_MAIN_CLK	54
+#define IMX7D_PLL_AUDIO_MAIN_SRC	55
+#define IMX7D_PLL_AUDIO_MAIN_BYPASS	56
+#define IMX7D_PLL_VIDEO_MAIN_CLK	57
+#define IMX7D_PLL_VIDEO_MAIN		58
+#define IMX7D_PLL_VIDEO_MAIN_SRC	59
+#define IMX7D_PLL_VIDEO_MAIN_BYPASS	60
+#define IMX7D_USB_MAIN_480M_CLK		61
+#define IMX7D_ARM_A7_ROOT_CLK		62
+#define IMX7D_ARM_A7_ROOT_SRC		63
+#define IMX7D_ARM_A7_ROOT_CG		64
+#define IMX7D_ARM_A7_ROOT_DIV		65
+#define IMX7D_ARM_M4_ROOT_CLK		66
+#define IMX7D_ARM_M4_ROOT_SRC		67
+#define IMX7D_ARM_M4_ROOT_CG		68
+#define IMX7D_ARM_M4_ROOT_DIV		69
+#define IMX7D_ARM_M0_ROOT_CLK		70	/* unused */
+#define IMX7D_ARM_M0_ROOT_SRC		71	/* unused */
+#define IMX7D_ARM_M0_ROOT_CG		72	/* unused */
+#define IMX7D_ARM_M0_ROOT_DIV		73	/* unused */
+#define IMX7D_MAIN_AXI_ROOT_CLK		74
+#define IMX7D_MAIN_AXI_ROOT_SRC		75
+#define IMX7D_MAIN_AXI_ROOT_CG		76
+#define IMX7D_MAIN_AXI_ROOT_DIV		77
+#define IMX7D_DISP_AXI_ROOT_CLK		78
+#define IMX7D_DISP_AXI_ROOT_SRC		79
+#define IMX7D_DISP_AXI_ROOT_CG		80
+#define IMX7D_DISP_AXI_ROOT_DIV		81
+#define IMX7D_ENET_AXI_ROOT_CLK		82
+#define IMX7D_ENET_AXI_ROOT_SRC		83
+#define IMX7D_ENET_AXI_ROOT_CG		84
+#define IMX7D_ENET_AXI_ROOT_DIV		85
+#define IMX7D_NAND_USDHC_BUS_ROOT_CLK	86
+#define IMX7D_NAND_USDHC_BUS_ROOT_SRC	87
+#define IMX7D_NAND_USDHC_BUS_ROOT_CG	88
+#define IMX7D_NAND_USDHC_BUS_ROOT_DIV	89
+#define IMX7D_AHB_CHANNEL_ROOT_CLK	90
+#define IMX7D_AHB_CHANNEL_ROOT_SRC	91
+#define IMX7D_AHB_CHANNEL_ROOT_CG	92
+#define IMX7D_AHB_CHANNEL_ROOT_DIV	93
+#define IMX7D_DRAM_PHYM_ROOT_CLK	94
+#define IMX7D_DRAM_PHYM_ROOT_SRC	95
+#define IMX7D_DRAM_PHYM_ROOT_CG		96
+#define IMX7D_DRAM_PHYM_ROOT_DIV	97
+#define IMX7D_DRAM_ROOT_CLK		98
+#define IMX7D_DRAM_ROOT_SRC		99
+#define IMX7D_DRAM_ROOT_CG		100
+#define IMX7D_DRAM_ROOT_DIV		101
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK	102
+#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC	103
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CG	104
+#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV	105
+#define IMX7D_DRAM_ALT_ROOT_CLK		106
+#define IMX7D_DRAM_ALT_ROOT_SRC		107
+#define IMX7D_DRAM_ALT_ROOT_CG		108
+#define IMX7D_DRAM_ALT_ROOT_DIV		109
+#define IMX7D_USB_HSIC_ROOT_CLK		110
+#define IMX7D_USB_HSIC_ROOT_SRC		111
+#define IMX7D_USB_HSIC_ROOT_CG		112
+#define IMX7D_USB_HSIC_ROOT_DIV		113
+#define IMX7D_PCIE_CTRL_ROOT_CLK	114
+#define IMX7D_PCIE_CTRL_ROOT_SRC	115
+#define IMX7D_PCIE_CTRL_ROOT_CG		116
+#define IMX7D_PCIE_CTRL_ROOT_DIV	117
+#define IMX7D_PCIE_PHY_ROOT_CLK		118
+#define IMX7D_PCIE_PHY_ROOT_SRC		119
+#define IMX7D_PCIE_PHY_ROOT_CG		120
+#define IMX7D_PCIE_PHY_ROOT_DIV		121
+#define IMX7D_EPDC_PIXEL_ROOT_CLK	122
+#define IMX7D_EPDC_PIXEL_ROOT_SRC	123
+#define IMX7D_EPDC_PIXEL_ROOT_CG	124
+#define IMX7D_EPDC_PIXEL_ROOT_DIV	125
+#define IMX7D_LCDIF_PIXEL_ROOT_CLK	126
+#define IMX7D_LCDIF_PIXEL_ROOT_SRC	127
+#define IMX7D_LCDIF_PIXEL_ROOT_CG	128
+#define IMX7D_LCDIF_PIXEL_ROOT_DIV	129
+#define IMX7D_MIPI_DSI_ROOT_CLK		130
+#define IMX7D_MIPI_DSI_ROOT_SRC		131
+#define IMX7D_MIPI_DSI_ROOT_CG		132
+#define IMX7D_MIPI_DSI_ROOT_DIV		133
+#define IMX7D_MIPI_CSI_ROOT_CLK		134
+#define IMX7D_MIPI_CSI_ROOT_SRC		135
+#define IMX7D_MIPI_CSI_ROOT_CG		136
+#define IMX7D_MIPI_CSI_ROOT_DIV		137
+#define IMX7D_MIPI_DPHY_ROOT_CLK	138
+#define IMX7D_MIPI_DPHY_ROOT_SRC	139
+#define IMX7D_MIPI_DPHY_ROOT_CG		140
+#define IMX7D_MIPI_DPHY_ROOT_DIV	141
+#define IMX7D_SAI1_ROOT_CLK		142
+#define IMX7D_SAI1_ROOT_SRC		143
+#define IMX7D_SAI1_ROOT_CG		144
+#define IMX7D_SAI1_ROOT_DIV		145
+#define IMX7D_SAI2_ROOT_CLK		146
+#define IMX7D_SAI2_ROOT_SRC		147
+#define IMX7D_SAI2_ROOT_CG		148
+#define IMX7D_SAI2_ROOT_DIV		149
+#define IMX7D_SAI3_ROOT_CLK		150
+#define IMX7D_SAI3_ROOT_SRC		151
+#define IMX7D_SAI3_ROOT_CG		152
+#define IMX7D_SAI3_ROOT_DIV		153
+#define IMX7D_SPDIF_ROOT_CLK		154
+#define IMX7D_SPDIF_ROOT_SRC		155
+#define IMX7D_SPDIF_ROOT_CG		156
+#define IMX7D_SPDIF_ROOT_DIV		157
+#define IMX7D_ENET1_IPG_ROOT_CLK        158
+#define IMX7D_ENET1_REF_ROOT_SRC	159
+#define IMX7D_ENET1_REF_ROOT_CG		160
+#define IMX7D_ENET1_REF_ROOT_DIV	161
+#define IMX7D_ENET1_TIME_ROOT_CLK	162
+#define IMX7D_ENET1_TIME_ROOT_SRC	163
+#define IMX7D_ENET1_TIME_ROOT_CG	164
+#define IMX7D_ENET1_TIME_ROOT_DIV	165
+#define IMX7D_ENET2_IPG_ROOT_CLK        166
+#define IMX7D_ENET2_REF_ROOT_SRC	167
+#define IMX7D_ENET2_REF_ROOT_CG		168
+#define IMX7D_ENET2_REF_ROOT_DIV	169
+#define IMX7D_ENET2_TIME_ROOT_CLK	170
+#define IMX7D_ENET2_TIME_ROOT_SRC	171
+#define IMX7D_ENET2_TIME_ROOT_CG	172
+#define IMX7D_ENET2_TIME_ROOT_DIV	173
+#define IMX7D_ENET_PHY_REF_ROOT_CLK	174
+#define IMX7D_ENET_PHY_REF_ROOT_SRC	175
+#define IMX7D_ENET_PHY_REF_ROOT_CG	176
+#define IMX7D_ENET_PHY_REF_ROOT_DIV	177
+#define IMX7D_EIM_ROOT_CLK		178
+#define IMX7D_EIM_ROOT_SRC		179
+#define IMX7D_EIM_ROOT_CG		180
+#define IMX7D_EIM_ROOT_DIV		181
+#define IMX7D_NAND_ROOT_CLK		182
+#define IMX7D_NAND_ROOT_SRC		183
+#define IMX7D_NAND_ROOT_CG		184
+#define IMX7D_NAND_ROOT_DIV		185
+#define IMX7D_QSPI_ROOT_CLK		186
+#define IMX7D_QSPI_ROOT_SRC		187
+#define IMX7D_QSPI_ROOT_CG		188
+#define IMX7D_QSPI_ROOT_DIV		189
+#define IMX7D_USDHC1_ROOT_CLK		190
+#define IMX7D_USDHC1_ROOT_SRC		191
+#define IMX7D_USDHC1_ROOT_CG		192
+#define IMX7D_USDHC1_ROOT_DIV		193
+#define IMX7D_USDHC2_ROOT_CLK		194
+#define IMX7D_USDHC2_ROOT_SRC		195
+#define IMX7D_USDHC2_ROOT_CG		196
+#define IMX7D_USDHC2_ROOT_DIV		197
+#define IMX7D_USDHC3_ROOT_CLK		198
+#define IMX7D_USDHC3_ROOT_SRC		199
+#define IMX7D_USDHC3_ROOT_CG		200
+#define IMX7D_USDHC3_ROOT_DIV		201
+#define IMX7D_CAN1_ROOT_CLK		202
+#define IMX7D_CAN1_ROOT_SRC		203
+#define IMX7D_CAN1_ROOT_CG		204
+#define IMX7D_CAN1_ROOT_DIV		205
+#define IMX7D_CAN2_ROOT_CLK		206
+#define IMX7D_CAN2_ROOT_SRC		207
+#define IMX7D_CAN2_ROOT_CG		208
+#define IMX7D_CAN2_ROOT_DIV		209
+#define IMX7D_I2C1_ROOT_CLK		210
+#define IMX7D_I2C1_ROOT_SRC		211
+#define IMX7D_I2C1_ROOT_CG		212
+#define IMX7D_I2C1_ROOT_DIV		213
+#define IMX7D_I2C2_ROOT_CLK		214
+#define IMX7D_I2C2_ROOT_SRC		215
+#define IMX7D_I2C2_ROOT_CG		216
+#define IMX7D_I2C2_ROOT_DIV		217
+#define IMX7D_I2C3_ROOT_CLK		218
+#define IMX7D_I2C3_ROOT_SRC		219
+#define IMX7D_I2C3_ROOT_CG		220
+#define IMX7D_I2C3_ROOT_DIV		221
+#define IMX7D_I2C4_ROOT_CLK		222
+#define IMX7D_I2C4_ROOT_SRC		223
+#define IMX7D_I2C4_ROOT_CG		224
+#define IMX7D_I2C4_ROOT_DIV		225
+#define IMX7D_UART1_ROOT_CLK		226
+#define IMX7D_UART1_ROOT_SRC		227
+#define IMX7D_UART1_ROOT_CG		228
+#define IMX7D_UART1_ROOT_DIV		229
+#define IMX7D_UART2_ROOT_CLK		230
+#define IMX7D_UART2_ROOT_SRC		231
+#define IMX7D_UART2_ROOT_CG		232
+#define IMX7D_UART2_ROOT_DIV		233
+#define IMX7D_UART3_ROOT_CLK		234
+#define IMX7D_UART3_ROOT_SRC		235
+#define IMX7D_UART3_ROOT_CG		236
+#define IMX7D_UART3_ROOT_DIV		237
+#define IMX7D_UART4_ROOT_CLK		238
+#define IMX7D_UART4_ROOT_SRC		239
+#define IMX7D_UART4_ROOT_CG		240
+#define IMX7D_UART4_ROOT_DIV		241
+#define IMX7D_UART5_ROOT_CLK		242
+#define IMX7D_UART5_ROOT_SRC		243
+#define IMX7D_UART5_ROOT_CG		244
+#define IMX7D_UART5_ROOT_DIV		245
+#define IMX7D_UART6_ROOT_CLK		246
+#define IMX7D_UART6_ROOT_SRC		247
+#define IMX7D_UART6_ROOT_CG		248
+#define IMX7D_UART6_ROOT_DIV		249
+#define IMX7D_UART7_ROOT_CLK		250
+#define IMX7D_UART7_ROOT_SRC		251
+#define IMX7D_UART7_ROOT_CG		252
+#define IMX7D_UART7_ROOT_DIV		253
+#define IMX7D_ECSPI1_ROOT_CLK		254
+#define IMX7D_ECSPI1_ROOT_SRC		255
+#define IMX7D_ECSPI1_ROOT_CG		256
+#define IMX7D_ECSPI1_ROOT_DIV		257
+#define IMX7D_ECSPI2_ROOT_CLK		258
+#define IMX7D_ECSPI2_ROOT_SRC		259
+#define IMX7D_ECSPI2_ROOT_CG		260
+#define IMX7D_ECSPI2_ROOT_DIV		261
+#define IMX7D_ECSPI3_ROOT_CLK		262
+#define IMX7D_ECSPI3_ROOT_SRC		263
+#define IMX7D_ECSPI3_ROOT_CG		264
+#define IMX7D_ECSPI3_ROOT_DIV		265
+#define IMX7D_ECSPI4_ROOT_CLK		266
+#define IMX7D_ECSPI4_ROOT_SRC		267
+#define IMX7D_ECSPI4_ROOT_CG		268
+#define IMX7D_ECSPI4_ROOT_DIV		269
+#define IMX7D_PWM1_ROOT_CLK		270
+#define IMX7D_PWM1_ROOT_SRC		271
+#define IMX7D_PWM1_ROOT_CG		272
+#define IMX7D_PWM1_ROOT_DIV		273
+#define IMX7D_PWM2_ROOT_CLK		274
+#define IMX7D_PWM2_ROOT_SRC		275
+#define IMX7D_PWM2_ROOT_CG		276
+#define IMX7D_PWM2_ROOT_DIV		277
+#define IMX7D_PWM3_ROOT_CLK		278
+#define IMX7D_PWM3_ROOT_SRC		279
+#define IMX7D_PWM3_ROOT_CG		280
+#define IMX7D_PWM3_ROOT_DIV		281
+#define IMX7D_PWM4_ROOT_CLK		282
+#define IMX7D_PWM4_ROOT_SRC		283
+#define IMX7D_PWM4_ROOT_CG		284
+#define IMX7D_PWM4_ROOT_DIV		285
+#define IMX7D_FLEXTIMER1_ROOT_CLK	286
+#define IMX7D_FLEXTIMER1_ROOT_SRC	287
+#define IMX7D_FLEXTIMER1_ROOT_CG	288
+#define IMX7D_FLEXTIMER1_ROOT_DIV	289
+#define IMX7D_FLEXTIMER2_ROOT_CLK	290
+#define IMX7D_FLEXTIMER2_ROOT_SRC	291
+#define IMX7D_FLEXTIMER2_ROOT_CG	292
+#define IMX7D_FLEXTIMER2_ROOT_DIV	293
+#define IMX7D_SIM1_ROOT_CLK		294
+#define IMX7D_SIM1_ROOT_SRC		295
+#define IMX7D_SIM1_ROOT_CG		296
+#define IMX7D_SIM1_ROOT_DIV		297
+#define IMX7D_SIM2_ROOT_CLK		298
+#define IMX7D_SIM2_ROOT_SRC		299
+#define IMX7D_SIM2_ROOT_CG		300
+#define IMX7D_SIM2_ROOT_DIV		301
+#define IMX7D_GPT1_ROOT_CLK		302
+#define IMX7D_GPT1_ROOT_SRC		303
+#define IMX7D_GPT1_ROOT_CG		304
+#define IMX7D_GPT1_ROOT_DIV		305
+#define IMX7D_GPT2_ROOT_CLK		306
+#define IMX7D_GPT2_ROOT_SRC		307
+#define IMX7D_GPT2_ROOT_CG		308
+#define IMX7D_GPT2_ROOT_DIV		309
+#define IMX7D_GPT3_ROOT_CLK		310
+#define IMX7D_GPT3_ROOT_SRC		311
+#define IMX7D_GPT3_ROOT_CG		312
+#define IMX7D_GPT3_ROOT_DIV		313
+#define IMX7D_GPT4_ROOT_CLK		314
+#define IMX7D_GPT4_ROOT_SRC		315
+#define IMX7D_GPT4_ROOT_CG		316
+#define IMX7D_GPT4_ROOT_DIV		317
+#define IMX7D_TRACE_ROOT_CLK		318
+#define IMX7D_TRACE_ROOT_SRC		319
+#define IMX7D_TRACE_ROOT_CG		320
+#define IMX7D_TRACE_ROOT_DIV		321
+#define IMX7D_WDOG1_ROOT_CLK		322
+#define IMX7D_WDOG_ROOT_SRC		323
+#define IMX7D_WDOG_ROOT_CG		324
+#define IMX7D_WDOG_ROOT_DIV		325
+#define IMX7D_CSI_MCLK_ROOT_CLK		326
+#define IMX7D_CSI_MCLK_ROOT_SRC		327
+#define IMX7D_CSI_MCLK_ROOT_CG		328
+#define IMX7D_CSI_MCLK_ROOT_DIV		329
+#define IMX7D_AUDIO_MCLK_ROOT_CLK	330
+#define IMX7D_AUDIO_MCLK_ROOT_SRC	331
+#define IMX7D_AUDIO_MCLK_ROOT_CG	332
+#define IMX7D_AUDIO_MCLK_ROOT_DIV	333
+#define IMX7D_WRCLK_ROOT_CLK		334
+#define IMX7D_WRCLK_ROOT_SRC		335
+#define IMX7D_WRCLK_ROOT_CG		336
+#define IMX7D_WRCLK_ROOT_DIV		337
+#define IMX7D_CLKO1_ROOT_SRC		338
+#define IMX7D_CLKO1_ROOT_CG		339
+#define IMX7D_CLKO1_ROOT_DIV		340
+#define IMX7D_CLKO2_ROOT_SRC		341
+#define IMX7D_CLKO2_ROOT_CG		342
+#define IMX7D_CLKO2_ROOT_DIV		343
+#define IMX7D_MAIN_AXI_ROOT_PRE_DIV	344
+#define IMX7D_DISP_AXI_ROOT_PRE_DIV	345
+#define IMX7D_ENET_AXI_ROOT_PRE_DIV	346
+#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
+#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV	348
+#define IMX7D_USB_HSIC_ROOT_PRE_DIV	349
+#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV	350
+#define IMX7D_PCIE_PHY_ROOT_PRE_DIV	351
+#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV	352
+#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV	353
+#define IMX7D_MIPI_DSI_ROOT_PRE_DIV	354
+#define IMX7D_MIPI_CSI_ROOT_PRE_DIV	355
+#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV	356
+#define IMX7D_SAI1_ROOT_PRE_DIV		357
+#define IMX7D_SAI2_ROOT_PRE_DIV		358
+#define IMX7D_SAI3_ROOT_PRE_DIV		359
+#define IMX7D_SPDIF_ROOT_PRE_DIV	360
+#define IMX7D_ENET1_REF_ROOT_PRE_DIV	361
+#define IMX7D_ENET1_TIME_ROOT_PRE_DIV	362
+#define IMX7D_ENET2_REF_ROOT_PRE_DIV	363
+#define IMX7D_ENET2_TIME_ROOT_PRE_DIV	364
+#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
+#define IMX7D_EIM_ROOT_PRE_DIV		366
+#define IMX7D_NAND_ROOT_PRE_DIV		367
+#define IMX7D_QSPI_ROOT_PRE_DIV		368
+#define IMX7D_USDHC1_ROOT_PRE_DIV	369
+#define IMX7D_USDHC2_ROOT_PRE_DIV	370
+#define IMX7D_USDHC3_ROOT_PRE_DIV	371
+#define IMX7D_CAN1_ROOT_PRE_DIV		372
+#define IMX7D_CAN2_ROOT_PRE_DIV		373
+#define IMX7D_I2C1_ROOT_PRE_DIV		374
+#define IMX7D_I2C2_ROOT_PRE_DIV		375
+#define IMX7D_I2C3_ROOT_PRE_DIV		376
+#define IMX7D_I2C4_ROOT_PRE_DIV		377
+#define IMX7D_UART1_ROOT_PRE_DIV	378
+#define IMX7D_UART2_ROOT_PRE_DIV	379
+#define IMX7D_UART3_ROOT_PRE_DIV	380
+#define IMX7D_UART4_ROOT_PRE_DIV	381
+#define IMX7D_UART5_ROOT_PRE_DIV	382
+#define IMX7D_UART6_ROOT_PRE_DIV	383
+#define IMX7D_UART7_ROOT_PRE_DIV	384
+#define IMX7D_ECSPI1_ROOT_PRE_DIV	385
+#define IMX7D_ECSPI2_ROOT_PRE_DIV	386
+#define IMX7D_ECSPI3_ROOT_PRE_DIV	387
+#define IMX7D_ECSPI4_ROOT_PRE_DIV	388
+#define IMX7D_PWM1_ROOT_PRE_DIV		389
+#define IMX7D_PWM2_ROOT_PRE_DIV		390
+#define IMX7D_PWM3_ROOT_PRE_DIV		391
+#define IMX7D_PWM4_ROOT_PRE_DIV		392
+#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV	393
+#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV	394
+#define IMX7D_SIM1_ROOT_PRE_DIV		395
+#define IMX7D_SIM2_ROOT_PRE_DIV		396
+#define IMX7D_GPT1_ROOT_PRE_DIV		397
+#define IMX7D_GPT2_ROOT_PRE_DIV		398
+#define IMX7D_GPT3_ROOT_PRE_DIV		399
+#define IMX7D_GPT4_ROOT_PRE_DIV		400
+#define IMX7D_TRACE_ROOT_PRE_DIV	401
+#define IMX7D_WDOG_ROOT_PRE_DIV		402
+#define IMX7D_CSI_MCLK_ROOT_PRE_DIV	403
+#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV	404
+#define IMX7D_WRCLK_ROOT_PRE_DIV	405
+#define IMX7D_CLKO1_ROOT_PRE_DIV	406
+#define IMX7D_CLKO2_ROOT_PRE_DIV	407
+#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
+#define IMX7D_DRAM_ALT_ROOT_PRE_DIV	409
+#define IMX7D_LVDS1_IN_CLK		410
+#define IMX7D_LVDS1_OUT_SEL		411
+#define IMX7D_LVDS1_OUT_CLK		412
+#define IMX7D_CLK_DUMMY			413
+#define IMX7D_GPT_3M_CLK		414
+#define IMX7D_OCRAM_CLK			415
+#define IMX7D_OCRAM_S_CLK		416
+#define IMX7D_WDOG2_ROOT_CLK		417
+#define IMX7D_WDOG3_ROOT_CLK		418
+#define IMX7D_WDOG4_ROOT_CLK		419
+#define IMX7D_SDMA_CORE_CLK		420
+#define IMX7D_USB1_MAIN_480M_CLK	421
+#define IMX7D_USB_CTRL_CLK		422
+#define IMX7D_USB_PHY1_CLK		423
+#define IMX7D_USB_PHY2_CLK		424
+#define IMX7D_IPG_ROOT_CLK		425
+#define IMX7D_SAI1_IPG_CLK		426
+#define IMX7D_SAI2_IPG_CLK		427
+#define IMX7D_SAI3_IPG_CLK		428
+#define IMX7D_PLL_AUDIO_TEST_DIV	429
+#define IMX7D_PLL_AUDIO_POST_DIV	430
+#define IMX7D_PLL_VIDEO_TEST_DIV	431
+#define IMX7D_PLL_VIDEO_POST_DIV	432
+#define IMX7D_MU_ROOT_CLK		433
+#define IMX7D_SEMA4_HS_ROOT_CLK		434
+#define IMX7D_PLL_DRAM_TEST_DIV		435
+#define IMX7D_ADC_ROOT_CLK		436
+#define IMX7D_CLK_ARM			437
+#define IMX7D_CKIL			438
+#define IMX7D_OCOTP_CLK			439
+#define IMX7D_NAND_RAWNAND_CLK		440
+#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
+#define IMX7D_SNVS_CLK			442
+#define IMX7D_CAAM_CLK			443
+#define IMX7D_KPP_ROOT_CLK		444
+#define IMX7D_CLK_END			445
+#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */

include/dt-bindings/clock/jz4740-cgu.h

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4740 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+
+#define JZ4740_CLK_EXT		0
+#define JZ4740_CLK_RTC		1
+#define JZ4740_CLK_PLL		2
+#define JZ4740_CLK_PLL_HALF	3
+#define JZ4740_CLK_CCLK		4
+#define JZ4740_CLK_HCLK		5
+#define JZ4740_CLK_PCLK		6
+#define JZ4740_CLK_MCLK		7
+#define JZ4740_CLK_LCD		8
+#define JZ4740_CLK_LCD_PCLK	9
+#define JZ4740_CLK_I2S		10
+#define JZ4740_CLK_SPI		11
+#define JZ4740_CLK_MMC		12
+#define JZ4740_CLK_UHC		13
+#define JZ4740_CLK_UDC		14
+#define JZ4740_CLK_UART0	15
+#define JZ4740_CLK_UART1	16
+#define JZ4740_CLK_DMA		17
+#define JZ4740_CLK_IPU		18
+#define JZ4740_CLK_ADC		19
+#define JZ4740_CLK_I2C		20
+#define JZ4740_CLK_AIC		21
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */

include/dt-bindings/clock/jz4770-cgu.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4770-cgu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
+
+#define JZ4770_CLK_EXT		0
+#define JZ4770_CLK_OSC32K	1
+#define JZ4770_CLK_PLL0		2
+#define JZ4770_CLK_PLL1		3
+#define JZ4770_CLK_CCLK		4
+#define JZ4770_CLK_H0CLK	5
+#define JZ4770_CLK_H1CLK	6
+#define JZ4770_CLK_H2CLK	7
+#define JZ4770_CLK_C1CLK	8
+#define JZ4770_CLK_PCLK		9
+#define JZ4770_CLK_MMC0_MUX	10
+#define JZ4770_CLK_MMC0		11
+#define JZ4770_CLK_MMC1_MUX	12
+#define JZ4770_CLK_MMC1		13
+#define JZ4770_CLK_MMC2_MUX	14
+#define JZ4770_CLK_MMC2		15
+#define JZ4770_CLK_CIM		16
+#define JZ4770_CLK_UHC		17
+#define JZ4770_CLK_GPU		18
+#define JZ4770_CLK_BCH		19
+#define JZ4770_CLK_LPCLK_MUX	20
+#define JZ4770_CLK_GPS		21
+#define JZ4770_CLK_SSI_MUX	22
+#define JZ4770_CLK_PCM_MUX	23
+#define JZ4770_CLK_I2S		24
+#define JZ4770_CLK_OTG		25
+#define JZ4770_CLK_SSI0		26
+#define JZ4770_CLK_SSI1		27
+#define JZ4770_CLK_SSI2		28
+#define JZ4770_CLK_PCM0		29
+#define JZ4770_CLK_PCM1		30
+#define JZ4770_CLK_DMA		31
+#define JZ4770_CLK_I2C0		32
+#define JZ4770_CLK_I2C1		33
+#define JZ4770_CLK_I2C2		34
+#define JZ4770_CLK_UART0	35
+#define JZ4770_CLK_UART1	36
+#define JZ4770_CLK_UART2	37
+#define JZ4770_CLK_UART3	38
+#define JZ4770_CLK_IPU		39
+#define JZ4770_CLK_ADC		40
+#define JZ4770_CLK_AIC		41
+#define JZ4770_CLK_AUX		42
+#define JZ4770_CLK_VPU		43
+#define JZ4770_CLK_UHC_PHY	44
+#define JZ4770_CLK_OTG_PHY	45
+#define JZ4770_CLK_EXT512	46
+#define JZ4770_CLK_RTC		47
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */

include/dt-bindings/clock/jz4780-cgu.h

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4780 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+
+#define JZ4780_CLK_EXCLK	0
+#define JZ4780_CLK_RTCLK	1
+#define JZ4780_CLK_APLL		2
+#define JZ4780_CLK_MPLL		3
+#define JZ4780_CLK_EPLL		4
+#define JZ4780_CLK_VPLL		5
+#define JZ4780_CLK_OTGPHY	6
+#define JZ4780_CLK_SCLKA	7
+#define JZ4780_CLK_CPUMUX	8
+#define JZ4780_CLK_CPU		9
+#define JZ4780_CLK_L2CACHE	10
+#define JZ4780_CLK_AHB0		11
+#define JZ4780_CLK_AHB2PMUX	12
+#define JZ4780_CLK_AHB2		13
+#define JZ4780_CLK_PCLK		14
+#define JZ4780_CLK_DDR		15
+#define JZ4780_CLK_VPU		16
+#define JZ4780_CLK_I2SPLL	17
+#define JZ4780_CLK_I2S		18
+#define JZ4780_CLK_LCD0PIXCLK	19
+#define JZ4780_CLK_LCD1PIXCLK	20
+#define JZ4780_CLK_MSCMUX	21
+#define JZ4780_CLK_MSC0		22
+#define JZ4780_CLK_MSC1		23
+#define JZ4780_CLK_MSC2		24
+#define JZ4780_CLK_UHC		25
+#define JZ4780_CLK_SSIPLL	26
+#define JZ4780_CLK_SSI		27
+#define JZ4780_CLK_CIMMCLK	28
+#define JZ4780_CLK_PCMPLL	29
+#define JZ4780_CLK_PCM		30
+#define JZ4780_CLK_GPU		31
+#define JZ4780_CLK_HDMI		32
+#define JZ4780_CLK_BCH		33
+#define JZ4780_CLK_NEMC		34
+#define JZ4780_CLK_OTG0		35
+#define JZ4780_CLK_SSI0		36
+#define JZ4780_CLK_SMB0		37
+#define JZ4780_CLK_SMB1		38
+#define JZ4780_CLK_SCC		39
+#define JZ4780_CLK_AIC		40
+#define JZ4780_CLK_TSSI0	41
+#define JZ4780_CLK_OWI		42
+#define JZ4780_CLK_KBC		43
+#define JZ4780_CLK_SADC		44
+#define JZ4780_CLK_UART0	45
+#define JZ4780_CLK_UART1	46
+#define JZ4780_CLK_UART2	47
+#define JZ4780_CLK_UART3	48
+#define JZ4780_CLK_SSI1		49
+#define JZ4780_CLK_SSI2		50
+#define JZ4780_CLK_PDMA		51
+#define JZ4780_CLK_GPS		52
+#define JZ4780_CLK_MAC		53
+#define JZ4780_CLK_SMB2		54
+#define JZ4780_CLK_CIM		55
+#define JZ4780_CLK_LCD		56
+#define JZ4780_CLK_TVE		57
+#define JZ4780_CLK_IPU		58
+#define JZ4780_CLK_DDR0		59
+#define JZ4780_CLK_DDR1		60
+#define JZ4780_CLK_SMB3		61
+#define JZ4780_CLK_TSSI1	62
+#define JZ4780_CLK_COMPRESS	63
+#define JZ4780_CLK_AIC1		64
+#define JZ4780_CLK_GPVLC	65
+#define JZ4780_CLK_OTG1		66
+#define JZ4780_CLK_UART4	67
+#define JZ4780_CLK_AHBMON	68
+#define JZ4780_CLK_SMB4		69
+#define JZ4780_CLK_DES		70
+#define JZ4780_CLK_X2D		71
+#define JZ4780_CLK_CORE1	72
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */

include/dt-bindings/clock/lpc18xx-ccu.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+/* Clock Control Unit 1 (CCU1) clock offsets */
+#define CLK_APB3_BUS		0x100
+#define CLK_APB3_I2C1		0x108
+#define CLK_APB3_DAC		0x110
+#define CLK_APB3_ADC0		0x118
+#define CLK_APB3_ADC1		0x120
+#define CLK_APB3_CAN0		0x128
+#define CLK_APB1_BUS		0x200
+#define CLK_APB1_MOTOCON_PWM	0x208
+#define CLK_APB1_I2C0		0x210
+#define CLK_APB1_I2S		0x218
+#define CLK_APB1_CAN1		0x220
+#define CLK_SPIFI		0x300
+#define CLK_CPU_BUS		0x400
+#define CLK_CPU_SPIFI		0x408
+#define CLK_CPU_GPIO		0x410
+#define CLK_CPU_LCD		0x418
+#define CLK_CPU_ETHERNET	0x420
+#define CLK_CPU_USB0		0x428
+#define CLK_CPU_EMC		0x430
+#define CLK_CPU_SDIO		0x438
+#define CLK_CPU_DMA		0x440
+#define CLK_CPU_CORE		0x448
+#define CLK_CPU_SCT		0x468
+#define CLK_CPU_USB1		0x470
+#define CLK_CPU_EMCDIV		0x478
+#define CLK_CPU_FLASHA		0x480
+#define CLK_CPU_FLASHB		0x488
+#define CLK_CPU_M0APP		0x490
+#define CLK_CPU_ADCHS		0x498
+#define CLK_CPU_EEPROM		0x4a0
+#define CLK_CPU_WWDT		0x500
+#define CLK_CPU_UART0		0x508
+#define CLK_CPU_UART1		0x510
+#define CLK_CPU_SSP0		0x518
+#define CLK_CPU_TIMER0		0x520
+#define CLK_CPU_TIMER1		0x528
+#define CLK_CPU_SCU		0x530
+#define CLK_CPU_CREG		0x538
+#define CLK_CPU_RITIMER		0x600
+#define CLK_CPU_UART2		0x608
+#define CLK_CPU_UART3		0x610
+#define CLK_CPU_TIMER2		0x618
+#define CLK_CPU_TIMER3		0x620
+#define CLK_CPU_SSP1		0x628
+#define CLK_CPU_QEI		0x630
+#define CLK_PERIPH_BUS		0x700
+#define CLK_PERIPH_CORE		0x710
+#define CLK_PERIPH_SGPIO	0x718
+#define CLK_USB0		0x800
+#define CLK_USB1		0x900
+#define CLK_SPI			0xA00
+#define CLK_ADCHS		0xB00
+
+/* Clock Control Unit 2 (CCU2) clock offsets */
+#define CLK_AUDIO		0x100
+#define CLK_APB2_UART3		0x200
+#define CLK_APB2_UART2		0x300
+#define CLK_APB0_UART1		0x400
+#define CLK_APB0_UART0		0x500
+#define CLK_APB2_SSP1		0x600
+#define CLK_APB0_SSP0		0x700
+#define CLK_SDIO		0x800

include/dt-bindings/clock/lpc18xx-cgu.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+/* LPC18xx/43xx base clock ids */
+#define BASE_SAFE_CLK		0
+#define BASE_USB0_CLK		1
+#define BASE_PERIPH_CLK		2
+#define BASE_USB1_CLK		3
+#define BASE_CPU_CLK		4
+#define BASE_SPIFI_CLK		5
+#define BASE_SPI_CLK		6
+#define BASE_PHY_RX_CLK		7
+#define BASE_PHY_TX_CLK		8
+#define BASE_APB1_CLK		9
+#define BASE_APB3_CLK		10
+#define BASE_LCD_CLK		11
+#define BASE_ADCHS_CLK		12
+#define BASE_SDIO_CLK		13
+#define BASE_SSP0_CLK		14
+#define BASE_SSP1_CLK		15
+#define BASE_UART0_CLK		16
+#define BASE_UART1_CLK		17
+#define BASE_UART2_CLK		18
+#define BASE_UART3_CLK		19
+#define BASE_OUT_CLK		20
+#define BASE_RES1_CLK		21
+#define BASE_RES2_CLK		22
+#define BASE_RES3_CLK		23
+#define BASE_RES4_CLK		24
+#define BASE_AUDIO_CLK		25
+#define BASE_CGU_OUT0_CLK	26
+#define BASE_CGU_OUT1_CLK	27
+#define BASE_CLK_MAX		(BASE_CGU_OUT1_CLK + 1)

include/dt-bindings/clock/lpc32xx-clock.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
+#define __DT_BINDINGS_LPC32XX_CLOCK_H
+
+/* LPC32XX System Control Block clocks */
+#define LPC32XX_CLK_RTC		1
+#define LPC32XX_CLK_DMA		2
+#define LPC32XX_CLK_MLC		3
+#define LPC32XX_CLK_SLC		4
+#define LPC32XX_CLK_LCD		5
+#define LPC32XX_CLK_MAC		6
+#define LPC32XX_CLK_SD		7
+#define LPC32XX_CLK_DDRAM	8
+#define LPC32XX_CLK_SSP0	9
+#define LPC32XX_CLK_SSP1	10
+#define LPC32XX_CLK_UART3	11
+#define LPC32XX_CLK_UART4	12
+#define LPC32XX_CLK_UART5	13
+#define LPC32XX_CLK_UART6	14
+#define LPC32XX_CLK_IRDA	15
+#define LPC32XX_CLK_I2C1	16
+#define LPC32XX_CLK_I2C2	17
+#define LPC32XX_CLK_TIMER0	18
+#define LPC32XX_CLK_TIMER1	19
+#define LPC32XX_CLK_TIMER2	20
+#define LPC32XX_CLK_TIMER3	21
+#define LPC32XX_CLK_TIMER4	22
+#define LPC32XX_CLK_TIMER5	23
+#define LPC32XX_CLK_WDOG	24
+#define LPC32XX_CLK_I2S0	25
+#define LPC32XX_CLK_I2S1	26
+#define LPC32XX_CLK_SPI1	27
+#define LPC32XX_CLK_SPI2	28
+#define LPC32XX_CLK_MCPWM	29
+#define LPC32XX_CLK_HSTIMER	30
+#define LPC32XX_CLK_KEY		31
+#define LPC32XX_CLK_PWM1	32
+#define LPC32XX_CLK_PWM2	33
+#define LPC32XX_CLK_ADC		34
+#define LPC32XX_CLK_HCLK_PLL	35
+#define LPC32XX_CLK_PERIPH	36
+
+/* LPC32XX USB clocks */
+#define LPC32XX_USB_CLK_I2C	1
+#define LPC32XX_USB_CLK_DEVICE	2
+#define LPC32XX_USB_CLK_HOST	3
+
+#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */

include/dt-bindings/clock/lsi,axm5516-clks.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2014 LSI Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AXM5516_H
+#define _DT_BINDINGS_CLK_AXM5516_H
+
+#define AXXIA_CLK_FAB_PLL	0
+#define AXXIA_CLK_CPU_PLL	1
+#define AXXIA_CLK_SYS_PLL	2
+#define AXXIA_CLK_SM0_PLL	3
+#define AXXIA_CLK_SM1_PLL	4
+#define AXXIA_CLK_FAB_DIV	5
+#define AXXIA_CLK_SYS_DIV	6
+#define AXXIA_CLK_NRCP_DIV	7
+#define AXXIA_CLK_CPU0_DIV	8
+#define AXXIA_CLK_CPU1_DIV	9
+#define AXXIA_CLK_CPU2_DIV	10
+#define AXXIA_CLK_CPU3_DIV	11
+#define AXXIA_CLK_PER_DIV	12
+#define AXXIA_CLK_MMC_DIV	13
+#define AXXIA_CLK_FAB		14
+#define AXXIA_CLK_SYS		15
+#define AXXIA_CLK_NRCP		16
+#define AXXIA_CLK_CPU0		17
+#define AXXIA_CLK_CPU1		18
+#define AXXIA_CLK_CPU2		19
+#define AXXIA_CLK_CPU3		20
+#define AXXIA_CLK_PER		21
+#define AXXIA_CLK_MMC		22
+
+#endif

include/dt-bindings/clock/marvell,mmp2.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_MMP2_CLOCK_H
+#define __DTS_MARVELL_MMP2_CLOCK_H
+
+/* fixed clocks and plls */
+#define MMP2_CLK_CLK32			1
+#define MMP2_CLK_VCTCXO			2
+#define MMP2_CLK_PLL1			3
+#define MMP2_CLK_PLL1_2			8
+#define MMP2_CLK_PLL1_4			9
+#define MMP2_CLK_PLL1_8			10
+#define MMP2_CLK_PLL1_16		11
+#define MMP2_CLK_PLL1_3			12
+#define MMP2_CLK_PLL1_6			13
+#define MMP2_CLK_PLL1_12		14
+#define MMP2_CLK_PLL1_20		15
+#define MMP2_CLK_PLL2			16
+#define MMP2_CLK_PLL2_2			17
+#define MMP2_CLK_PLL2_4			18
+#define MMP2_CLK_PLL2_8			19
+#define MMP2_CLK_PLL2_16		20
+#define MMP2_CLK_PLL2_3			21
+#define MMP2_CLK_PLL2_6			22
+#define MMP2_CLK_PLL2_12		23
+#define MMP2_CLK_VCTCXO_2		24
+#define MMP2_CLK_VCTCXO_4		25
+#define MMP2_CLK_UART_PLL		26
+#define MMP2_CLK_USB_PLL		27
+
+/* apb periphrals */
+#define MMP2_CLK_TWSI0			60
+#define MMP2_CLK_TWSI1			61
+#define MMP2_CLK_TWSI2			62
+#define MMP2_CLK_TWSI3			63
+#define MMP2_CLK_TWSI4			64
+#define MMP2_CLK_TWSI5			65
+#define MMP2_CLK_GPIO			66
+#define MMP2_CLK_KPC			67
+#define MMP2_CLK_RTC			68
+#define MMP2_CLK_PWM0			69
+#define MMP2_CLK_PWM1			70
+#define MMP2_CLK_PWM2			71
+#define MMP2_CLK_PWM3			72
+#define MMP2_CLK_UART0			73
+#define MMP2_CLK_UART1			74
+#define MMP2_CLK_UART2			75
+#define MMP2_CLK_UART3			76
+#define MMP2_CLK_SSP0			77
+#define MMP2_CLK_SSP1			78
+#define MMP2_CLK_SSP2			79
+#define MMP2_CLK_SSP3			80
+#define MMP2_CLK_TIMER			81
+
+/* axi periphrals */
+#define MMP2_CLK_SDH0			101
+#define MMP2_CLK_SDH1			102
+#define MMP2_CLK_SDH2			103
+#define MMP2_CLK_SDH3			104
+#define MMP2_CLK_USB			105
+#define MMP2_CLK_DISP0			106
+#define MMP2_CLK_DISP0_MUX		107
+#define MMP2_CLK_DISP0_SPHY		108
+#define MMP2_CLK_DISP1			109
+#define MMP2_CLK_DISP1_MUX		110
+#define MMP2_CLK_CCIC_ARBITER		111
+#define MMP2_CLK_CCIC0			112
+#define MMP2_CLK_CCIC0_MIX		113
+#define MMP2_CLK_CCIC0_PHY		114
+#define MMP2_CLK_CCIC0_SPHY		115
+#define MMP2_CLK_CCIC1			116
+#define MMP2_CLK_CCIC1_MIX		117
+#define MMP2_CLK_CCIC1_PHY		118
+#define MMP2_CLK_CCIC1_SPHY		119
+
+#define MMP2_NR_CLKS			200
+#endif

include/dt-bindings/clock/marvell,pxa168.h

@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_PXA168_CLOCK_H
+#define __DTS_MARVELL_PXA168_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA168_CLK_CLK32		1
+#define PXA168_CLK_VCTCXO		2
+#define PXA168_CLK_PLL1			3
+#define PXA168_CLK_PLL1_2		8
+#define PXA168_CLK_PLL1_4		9
+#define PXA168_CLK_PLL1_8		10
+#define PXA168_CLK_PLL1_16		11
+#define PXA168_CLK_PLL1_6		12
+#define PXA168_CLK_PLL1_12		13
+#define PXA168_CLK_PLL1_24		14
+#define PXA168_CLK_PLL1_48		15
+#define PXA168_CLK_PLL1_96		16
+#define PXA168_CLK_PLL1_13		17
+#define PXA168_CLK_PLL1_13_1_5		18
+#define PXA168_CLK_PLL1_2_1_5		19
+#define PXA168_CLK_PLL1_3_16		20
+#define PXA168_CLK_PLL1_192		21
+#define PXA168_CLK_UART_PLL		27
+#define PXA168_CLK_USB_PLL		28
+
+/* apb periphrals */
+#define PXA168_CLK_TWSI0		60
+#define PXA168_CLK_TWSI1		61
+#define PXA168_CLK_TWSI2		62
+#define PXA168_CLK_TWSI3		63
+#define PXA168_CLK_GPIO			64
+#define PXA168_CLK_KPC			65
+#define PXA168_CLK_RTC			66
+#define PXA168_CLK_PWM0			67
+#define PXA168_CLK_PWM1			68
+#define PXA168_CLK_PWM2			69
+#define PXA168_CLK_PWM3			70
+#define PXA168_CLK_UART0		71
+#define PXA168_CLK_UART1		72
+#define PXA168_CLK_UART2		73
+#define PXA168_CLK_SSP0			74
+#define PXA168_CLK_SSP1			75
+#define PXA168_CLK_SSP2			76
+#define PXA168_CLK_SSP3			77
+#define PXA168_CLK_SSP4			78
+#define PXA168_CLK_TIMER		79
+
+/* axi periphrals */
+#define PXA168_CLK_DFC			100
+#define PXA168_CLK_SDH0			101
+#define PXA168_CLK_SDH1			102
+#define PXA168_CLK_SDH2			103
+#define PXA168_CLK_USB			104
+#define PXA168_CLK_SPH			105
+#define PXA168_CLK_DISP0		106
+#define PXA168_CLK_CCIC0		107
+#define PXA168_CLK_CCIC0_PHY		108
+#define PXA168_CLK_CCIC0_SPHY		109
+
+#define PXA168_NR_CLKS			200
+#endif

include/dt-bindings/clock/marvell,pxa1928.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_PXA1928_CLOCK_H
+#define __DTS_MARVELL_PXA1928_CLOCK_H
+
+/*
+ * Clock ID values here correspond to the control register offset/4.
+ */
+
+/* apb peripherals */
+#define PXA1928_CLK_RTC			0x00
+#define PXA1928_CLK_TWSI0		0x01
+#define PXA1928_CLK_TWSI1		0x02
+#define PXA1928_CLK_TWSI2		0x03
+#define PXA1928_CLK_TWSI3		0x04
+#define PXA1928_CLK_OWIRE		0x05
+#define PXA1928_CLK_KPC			0x06
+#define PXA1928_CLK_TB_ROTARY		0x07
+#define PXA1928_CLK_SW_JTAG		0x08
+#define PXA1928_CLK_TIMER1		0x09
+#define PXA1928_CLK_UART0		0x0b
+#define PXA1928_CLK_UART1		0x0c
+#define PXA1928_CLK_UART2		0x0d
+#define PXA1928_CLK_GPIO		0x0e
+#define PXA1928_CLK_PWM0		0x0f
+#define PXA1928_CLK_PWM1		0x10
+#define PXA1928_CLK_PWM2		0x11
+#define PXA1928_CLK_PWM3		0x12
+#define PXA1928_CLK_SSP0		0x13
+#define PXA1928_CLK_SSP1		0x14
+#define PXA1928_CLK_SSP2		0x15
+
+#define PXA1928_CLK_TWSI4		0x1f
+#define PXA1928_CLK_TWSI5		0x20
+#define PXA1928_CLK_UART3		0x22
+#define PXA1928_CLK_THSENS_GLOB		0x24
+#define PXA1928_CLK_THSENS_CPU		0x26
+#define PXA1928_CLK_THSENS_VPU		0x27
+#define PXA1928_CLK_THSENS_GC		0x28
+#define PXA1928_APBC_NR_CLKS		0x30
+
+
+/* axi peripherals */
+#define PXA1928_CLK_SDH0		0x15
+#define PXA1928_CLK_SDH1		0x16
+#define PXA1928_CLK_USB			0x17
+#define PXA1928_CLK_NAND		0x18
+#define PXA1928_CLK_DMA			0x19
+
+#define PXA1928_CLK_SDH2		0x3a
+#define PXA1928_CLK_SDH3		0x3b
+#define PXA1928_CLK_HSIC		0x3e
+#define PXA1928_CLK_SDH4		0x57
+#define PXA1928_CLK_GC3D		0x5d
+#define PXA1928_CLK_GC2D		0x5f
+
+#define PXA1928_APMU_NR_CLKS		0x60
+
+#endif

include/dt-bindings/clock/marvell,pxa910.h

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_PXA910_CLOCK_H
+#define __DTS_MARVELL_PXA910_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA910_CLK_CLK32		1
+#define PXA910_CLK_VCTCXO		2
+#define PXA910_CLK_PLL1			3
+#define PXA910_CLK_PLL1_2		8
+#define PXA910_CLK_PLL1_4		9
+#define PXA910_CLK_PLL1_8		10
+#define PXA910_CLK_PLL1_16		11
+#define PXA910_CLK_PLL1_6		12
+#define PXA910_CLK_PLL1_12		13
+#define PXA910_CLK_PLL1_24		14
+#define PXA910_CLK_PLL1_48		15
+#define PXA910_CLK_PLL1_96		16
+#define PXA910_CLK_PLL1_13		17
+#define PXA910_CLK_PLL1_13_1_5		18
+#define PXA910_CLK_PLL1_2_1_5		19
+#define PXA910_CLK_PLL1_3_16		20
+#define PXA910_CLK_PLL1_192		21
+#define PXA910_CLK_UART_PLL		27
+#define PXA910_CLK_USB_PLL		28
+
+/* apb periphrals */
+#define PXA910_CLK_TWSI0		60
+#define PXA910_CLK_TWSI1		61
+#define PXA910_CLK_TWSI2		62
+#define PXA910_CLK_TWSI3		63
+#define PXA910_CLK_GPIO			64
+#define PXA910_CLK_KPC			65
+#define PXA910_CLK_RTC			66
+#define PXA910_CLK_PWM0			67
+#define PXA910_CLK_PWM1			68
+#define PXA910_CLK_PWM2			69
+#define PXA910_CLK_PWM3			70
+#define PXA910_CLK_UART0		71
+#define PXA910_CLK_UART1		72
+#define PXA910_CLK_UART2		73
+#define PXA910_CLK_SSP0			74
+#define PXA910_CLK_SSP1			75
+#define PXA910_CLK_TIMER0		76
+#define PXA910_CLK_TIMER1		77
+
+/* axi periphrals */
+#define PXA910_CLK_DFC			100
+#define PXA910_CLK_SDH0			101
+#define PXA910_CLK_SDH1			102
+#define PXA910_CLK_SDH2			103
+#define PXA910_CLK_USB			104
+#define PXA910_CLK_SPH			105
+#define PXA910_CLK_DISP0		106
+#define PXA910_CLK_CCIC0		107
+#define PXA910_CLK_CCIC0_PHY		108
+#define PXA910_CLK_CCIC0_SPHY		109
+
+#define PXA910_NR_CLKS			200
+#endif

include/dt-bindings/clock/maxim,max77620.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77620 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77620_CLK_32K_OUT0		0
+
+/* Total number of clocks. */
+#define MAX77620_CLKS_NUM		(MAX77620_CLK_32K_OUT0 + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H */

include/dt-bindings/clock/maxim,max77686.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP		0
+#define MAX77686_CLK_CP		1
+#define MAX77686_CLK_PMIC	2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM		(MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */

include/dt-bindings/clock/maxim,max77802.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP		0
+#define MAX77802_CLK_32K_CP		1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */

include/dt-bindings/clock/maxim,max9485.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2018 Daniel Mack
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_MAX9485_CLK_H
+#define __DT_BINDINGS_MAX9485_CLK_H
+
+#define MAX9485_MCLKOUT	0
+#define MAX9485_CLKOUT	1
+#define MAX9485_CLKOUT1	2
+#define MAX9485_CLKOUT2	3
+
+#endif /* __DT_BINDINGS_MAX9485_CLK_H */

include/dt-bindings/clock/meson8b-clkc.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Meson8b clock tree IDs
+ */
+
+#ifndef __MESON8B_CLKC_H
+#define __MESON8B_CLKC_H
+
+#define CLKID_UNUSED		0
+#define CLKID_XTAL		1
+#define CLKID_PLL_FIXED		2
+#define CLKID_PLL_VID		3
+#define CLKID_PLL_SYS		4
+#define CLKID_FCLK_DIV2		5
+#define CLKID_FCLK_DIV3		6
+#define CLKID_FCLK_DIV4		7
+#define CLKID_FCLK_DIV5		8
+#define CLKID_FCLK_DIV7		9
+#define CLKID_CLK81		10
+#define CLKID_MALI		11
+#define CLKID_CPUCLK		12
+#define CLKID_ZERO		13
+#define CLKID_MPEG_SEL		14
+#define CLKID_MPEG_DIV		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_I2S_SPDIF		35
+#define CLKID_ETH		36
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE	71
+#define CLKID_CLK81_A9		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT	77
+#define CLKID_GCLK_VENCP_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCL_INT	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK2_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
+#define CLKID_MPLL0		93
+#define CLKID_MPLL1		94
+#define CLKID_MPLL2		95
+#define CLKID_NAND_CLK		112
+
+#endif /* __MESON8B_CLKC_H */

include/dt-bindings/clock/microchip,pic32-clock.h

@@ -0,0 +1,42 @@
+/*
+ * Purna Chandra Mandal,<purna.mandal@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+
+/* clock output indices */
+#define POSCCLK		0
+#define FRCCLK		1
+#define BFRCCLK		2
+#define LPRCCLK		3
+#define SOSCCLK		4
+#define FRCDIVCLK	5
+#define PLLCLK		6
+#define SCLK		7
+#define PB1CLK		8
+#define PB2CLK		9
+#define PB3CLK		10
+#define PB4CLK		11
+#define PB5CLK		12
+#define PB6CLK		13
+#define PB7CLK		14
+#define REF1CLK		15
+#define REF2CLK		16
+#define REF3CLK		17
+#define REF4CLK		18
+#define REF5CLK		19
+#define UPLLCLK		20
+#define MAXCLKS		21
+
+#endif	/* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */

include/dt-bindings/clock/mpc512x-clock.h

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY		0
+#define MPC512x_CLK_REF			1
+#define MPC512x_CLK_SYS			2
+#define MPC512x_CLK_DIU			3
+#define MPC512x_CLK_VIU			4
+#define MPC512x_CLK_CSB			5
+#define MPC512x_CLK_E300		6
+#define MPC512x_CLK_IPS			7
+#define MPC512x_CLK_FEC			8
+#define MPC512x_CLK_SATA		9
+#define MPC512x_CLK_PATA		10
+#define MPC512x_CLK_NFC			11
+#define MPC512x_CLK_LPC			12
+#define MPC512x_CLK_MBX_BUS		13
+#define MPC512x_CLK_MBX			14
+#define MPC512x_CLK_MBX_3D		15
+#define MPC512x_CLK_AXE			16
+#define MPC512x_CLK_USB1		17
+#define MPC512x_CLK_USB2		18
+#define MPC512x_CLK_I2C			19
+#define MPC512x_CLK_MSCAN0_MCLK		20
+#define MPC512x_CLK_MSCAN1_MCLK		21
+#define MPC512x_CLK_MSCAN2_MCLK		22
+#define MPC512x_CLK_MSCAN3_MCLK		23
+#define MPC512x_CLK_BDLC		24
+#define MPC512x_CLK_SDHC		25
+#define MPC512x_CLK_PCI			26
+#define MPC512x_CLK_PSC_MCLK_IN		27
+#define MPC512x_CLK_SPDIF_TX		28
+#define MPC512x_CLK_SPDIF_RX		29
+#define MPC512x_CLK_SPDIF_MCLK		30
+#define MPC512x_CLK_SPDIF		31
+#define MPC512x_CLK_AC97		32
+#define MPC512x_CLK_PSC0_MCLK		33
+#define MPC512x_CLK_PSC1_MCLK		34
+#define MPC512x_CLK_PSC2_MCLK		35
+#define MPC512x_CLK_PSC3_MCLK		36
+#define MPC512x_CLK_PSC4_MCLK		37
+#define MPC512x_CLK_PSC5_MCLK		38
+#define MPC512x_CLK_PSC6_MCLK		39
+#define MPC512x_CLK_PSC7_MCLK		40
+#define MPC512x_CLK_PSC8_MCLK		41
+#define MPC512x_CLK_PSC9_MCLK		42
+#define MPC512x_CLK_PSC10_MCLK		43
+#define MPC512x_CLK_PSC11_MCLK		44
+#define MPC512x_CLK_PSC_FIFO		45
+#define MPC512x_CLK_PSC0		46
+#define MPC512x_CLK_PSC1		47
+#define MPC512x_CLK_PSC2		48
+#define MPC512x_CLK_PSC3		49
+#define MPC512x_CLK_PSC4		50
+#define MPC512x_CLK_PSC5		51
+#define MPC512x_CLK_PSC6		52
+#define MPC512x_CLK_PSC7		53
+#define MPC512x_CLK_PSC8		54
+#define MPC512x_CLK_PSC9		55
+#define MPC512x_CLK_PSC10		56
+#define MPC512x_CLK_PSC11		57
+#define MPC512x_CLK_SDHC2		58
+#define MPC512x_CLK_FEC2		59
+#define MPC512x_CLK_OUT0_CLK		60
+#define MPC512x_CLK_OUT1_CLK		61
+#define MPC512x_CLK_OUT2_CLK		62
+#define MPC512x_CLK_OUT3_CLK		63
+#define MPC512x_CLK_CAN_CLK_IN		64
+
+#define MPC512x_CLK_LAST_PUBLIC		64
+
+#endif

include/dt-bindings/clock/mt2701-clk.h

@@ -0,0 +1,492 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2701_H
+#define _DT_BINDINGS_CLK_MT2701_H
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL				1
+#define CLK_TOP_SYSPLL_D2			2
+#define CLK_TOP_SYSPLL_D3			3
+#define CLK_TOP_SYSPLL_D5			4
+#define CLK_TOP_SYSPLL_D7			5
+#define CLK_TOP_SYSPLL1_D2			6
+#define CLK_TOP_SYSPLL1_D4			7
+#define CLK_TOP_SYSPLL1_D8			8
+#define CLK_TOP_SYSPLL1_D16			9
+#define CLK_TOP_SYSPLL2_D2			10
+#define CLK_TOP_SYSPLL2_D4			11
+#define CLK_TOP_SYSPLL2_D8			12
+#define CLK_TOP_SYSPLL3_D2			13
+#define CLK_TOP_SYSPLL3_D4			14
+#define CLK_TOP_SYSPLL4_D2			15
+#define CLK_TOP_SYSPLL4_D4			16
+#define CLK_TOP_UNIVPLL				17
+#define CLK_TOP_UNIVPLL_D2			18
+#define CLK_TOP_UNIVPLL_D3			19
+#define CLK_TOP_UNIVPLL_D5			20
+#define CLK_TOP_UNIVPLL_D7			21
+#define CLK_TOP_UNIVPLL_D26			22
+#define CLK_TOP_UNIVPLL_D52			23
+#define CLK_TOP_UNIVPLL_D108			24
+#define CLK_TOP_USB_PHY48M			25
+#define CLK_TOP_UNIVPLL1_D2			26
+#define CLK_TOP_UNIVPLL1_D4			27
+#define CLK_TOP_UNIVPLL1_D8			28
+#define CLK_TOP_UNIVPLL2_D2			29
+#define CLK_TOP_UNIVPLL2_D4			30
+#define CLK_TOP_UNIVPLL2_D8			31
+#define CLK_TOP_UNIVPLL2_D16			32
+#define CLK_TOP_UNIVPLL2_D32			33
+#define CLK_TOP_UNIVPLL3_D2			34
+#define CLK_TOP_UNIVPLL3_D4			35
+#define CLK_TOP_UNIVPLL3_D8			36
+#define CLK_TOP_MSDCPLL				37
+#define CLK_TOP_MSDCPLL_D2			38
+#define CLK_TOP_MSDCPLL_D4			39
+#define CLK_TOP_MSDCPLL_D8			40
+#define CLK_TOP_MMPLL				41
+#define CLK_TOP_MMPLL_D2			42
+#define CLK_TOP_DMPLL				43
+#define CLK_TOP_DMPLL_D2			44
+#define CLK_TOP_DMPLL_D4			45
+#define CLK_TOP_DMPLL_X2			46
+#define CLK_TOP_TVDPLL				47
+#define CLK_TOP_TVDPLL_D2			48
+#define CLK_TOP_TVDPLL_D4			49
+#define CLK_TOP_TVD2PLL				50
+#define CLK_TOP_TVD2PLL_D2			51
+#define CLK_TOP_HADDS2PLL_98M			52
+#define CLK_TOP_HADDS2PLL_294M			53
+#define CLK_TOP_HADDS2_FB			54
+#define CLK_TOP_MIPIPLL_D2			55
+#define CLK_TOP_MIPIPLL_D4			56
+#define CLK_TOP_HDMIPLL				57
+#define CLK_TOP_HDMIPLL_D2			58
+#define CLK_TOP_HDMIPLL_D3			59
+#define CLK_TOP_HDMI_SCL_RX			60
+#define CLK_TOP_HDMI_0_PIX340M			61
+#define CLK_TOP_HDMI_0_DEEP340M			62
+#define CLK_TOP_HDMI_0_PLL340M			63
+#define CLK_TOP_AUD1PLL_98M			64
+#define CLK_TOP_AUD2PLL_90M			65
+#define CLK_TOP_AUDPLL				66
+#define CLK_TOP_AUDPLL_D4			67
+#define CLK_TOP_AUDPLL_D8			68
+#define CLK_TOP_AUDPLL_D16			69
+#define CLK_TOP_AUDPLL_D24			70
+#define CLK_TOP_ETHPLL_500M			71
+#define CLK_TOP_VDECPLL				72
+#define CLK_TOP_VENCPLL				73
+#define CLK_TOP_MIPIPLL				74
+#define CLK_TOP_ARMPLL_1P3G			75
+
+#define CLK_TOP_MM_SEL				76
+#define CLK_TOP_DDRPHYCFG_SEL			77
+#define CLK_TOP_MEM_SEL				78
+#define CLK_TOP_AXI_SEL				79
+#define CLK_TOP_CAMTG_SEL			80
+#define CLK_TOP_MFG_SEL				81
+#define CLK_TOP_VDEC_SEL			82
+#define CLK_TOP_PWM_SEL				83
+#define CLK_TOP_MSDC30_0_SEL			84
+#define CLK_TOP_USB20_SEL			85
+#define CLK_TOP_SPI0_SEL			86
+#define CLK_TOP_UART_SEL			87
+#define CLK_TOP_AUDINTBUS_SEL			88
+#define CLK_TOP_AUDIO_SEL			89
+#define CLK_TOP_MSDC30_2_SEL			90
+#define CLK_TOP_MSDC30_1_SEL			91
+#define CLK_TOP_DPI1_SEL			92
+#define CLK_TOP_DPI0_SEL			93
+#define CLK_TOP_SCP_SEL				94
+#define CLK_TOP_PMICSPI_SEL			95
+#define CLK_TOP_APLL_SEL			96
+#define CLK_TOP_HDMI_SEL			97
+#define CLK_TOP_TVE_SEL				98
+#define CLK_TOP_EMMC_HCLK_SEL			99
+#define CLK_TOP_NFI2X_SEL			100
+#define CLK_TOP_RTC_SEL				101
+#define CLK_TOP_OSD_SEL				102
+#define CLK_TOP_NR_SEL				103
+#define CLK_TOP_DI_SEL				104
+#define CLK_TOP_FLASH_SEL			105
+#define CLK_TOP_ASM_M_SEL			106
+#define CLK_TOP_ASM_I_SEL			107
+#define CLK_TOP_INTDIR_SEL			108
+#define CLK_TOP_HDMIRX_BIST_SEL			109
+#define CLK_TOP_ETHIF_SEL			110
+#define CLK_TOP_MS_CARD_SEL			111
+#define CLK_TOP_ASM_H_SEL			112
+#define CLK_TOP_SPI1_SEL			113
+#define CLK_TOP_CMSYS_SEL			114
+#define CLK_TOP_MSDC30_3_SEL			115
+#define CLK_TOP_HDMIRX26_24_SEL			116
+#define CLK_TOP_AUD2DVD_SEL			117
+#define CLK_TOP_8BDAC_SEL			118
+#define CLK_TOP_SPI2_SEL			119
+#define CLK_TOP_AUD_MUX1_SEL			120
+#define CLK_TOP_AUD_MUX2_SEL			121
+#define CLK_TOP_AUDPLL_MUX_SEL			122
+#define CLK_TOP_AUD_K1_SRC_SEL			123
+#define CLK_TOP_AUD_K2_SRC_SEL			124
+#define CLK_TOP_AUD_K3_SRC_SEL			125
+#define CLK_TOP_AUD_K4_SRC_SEL			126
+#define CLK_TOP_AUD_K5_SRC_SEL			127
+#define CLK_TOP_AUD_K6_SRC_SEL			128
+#define CLK_TOP_PADMCLK_SEL			129
+#define CLK_TOP_AUD_EXTCK1_DIV			130
+#define CLK_TOP_AUD_EXTCK2_DIV			131
+#define CLK_TOP_AUD_MUX1_DIV			132
+#define CLK_TOP_AUD_MUX2_DIV			133
+#define CLK_TOP_AUD_K1_SRC_DIV			134
+#define CLK_TOP_AUD_K2_SRC_DIV			135
+#define CLK_TOP_AUD_K3_SRC_DIV			136
+#define CLK_TOP_AUD_K4_SRC_DIV			137
+#define CLK_TOP_AUD_K5_SRC_DIV			138
+#define CLK_TOP_AUD_K6_SRC_DIV			139
+#define CLK_TOP_AUD_I2S1_MCLK			140
+#define CLK_TOP_AUD_I2S2_MCLK			141
+#define CLK_TOP_AUD_I2S3_MCLK			142
+#define CLK_TOP_AUD_I2S4_MCLK			143
+#define CLK_TOP_AUD_I2S5_MCLK			144
+#define CLK_TOP_AUD_I2S6_MCLK			145
+#define CLK_TOP_AUD_48K_TIMING			146
+#define CLK_TOP_AUD_44K_TIMING			147
+
+#define CLK_TOP_32K_INTERNAL			148
+#define CLK_TOP_32K_EXTERNAL			149
+#define CLK_TOP_CLK26M_D8			150
+#define CLK_TOP_8BDAC				151
+#define CLK_TOP_WBG_DIG_416M			152
+#define CLK_TOP_DPI				153
+#define CLK_TOP_DSI0_LNTC_DSI			154
+#define CLK_TOP_AUD_EXT1			155
+#define CLK_TOP_AUD_EXT2			156
+#define CLK_TOP_NFI1X_PAD			157
+#define CLK_TOP_AXISEL_D4			158
+#define CLK_TOP_NR				159
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL			1
+#define CLK_APMIXED_MAINPLL			2
+#define CLK_APMIXED_UNIVPLL			3
+#define CLK_APMIXED_MMPLL			4
+#define CLK_APMIXED_MSDCPLL			5
+#define CLK_APMIXED_TVDPLL			6
+#define CLK_APMIXED_AUD1PLL			7
+#define CLK_APMIXED_TRGPLL			8
+#define CLK_APMIXED_ETHPLL			9
+#define CLK_APMIXED_VDECPLL			10
+#define CLK_APMIXED_HADDS2PLL			11
+#define CLK_APMIXED_AUD2PLL			12
+#define CLK_APMIXED_TVD2PLL			13
+#define CLK_APMIXED_HDMI_REF			14
+#define CLK_APMIXED_NR				15
+
+/* DDRPHY */
+
+#define CLK_DDRPHY_VENCPLL			1
+#define CLK_DDRPHY_NR				2
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBG				1
+#define CLK_INFRA_SMI				2
+#define CLK_INFRA_QAXI_CM4			3
+#define CLK_INFRA_AUD_SPLIN_B			4
+#define CLK_INFRA_AUDIO				5
+#define CLK_INFRA_EFUSE				6
+#define CLK_INFRA_L2C_SRAM			7
+#define CLK_INFRA_M4U				8
+#define CLK_INFRA_CONNMCU			9
+#define CLK_INFRA_TRNG				10
+#define CLK_INFRA_RAMBUFIF			11
+#define CLK_INFRA_CPUM				12
+#define CLK_INFRA_KP				13
+#define CLK_INFRA_CEC				14
+#define CLK_INFRA_IRRX				15
+#define CLK_INFRA_PMICSPI			16
+#define CLK_INFRA_PMICWRAP			17
+#define CLK_INFRA_DDCCI				18
+#define CLK_INFRA_CLK_13M			19
+#define CLK_INFRA_CPUSEL                        20
+#define CLK_INFRA_NR				21
+
+/* PERICFG */
+
+#define CLK_PERI_NFI				1
+#define CLK_PERI_THERM				2
+#define CLK_PERI_PWM1				3
+#define CLK_PERI_PWM2				4
+#define CLK_PERI_PWM3				5
+#define CLK_PERI_PWM4				6
+#define CLK_PERI_PWM5				7
+#define CLK_PERI_PWM6				8
+#define CLK_PERI_PWM7				9
+#define CLK_PERI_PWM				10
+#define CLK_PERI_USB0				11
+#define CLK_PERI_USB1				12
+#define CLK_PERI_AP_DMA				13
+#define CLK_PERI_MSDC30_0			14
+#define CLK_PERI_MSDC30_1			15
+#define CLK_PERI_MSDC30_2			16
+#define CLK_PERI_MSDC30_3			17
+#define CLK_PERI_MSDC50_3			18
+#define CLK_PERI_NLI				19
+#define CLK_PERI_UART0				20
+#define CLK_PERI_UART1				21
+#define CLK_PERI_UART2				22
+#define CLK_PERI_UART3				23
+#define CLK_PERI_BTIF				24
+#define CLK_PERI_I2C0				25
+#define CLK_PERI_I2C1				26
+#define CLK_PERI_I2C2				27
+#define CLK_PERI_I2C3				28
+#define CLK_PERI_AUXADC				29
+#define CLK_PERI_SPI0				30
+#define CLK_PERI_ETH				31
+#define CLK_PERI_USB0_MCU			32
+
+#define CLK_PERI_USB1_MCU			33
+#define CLK_PERI_USB_SLV			34
+#define CLK_PERI_GCPU				35
+#define CLK_PERI_NFI_ECC			36
+#define CLK_PERI_NFI_PAD			37
+#define CLK_PERI_FLASH				38
+#define CLK_PERI_HOST89_INT			39
+#define CLK_PERI_HOST89_SPI			40
+#define CLK_PERI_HOST89_DVD			41
+#define CLK_PERI_SPI1				42
+#define CLK_PERI_SPI2				43
+#define CLK_PERI_FCI				44
+
+#define CLK_PERI_UART0_SEL			45
+#define CLK_PERI_UART1_SEL			46
+#define CLK_PERI_UART2_SEL			47
+#define CLK_PERI_UART3_SEL			48
+#define CLK_PERI_NR				49
+
+/* AUDIO */
+
+#define CLK_AUD_AFE				1
+#define CLK_AUD_LRCK_DETECT			2
+#define CLK_AUD_I2S				3
+#define CLK_AUD_APLL_TUNER			4
+#define CLK_AUD_HDMI				5
+#define CLK_AUD_SPDF				6
+#define CLK_AUD_SPDF2				7
+#define CLK_AUD_APLL				8
+#define CLK_AUD_TML				9
+#define CLK_AUD_AHB_IDLE_EXT			10
+#define CLK_AUD_AHB_IDLE_INT			11
+
+#define CLK_AUD_I2SIN1				12
+#define CLK_AUD_I2SIN2				13
+#define CLK_AUD_I2SIN3				14
+#define CLK_AUD_I2SIN4				15
+#define CLK_AUD_I2SIN5				16
+#define CLK_AUD_I2SIN6				17
+#define CLK_AUD_I2SO1				18
+#define CLK_AUD_I2SO2				19
+#define CLK_AUD_I2SO3				20
+#define CLK_AUD_I2SO4				21
+#define CLK_AUD_I2SO5				22
+#define CLK_AUD_I2SO6				23
+#define CLK_AUD_ASRCI1				24
+#define CLK_AUD_ASRCI2				25
+#define CLK_AUD_ASRCO1				26
+#define CLK_AUD_ASRCO2				27
+#define CLK_AUD_ASRC11				28
+#define CLK_AUD_ASRC12				29
+#define CLK_AUD_HDMIRX				30
+#define CLK_AUD_INTDIR				31
+#define CLK_AUD_A1SYS				32
+#define CLK_AUD_A2SYS				33
+#define CLK_AUD_AFE_CONN			34
+#define CLK_AUD_AFE_PCMIF			35
+#define CLK_AUD_AFE_MRGIF			36
+
+#define CLK_AUD_MMIF_UL1			37
+#define CLK_AUD_MMIF_UL2			38
+#define CLK_AUD_MMIF_UL3			39
+#define CLK_AUD_MMIF_UL4			40
+#define CLK_AUD_MMIF_UL5			41
+#define CLK_AUD_MMIF_UL6			42
+#define CLK_AUD_MMIF_DL1			43
+#define CLK_AUD_MMIF_DL2			44
+#define CLK_AUD_MMIF_DL3			45
+#define CLK_AUD_MMIF_DL4			46
+#define CLK_AUD_MMIF_DL5			47
+#define CLK_AUD_MMIF_DL6			48
+#define CLK_AUD_MMIF_DLMCH			49
+#define CLK_AUD_MMIF_ARB1			50
+#define CLK_AUD_MMIF_AWB1			51
+#define CLK_AUD_MMIF_AWB2			52
+#define CLK_AUD_MMIF_DAI			53
+
+#define CLK_AUD_DMIC1				54
+#define CLK_AUD_DMIC2				55
+#define CLK_AUD_ASRCI3				56
+#define CLK_AUD_ASRCI4				57
+#define CLK_AUD_ASRCI5				58
+#define CLK_AUD_ASRCI6				59
+#define CLK_AUD_ASRCO3				60
+#define CLK_AUD_ASRCO4				61
+#define CLK_AUD_ASRCO5				62
+#define CLK_AUD_ASRCO6				63
+#define CLK_AUD_MEM_ASRC1			64
+#define CLK_AUD_MEM_ASRC2			65
+#define CLK_AUD_MEM_ASRC3			66
+#define CLK_AUD_MEM_ASRC4			67
+#define CLK_AUD_MEM_ASRC5			68
+#define CLK_AUD_DSD_ENC				69
+#define CLK_AUD_ASRC_BRG			70
+#define CLK_AUD_NR				71
+
+/* MMSYS */
+
+#define CLK_MM_SMI_COMMON			1
+#define CLK_MM_SMI_LARB0			2
+#define CLK_MM_CMDQ				3
+#define CLK_MM_MUTEX				4
+#define CLK_MM_DISP_COLOR			5
+#define CLK_MM_DISP_BLS				6
+#define CLK_MM_DISP_WDMA			7
+#define CLK_MM_DISP_RDMA			8
+#define CLK_MM_DISP_OVL				9
+#define CLK_MM_MDP_TDSHP			10
+#define CLK_MM_MDP_WROT				11
+#define CLK_MM_MDP_WDMA				12
+#define CLK_MM_MDP_RSZ1				13
+#define CLK_MM_MDP_RSZ0				14
+#define CLK_MM_MDP_RDMA				15
+#define CLK_MM_MDP_BLS_26M			16
+#define CLK_MM_CAM_MDP				17
+#define CLK_MM_FAKE_ENG				18
+#define CLK_MM_MUTEX_32K			19
+#define CLK_MM_DISP_RDMA1			20
+#define CLK_MM_DISP_UFOE			21
+
+#define CLK_MM_DSI_ENGINE			22
+#define CLK_MM_DSI_DIG				23
+#define CLK_MM_DPI_DIGL				24
+#define CLK_MM_DPI_ENGINE			25
+#define CLK_MM_DPI1_DIGL			26
+#define CLK_MM_DPI1_ENGINE			27
+#define CLK_MM_TVE_OUTPUT			28
+#define CLK_MM_TVE_INPUT			29
+#define CLK_MM_HDMI_PIXEL			30
+#define CLK_MM_HDMI_PLL				31
+#define CLK_MM_HDMI_AUDIO			32
+#define CLK_MM_HDMI_SPDIF			33
+#define CLK_MM_TVE_FMM				34
+#define CLK_MM_NR				35
+
+/* IMGSYS */
+
+#define CLK_IMG_SMI_COMM			1
+#define CLK_IMG_RESZ				2
+#define CLK_IMG_JPGDEC_SMI			3
+#define CLK_IMG_JPGDEC				4
+#define CLK_IMG_VENC_LT				5
+#define CLK_IMG_VENC				6
+#define CLK_IMG_NR				7
+
+/* VDEC */
+
+#define CLK_VDEC_CKGEN				1
+#define CLK_VDEC_LARB				2
+#define CLK_VDEC_NR				3
+
+/* HIFSYS */
+
+#define CLK_HIFSYS_USB0PHY			1
+#define CLK_HIFSYS_USB1PHY			2
+#define CLK_HIFSYS_PCIE0			3
+#define CLK_HIFSYS_PCIE1			4
+#define CLK_HIFSYS_PCIE2			5
+#define CLK_HIFSYS_NR				6
+
+/* ETHSYS */
+#define CLK_ETHSYS_HSDMA			1
+#define CLK_ETHSYS_ESW				2
+#define CLK_ETHSYS_GP2				3
+#define CLK_ETHSYS_GP1				4
+#define CLK_ETHSYS_PCM				5
+#define CLK_ETHSYS_GDMA				6
+#define CLK_ETHSYS_I2S				7
+#define CLK_ETHSYS_CRYPTO			8
+#define CLK_ETHSYS_NR				9
+
+/* G3DSYS */
+#define CLK_G3DSYS_CORE				1
+#define CLK_G3DSYS_NR				2
+
+/* BDP */
+
+#define CLK_BDP_BRG_BA				1
+#define CLK_BDP_BRG_DRAM			2
+#define CLK_BDP_LARB_DRAM			3
+#define CLK_BDP_WR_VDI_PXL			4
+#define CLK_BDP_WR_VDI_DRAM			5
+#define CLK_BDP_WR_B				6
+#define CLK_BDP_DGI_IN				7
+#define CLK_BDP_DGI_OUT				8
+#define CLK_BDP_FMT_MAST_27			9
+#define CLK_BDP_FMT_B				10
+#define CLK_BDP_OSD_B				11
+#define CLK_BDP_OSD_DRAM			12
+#define CLK_BDP_OSD_AGENT			13
+#define CLK_BDP_OSD_PXL				14
+#define CLK_BDP_RLE_B				15
+#define CLK_BDP_RLE_AGENT			16
+#define CLK_BDP_RLE_DRAM			17
+#define CLK_BDP_F27M				18
+#define CLK_BDP_F27M_VDOUT			19
+#define CLK_BDP_F27_74_74			20
+#define CLK_BDP_F2FS				21
+#define CLK_BDP_F2FS74_148			22
+#define CLK_BDP_FB				23
+#define CLK_BDP_VDO_DRAM			24
+#define CLK_BDP_VDO_2FS				25
+#define CLK_BDP_VDO_B				26
+#define CLK_BDP_WR_DI_PXL			27
+#define CLK_BDP_WR_DI_DRAM			28
+#define CLK_BDP_WR_DI_B				29
+#define CLK_BDP_NR_PXL				30
+#define CLK_BDP_NR_DRAM				31
+#define CLK_BDP_NR_B				32
+
+#define CLK_BDP_RX_F				33
+#define CLK_BDP_RX_X				34
+#define CLK_BDP_RXPDT				35
+#define CLK_BDP_RX_CSCL_N			36
+#define CLK_BDP_RX_CSCL				37
+#define CLK_BDP_RX_DDCSCL_N			38
+#define CLK_BDP_RX_DDCSCL			39
+#define CLK_BDP_RX_VCO				40
+#define CLK_BDP_RX_DP				41
+#define CLK_BDP_RX_P				42
+#define CLK_BDP_RX_M				43
+#define CLK_BDP_RX_PLL				44
+#define CLK_BDP_BRG_RT_B			45
+#define CLK_BDP_BRG_RT_DRAM			46
+#define CLK_BDP_LARBRT_DRAM			47
+#define CLK_BDP_TMDS_SYN			48
+#define CLK_BDP_HDMI_MON			49
+#define CLK_BDP_NR				50
+
+#endif /* _DT_BINDINGS_CLK_MT2701_H */

include/dt-bindings/clock/mt2712-clk.h

@@ -0,0 +1,438 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2712_H
+#define _DT_BINDINGS_CLK_MT2712_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_MAINPLL		0
+#define CLK_APMIXED_UNIVPLL		1
+#define CLK_APMIXED_VCODECPLL		2
+#define CLK_APMIXED_VENCPLL		3
+#define CLK_APMIXED_APLL1		4
+#define CLK_APMIXED_APLL2		5
+#define CLK_APMIXED_LVDSPLL		6
+#define CLK_APMIXED_LVDSPLL2		7
+#define CLK_APMIXED_MSDCPLL		8
+#define CLK_APMIXED_MSDCPLL2		9
+#define CLK_APMIXED_TVDPLL		10
+#define CLK_APMIXED_MMPLL		11
+#define CLK_APMIXED_ARMCA35PLL		12
+#define CLK_APMIXED_ARMCA72PLL		13
+#define CLK_APMIXED_ETHERPLL		14
+#define CLK_APMIXED_NR_CLK		15
+
+/* TOPCKGEN */
+
+#define CLK_TOP_ARMCA35PLL		0
+#define CLK_TOP_ARMCA35PLL_600M		1
+#define CLK_TOP_ARMCA35PLL_400M		2
+#define CLK_TOP_ARMCA72PLL		3
+#define CLK_TOP_SYSPLL			4
+#define CLK_TOP_SYSPLL_D2		5
+#define CLK_TOP_SYSPLL1_D2		6
+#define CLK_TOP_SYSPLL1_D4		7
+#define CLK_TOP_SYSPLL1_D8		8
+#define CLK_TOP_SYSPLL1_D16		9
+#define CLK_TOP_SYSPLL_D3		10
+#define CLK_TOP_SYSPLL2_D2		11
+#define CLK_TOP_SYSPLL2_D4		12
+#define CLK_TOP_SYSPLL_D5		13
+#define CLK_TOP_SYSPLL3_D2		14
+#define CLK_TOP_SYSPLL3_D4		15
+#define CLK_TOP_SYSPLL_D7		16
+#define CLK_TOP_SYSPLL4_D2		17
+#define CLK_TOP_SYSPLL4_D4		18
+#define CLK_TOP_UNIVPLL			19
+#define CLK_TOP_UNIVPLL_D7		20
+#define CLK_TOP_UNIVPLL_D26		21
+#define CLK_TOP_UNIVPLL_D52		22
+#define CLK_TOP_UNIVPLL_D104		23
+#define CLK_TOP_UNIVPLL_D208		24
+#define CLK_TOP_UNIVPLL_D2		25
+#define CLK_TOP_UNIVPLL1_D2		26
+#define CLK_TOP_UNIVPLL1_D4		27
+#define CLK_TOP_UNIVPLL1_D8		28
+#define CLK_TOP_UNIVPLL_D3		29
+#define CLK_TOP_UNIVPLL2_D2		30
+#define CLK_TOP_UNIVPLL2_D4		31
+#define CLK_TOP_UNIVPLL2_D8		32
+#define CLK_TOP_UNIVPLL_D5		33
+#define CLK_TOP_UNIVPLL3_D2		34
+#define CLK_TOP_UNIVPLL3_D4		35
+#define CLK_TOP_UNIVPLL3_D8		36
+#define CLK_TOP_F_MP0_PLL1		37
+#define CLK_TOP_F_MP0_PLL2		38
+#define CLK_TOP_F_BIG_PLL1		39
+#define CLK_TOP_F_BIG_PLL2		40
+#define CLK_TOP_F_BUS_PLL1		41
+#define CLK_TOP_F_BUS_PLL2		42
+#define CLK_TOP_APLL1			43
+#define CLK_TOP_APLL1_D2		44
+#define CLK_TOP_APLL1_D4		45
+#define CLK_TOP_APLL1_D8		46
+#define CLK_TOP_APLL1_D16		47
+#define CLK_TOP_APLL2			48
+#define CLK_TOP_APLL2_D2		49
+#define CLK_TOP_APLL2_D4		50
+#define CLK_TOP_APLL2_D8		51
+#define CLK_TOP_APLL2_D16		52
+#define CLK_TOP_LVDSPLL			53
+#define CLK_TOP_LVDSPLL_D2		54
+#define CLK_TOP_LVDSPLL_D4		55
+#define CLK_TOP_LVDSPLL_D8		56
+#define CLK_TOP_LVDSPLL2		57
+#define CLK_TOP_LVDSPLL2_D2		58
+#define CLK_TOP_LVDSPLL2_D4		59
+#define CLK_TOP_LVDSPLL2_D8		60
+#define CLK_TOP_ETHERPLL_125M		61
+#define CLK_TOP_ETHERPLL_50M		62
+#define CLK_TOP_CVBS			63
+#define CLK_TOP_CVBS_D2			64
+#define CLK_TOP_SYS_26M			65
+#define CLK_TOP_MMPLL			66
+#define CLK_TOP_MMPLL_D2		67
+#define CLK_TOP_VENCPLL			68
+#define CLK_TOP_VENCPLL_D2		69
+#define CLK_TOP_VCODECPLL		70
+#define CLK_TOP_VCODECPLL_D2		71
+#define CLK_TOP_TVDPLL			72
+#define CLK_TOP_TVDPLL_D2		73
+#define CLK_TOP_TVDPLL_D4		74
+#define CLK_TOP_TVDPLL_D8		75
+#define CLK_TOP_TVDPLL_429M		76
+#define CLK_TOP_TVDPLL_429M_D2		77
+#define CLK_TOP_TVDPLL_429M_D4		78
+#define CLK_TOP_MSDCPLL			79
+#define CLK_TOP_MSDCPLL_D2		80
+#define CLK_TOP_MSDCPLL_D4		81
+#define CLK_TOP_MSDCPLL2		82
+#define CLK_TOP_MSDCPLL2_D2		83
+#define CLK_TOP_MSDCPLL2_D4		84
+#define CLK_TOP_CLK26M_D2		85
+#define CLK_TOP_D2A_ULCLK_6P5M		86
+#define CLK_TOP_VPLL3_DPIX		87
+#define CLK_TOP_VPLL_DPIX		88
+#define CLK_TOP_LTEPLL_FS26M		89
+#define CLK_TOP_DMPLL			90
+#define CLK_TOP_DSI0_LNTC		91
+#define CLK_TOP_DSI1_LNTC		92
+#define CLK_TOP_LVDSTX3_CLKDIG_CTS	93
+#define CLK_TOP_LVDSTX_CLKDIG_CTS	94
+#define CLK_TOP_CLKRTC_EXT		95
+#define CLK_TOP_CLKRTC_INT		96
+#define CLK_TOP_CSI0			97
+#define CLK_TOP_CVBSPLL			98
+#define CLK_TOP_AXI_SEL			99
+#define CLK_TOP_MEM_SEL			100
+#define CLK_TOP_MM_SEL			101
+#define CLK_TOP_PWM_SEL			102
+#define CLK_TOP_VDEC_SEL		103
+#define CLK_TOP_VENC_SEL		104
+#define CLK_TOP_MFG_SEL			105
+#define CLK_TOP_CAMTG_SEL		106
+#define CLK_TOP_UART_SEL		107
+#define CLK_TOP_SPI_SEL			108
+#define CLK_TOP_USB20_SEL		109
+#define CLK_TOP_USB30_SEL		110
+#define CLK_TOP_MSDC50_0_HCLK_SEL	111
+#define CLK_TOP_MSDC50_0_SEL		112
+#define CLK_TOP_MSDC30_1_SEL		113
+#define CLK_TOP_MSDC30_2_SEL		114
+#define CLK_TOP_MSDC30_3_SEL		115
+#define CLK_TOP_AUDIO_SEL		116
+#define CLK_TOP_AUD_INTBUS_SEL		117
+#define CLK_TOP_PMICSPI_SEL		118
+#define CLK_TOP_DPILVDS1_SEL		119
+#define CLK_TOP_ATB_SEL			120
+#define CLK_TOP_NR_SEL			121
+#define CLK_TOP_NFI2X_SEL		122
+#define CLK_TOP_IRDA_SEL		123
+#define CLK_TOP_CCI400_SEL		124
+#define CLK_TOP_AUD_1_SEL		125
+#define CLK_TOP_AUD_2_SEL		126
+#define CLK_TOP_MEM_MFG_IN_AS_SEL	127
+#define CLK_TOP_AXI_MFG_IN_AS_SEL	128
+#define CLK_TOP_SCAM_SEL		129
+#define CLK_TOP_NFIECC_SEL		130
+#define CLK_TOP_PE2_MAC_P0_SEL		131
+#define CLK_TOP_PE2_MAC_P1_SEL		132
+#define CLK_TOP_DPILVDS_SEL		133
+#define CLK_TOP_MSDC50_3_HCLK_SEL	134
+#define CLK_TOP_HDCP_SEL		135
+#define CLK_TOP_HDCP_24M_SEL		136
+#define CLK_TOP_RTC_SEL			137
+#define CLK_TOP_SPINOR_SEL		138
+#define CLK_TOP_APLL_SEL		139
+#define CLK_TOP_APLL2_SEL		140
+#define CLK_TOP_A1SYS_HP_SEL		141
+#define CLK_TOP_A2SYS_HP_SEL		142
+#define CLK_TOP_ASM_L_SEL		143
+#define CLK_TOP_ASM_M_SEL		144
+#define CLK_TOP_ASM_H_SEL		145
+#define CLK_TOP_I2SO1_SEL		146
+#define CLK_TOP_I2SO2_SEL		147
+#define CLK_TOP_I2SO3_SEL		148
+#define CLK_TOP_TDMO0_SEL		149
+#define CLK_TOP_TDMO1_SEL		150
+#define CLK_TOP_I2SI1_SEL		151
+#define CLK_TOP_I2SI2_SEL		152
+#define CLK_TOP_I2SI3_SEL		153
+#define CLK_TOP_ETHER_125M_SEL		154
+#define CLK_TOP_ETHER_50M_SEL		155
+#define CLK_TOP_JPGDEC_SEL		156
+#define CLK_TOP_SPISLV_SEL		157
+#define CLK_TOP_ETHER_50M_RMII_SEL	158
+#define CLK_TOP_CAM2TG_SEL		159
+#define CLK_TOP_DI_SEL			160
+#define CLK_TOP_TVD_SEL			161
+#define CLK_TOP_I2C_SEL			162
+#define CLK_TOP_PWM_INFRA_SEL		163
+#define CLK_TOP_MSDC0P_AES_SEL		164
+#define CLK_TOP_CMSYS_SEL		165
+#define CLK_TOP_GCPU_SEL		166
+#define CLK_TOP_AUD_APLL1_SEL		167
+#define CLK_TOP_AUD_APLL2_SEL		168
+#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL	169
+#define CLK_TOP_APLL_DIV0		170
+#define CLK_TOP_APLL_DIV1		171
+#define CLK_TOP_APLL_DIV2		172
+#define CLK_TOP_APLL_DIV3		173
+#define CLK_TOP_APLL_DIV4		174
+#define CLK_TOP_APLL_DIV5		175
+#define CLK_TOP_APLL_DIV6		176
+#define CLK_TOP_APLL_DIV7		177
+#define CLK_TOP_APLL_DIV_PDN0		178
+#define CLK_TOP_APLL_DIV_PDN1		179
+#define CLK_TOP_APLL_DIV_PDN2		180
+#define CLK_TOP_APLL_DIV_PDN3		181
+#define CLK_TOP_APLL_DIV_PDN4		182
+#define CLK_TOP_APLL_DIV_PDN5		183
+#define CLK_TOP_APLL_DIV_PDN6		184
+#define CLK_TOP_APLL_DIV_PDN7		185
+#define CLK_TOP_APLL1_D3		186
+#define CLK_TOP_APLL1_REF_SEL		187
+#define CLK_TOP_APLL2_REF_SEL		188
+#define CLK_TOP_NFI2X_EN		189
+#define CLK_TOP_NFIECC_EN		190
+#define CLK_TOP_NFI1X_CK_EN		191
+#define CLK_TOP_APLL2_D3		192
+#define CLK_TOP_NR_CLK			193
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBGCLK		0
+#define CLK_INFRA_GCE			1
+#define CLK_INFRA_M4U			2
+#define CLK_INFRA_KP			3
+#define CLK_INFRA_AO_SPI0		4
+#define CLK_INFRA_AO_SPI1		5
+#define CLK_INFRA_AO_UART5		6
+#define CLK_INFRA_NR_CLK		7
+
+/* PERICFG */
+
+#define CLK_PERI_NFI			0
+#define CLK_PERI_THERM			1
+#define CLK_PERI_PWM0			2
+#define CLK_PERI_PWM1			3
+#define CLK_PERI_PWM2			4
+#define CLK_PERI_PWM3			5
+#define CLK_PERI_PWM4			6
+#define CLK_PERI_PWM5			7
+#define CLK_PERI_PWM6			8
+#define CLK_PERI_PWM7			9
+#define CLK_PERI_PWM			10
+#define CLK_PERI_AP_DMA			11
+#define CLK_PERI_MSDC30_0		12
+#define CLK_PERI_MSDC30_1		13
+#define CLK_PERI_MSDC30_2		14
+#define CLK_PERI_MSDC30_3		15
+#define CLK_PERI_UART0			16
+#define CLK_PERI_UART1			17
+#define CLK_PERI_UART2			18
+#define CLK_PERI_UART3			19
+#define CLK_PERI_I2C0			20
+#define CLK_PERI_I2C1			21
+#define CLK_PERI_I2C2			22
+#define CLK_PERI_I2C3			23
+#define CLK_PERI_I2C4			24
+#define CLK_PERI_AUXADC			25
+#define CLK_PERI_SPI0			26
+#define CLK_PERI_SPI			27
+#define CLK_PERI_I2C5			28
+#define CLK_PERI_SPI2			29
+#define CLK_PERI_SPI3			30
+#define CLK_PERI_SPI5			31
+#define CLK_PERI_UART4			32
+#define CLK_PERI_SFLASH			33
+#define CLK_PERI_GMAC			34
+#define CLK_PERI_PCIE0			35
+#define CLK_PERI_PCIE1			36
+#define CLK_PERI_GMAC_PCLK		37
+#define CLK_PERI_MSDC50_0_EN		38
+#define CLK_PERI_MSDC30_1_EN		39
+#define CLK_PERI_MSDC30_2_EN		40
+#define CLK_PERI_MSDC30_3_EN		41
+#define CLK_PERI_MSDC50_0_HCLK_EN	42
+#define CLK_PERI_MSDC50_3_HCLK_EN	43
+#define CLK_PERI_MSDC30_0_QTR_EN	44
+#define CLK_PERI_MSDC30_3_QTR_EN	45
+#define CLK_PERI_NR_CLK			46
+
+/* MCUCFG */
+
+#define CLK_MCU_MP0_SEL			0
+#define CLK_MCU_MP2_SEL			1
+#define CLK_MCU_BUS_SEL			2
+#define CLK_MCU_NR_CLK			3
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D			0
+#define CLK_MFG_NR_CLK			1
+
+/* MMSYS */
+
+#define CLK_MM_SMI_COMMON		0
+#define CLK_MM_SMI_LARB0		1
+#define CLK_MM_CAM_MDP			2
+#define CLK_MM_MDP_RDMA0		3
+#define CLK_MM_MDP_RDMA1		4
+#define CLK_MM_MDP_RSZ0			5
+#define CLK_MM_MDP_RSZ1			6
+#define CLK_MM_MDP_RSZ2			7
+#define CLK_MM_MDP_TDSHP0		8
+#define CLK_MM_MDP_TDSHP1		9
+#define CLK_MM_MDP_CROP			10
+#define CLK_MM_MDP_WDMA			11
+#define CLK_MM_MDP_WROT0		12
+#define CLK_MM_MDP_WROT1		13
+#define CLK_MM_FAKE_ENG			14
+#define CLK_MM_MUTEX_32K		15
+#define CLK_MM_DISP_OVL0		16
+#define CLK_MM_DISP_OVL1		17
+#define CLK_MM_DISP_RDMA0		18
+#define CLK_MM_DISP_RDMA1		19
+#define CLK_MM_DISP_RDMA2		20
+#define CLK_MM_DISP_WDMA0		21
+#define CLK_MM_DISP_WDMA1		22
+#define CLK_MM_DISP_COLOR0		23
+#define CLK_MM_DISP_COLOR1		24
+#define CLK_MM_DISP_AAL			25
+#define CLK_MM_DISP_GAMMA		26
+#define CLK_MM_DISP_UFOE		27
+#define CLK_MM_DISP_SPLIT0		28
+#define CLK_MM_DISP_OD			29
+#define CLK_MM_DISP_PWM0_MM		30
+#define CLK_MM_DISP_PWM0_26M		31
+#define CLK_MM_DISP_PWM1_MM		32
+#define CLK_MM_DISP_PWM1_26M		33
+#define CLK_MM_DSI0_ENGINE		34
+#define CLK_MM_DSI0_DIGITAL		35
+#define CLK_MM_DSI1_ENGINE		36
+#define CLK_MM_DSI1_DIGITAL		37
+#define CLK_MM_DPI_PIXEL		38
+#define CLK_MM_DPI_ENGINE		39
+#define CLK_MM_DPI1_PIXEL		40
+#define CLK_MM_DPI1_ENGINE		41
+#define CLK_MM_LVDS_PIXEL		42
+#define CLK_MM_LVDS_CTS			43
+#define CLK_MM_SMI_LARB4		44
+#define CLK_MM_SMI_COMMON1		45
+#define CLK_MM_SMI_LARB5		46
+#define CLK_MM_MDP_RDMA2		47
+#define CLK_MM_MDP_TDSHP2		48
+#define CLK_MM_DISP_OVL2		49
+#define CLK_MM_DISP_WDMA2		50
+#define CLK_MM_DISP_COLOR2		51
+#define CLK_MM_DISP_AAL1		52
+#define CLK_MM_DISP_OD1			53
+#define CLK_MM_LVDS1_PIXEL		54
+#define CLK_MM_LVDS1_CTS		55
+#define CLK_MM_SMI_LARB7		56
+#define CLK_MM_MDP_RDMA3		57
+#define CLK_MM_MDP_WROT2		58
+#define CLK_MM_DSI2			59
+#define CLK_MM_DSI2_DIGITAL		60
+#define CLK_MM_DSI3			61
+#define CLK_MM_DSI3_DIGITAL		62
+#define CLK_MM_DISP_PWM2_MM		63
+#define CLK_MM_DISP_PWM2_26M		64
+#define CLK_MM_NR_CLK			65
+
+/* IMGSYS */
+
+#define CLK_IMG_SMI_LARB2		0
+#define CLK_IMG_SENINF_SCAM_EN		1
+#define CLK_IMG_SENINF_CAM_EN		2
+#define CLK_IMG_CAM_SV_EN		3
+#define CLK_IMG_CAM_SV1_EN		4
+#define CLK_IMG_CAM_SV2_EN		5
+#define CLK_IMG_NR_CLK			6
+
+/* BDPSYS */
+
+#define CLK_BDP_BRIDGE_B		0
+#define CLK_BDP_BRIDGE_DRAM		1
+#define CLK_BDP_LARB_DRAM		2
+#define CLK_BDP_WR_CHANNEL_VDI_PXL	3
+#define CLK_BDP_WR_CHANNEL_VDI_DRAM	4
+#define CLK_BDP_WR_CHANNEL_VDI_B	5
+#define CLK_BDP_MT_B			6
+#define CLK_BDP_DISPFMT_27M		7
+#define CLK_BDP_DISPFMT_27M_VDOUT	8
+#define CLK_BDP_DISPFMT_27_74_74	9
+#define CLK_BDP_DISPFMT_2FS		10
+#define CLK_BDP_DISPFMT_2FS_2FS74_148	11
+#define CLK_BDP_DISPFMT_B		12
+#define CLK_BDP_VDO_DRAM		13
+#define CLK_BDP_VDO_2FS			14
+#define CLK_BDP_VDO_B			15
+#define CLK_BDP_WR_CHANNEL_DI_PXL	16
+#define CLK_BDP_WR_CHANNEL_DI_DRAM	17
+#define CLK_BDP_WR_CHANNEL_DI_B		18
+#define CLK_BDP_NR_AGENT		19
+#define CLK_BDP_NR_DRAM			20
+#define CLK_BDP_NR_B			21
+#define CLK_BDP_BRIDGE_RT_B		22
+#define CLK_BDP_BRIDGE_RT_DRAM		23
+#define CLK_BDP_LARB_RT_DRAM		24
+#define CLK_BDP_TVD_TDC			25
+#define CLK_BDP_TVD_54			26
+#define CLK_BDP_TVD_CBUS		27
+#define CLK_BDP_NR_CLK			28
+
+/* VDECSYS */
+
+#define CLK_VDEC_CKEN			0
+#define CLK_VDEC_LARB1_CKEN		1
+#define CLK_VDEC_IMGRZ_CKEN		2
+#define CLK_VDEC_NR_CLK			3
+
+/* VENCSYS */
+
+#define CLK_VENC_SMI_COMMON_CON		0
+#define CLK_VENC_VENC			1
+#define CLK_VENC_SMI_LARB6		2
+#define CLK_VENC_NR_CLK			3
+
+/* JPGDECSYS */
+
+#define CLK_JPGDEC_JPGDEC1		0
+#define CLK_JPGDEC_JPGDEC		1
+#define CLK_JPGDEC_NR_CLK		2
+
+#endif /* _DT_BINDINGS_CLK_MT2712_H */

include/dt-bindings/clock/mt6739-clk.h

@@ -0,0 +1,262 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+
+#ifndef _DT_BINDINGS_CLK_MT6739_H
+#define _DT_BINDINGS_CLK_MT6739_H
+
+#define	CLK_TOP_CLK26M		0
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL		0	/* armpll_ll		ARMPLL_LL */
+#define CLK_APMIXED_MAINPLL		1	/* mainpll		MAINPLL */
+#define CLK_APMIXED_MFGPLL		2	/* mfgpll		MFGPLL */
+#define CLK_APMIXED_MMPLL		3	/* mmpll		MMPLL */
+#define CLK_APMIXED_UNIVPLL		4	/* univpll		UNIVPLL */
+#define CLK_APMIXED_MSDCPLL		5	/* msdcpll		MSDCPLL */
+#define CLK_APMIXED_APLL1		6	/* apll1		APLL1 */
+#define CLK_APMIXED_NR_CLK		7
+
+/* TOPCK */
+
+#define CLK_TOP_SYSPLL			0	/* syspll_ck		syspll_ck */
+#define CLK_TOP_SYSPLL_D2		1	/* syspll_d2		syspll_d2 */
+#define CLK_TOP_SYSPLL1_D2		2	/* syspll1_d2		syspll1_d2 */
+#define CLK_TOP_SYSPLL1_D4		3	/* syspll1_d4		syspll1_d4 */
+#define CLK_TOP_SYSPLL1_D8		4	/* syspll1_d8		syspll1_d8 */
+#define CLK_TOP_SYSPLL1_D16		5	/* syspll1_d16		syspll1_d16 */
+#define CLK_TOP_SYSPLL_D3		6	/* syspll_d3		syspll_d3 */
+#define CLK_TOP_SYSPLL2_D2		7	/* syspll2_d2		syspll2_d2 */
+#define CLK_TOP_SYSPLL2_D4		8	/* syspll2_d4		syspll2_d4 */
+#define CLK_TOP_SYSPLL_D5		9	/* syspll_d5		syspll_d5 */
+#define CLK_TOP_SYSPLL3_D2		10	/* syspll3_d2		syspll3_d2 */
+#define CLK_TOP_SYSPLL3_D4		11	/* syspll3_d4		syspll3_d4 */
+#define CLK_TOP_SYSPLL_D7		12	/* syspll_d7		syspll_d7 */
+#define CLK_TOP_SYSPLL4_D2		13	/* syspll4_d2		syspll4_d2 */
+#define CLK_TOP_SYSPLL4_D4		14	/* syspll4_d4		syspll4_d4 */
+#define CLK_TOP_UNIVPLL			15	/* univpll_ck		univpll_ck */
+#define CLK_TOP_UNIVPLL_D26		16	/* univpll_d26		univpll_d26 */
+#define CLK_TOP_UNIVPLL_48M_D2		17	/* univpll_48m_d2	univpll_48m_d2 */
+#define CLK_TOP_UNIVPLL_48M_D4		18	/* univpll_48m_d4	univpll_48m_d4 */
+#define CLK_TOP_UNIVPLL_48M_D8		19	/* univpll_48m_d8	univpll_48m_d8 */
+#define CLK_TOP_UNIVPLL_D2		20	/* univpll_d2		univpll_d2 */
+#define CLK_TOP_UNIVPLL1_D2		21	/* univpll1_d2		univpll1_d2 */
+#define CLK_TOP_UNIVPLL1_D4		22	/* univpll1_d4		univpll1_d4 */
+#define CLK_TOP_UNIVPLL_D3		23	/* univpll_d3		univpll_d3 */
+#define CLK_TOP_UNIVPLL2_D2		24	/* univpll2_d2		univpll2_d2 */
+#define CLK_TOP_UNIVPLL2_D4		25	/* univpll2_d4		univpll2_d4 */
+#define CLK_TOP_UNIVPLL2_D8		26	/* univpll2_d8		univpll2_d8 */
+#define CLK_TOP_UNIVPLL2_D32		27	/* univpll2_d32		univpll2_d32 */
+#define CLK_TOP_UNIVPLL_D5		28	/* univpll_d5		univpll_d5 */
+#define CLK_TOP_UNIVPLL3_D2		29	/* univpll3_d2		univpll3_d2 */
+#define CLK_TOP_UNIVPLL3_D4		30	/* univpll3_d4		univpll3_d4 */
+#define CLK_TOP_UNIVPLL3_D8		31	/* univpll3_d8		univpll3_d8 */
+#define CLK_TOP_MMPLL			32	/* mmpll_ck		mmpll_ck */
+#define CLK_TOP_VENCPLL			33	/* vencpll_ck		vencpll_ck */
+#define CLK_TOP_MSDCPLL			34	/* msdcpll_ck		msdcpll_ck */
+#define CLK_TOP_MSDCPLL_D2		35	/* msdcpll_d2		msdcpll_d2 */
+#define CLK_TOP_APLL1			36	/* apll1_ck		apll1_ck */
+#define CLK_TOP_APLL1_D2		37	/* apll1_d2		apll1_d2 */
+#define CLK_TOP_APLL1_D4		38	/* apll1_d4		apll1_d4 */
+#define CLK_TOP_APLL1_D8		39	/* apll1_d8		apll1_d8 */
+#define CLK_TOP_DMPLL			40	/* dmpll_ck		dmpll_ck */
+#define CLK_TOP_AXI_SEL			41	/* axi_sel		axi_sel */
+#define CLK_TOP_MEM_SEL			42	/* mem_sel		mem_sel */
+#define CLK_TOP_DDRPHYCFG_SEL		43	/* ddrphycfg_sel	ddrphycfg_sel */
+#define CLK_TOP_MM_SEL			44	/* mm_sel		mm_sel */
+#define CLK_TOP_MFG_SEL			45	/* mfg_sel		mfg_sel */
+#define CLK_TOP_CAMTG_SEL		46	/* camtg_sel		camtg_sel */
+#define CLK_TOP_UART_SEL		47	/* uart_sel		uart_sel */
+#define CLK_TOP_SPI_SEL			48	/* spi_sel		spi_sel */
+#define CLK_TOP_MSDC50_0_HCLK_SEL	49	/* msdc5hclk		msdc50_0_hclk_sel */
+#define CLK_TOP_MSDC50_0_SEL		50	/* msdc50_0_sel		msdc50_0_sel */
+#define CLK_TOP_MSDC30_1_SEL		51	/* msdc30_1_sel		msdc30_1_sel */
+#define CLK_TOP_AUDIO_SEL		52	/* audio_sel		audio_sel */
+#define CLK_TOP_AUD_INTBUS_SEL		53	/* aud_intbus_sel	aud_intbus_sel */
+#define CLK_TOP_DBI0_SEL		54	/* dbi0_sel		dbi0_sel */
+#define CLK_TOP_SCAM_SEL		55	/* scam_sel		scam_sel */
+#define CLK_TOP_AUD_1_SEL		56	/* aud_1_sel		aud_1_sel */
+#define CLK_TOP_DISP_PWM_SEL		57	/* disp_pwm_sel		disp_pwm_sel */
+#define CLK_TOP_NFI2X_SEL		58	/* nfi2x_sel		nfi2x_sel */
+#define CLK_TOP_NFIECC_SEL		59	/* nfiecc_sel		nfiecc_sel */
+#define CLK_TOP_USB_TOP_SEL		60	/* usb_top_sel		usb_top_sel */
+#define CLK_TOP_SPM_SEL			61	/* spm_sel		spm_sel */
+#define CLK_TOP_I2C_SEL			62	/* i2c_sel		i2c_sel */
+#define CLK_TOP_SENIF_SEL		63	/* senif_sel		senif_sel */
+#define CLK_TOP_DXCC_SEL		64	/* dxcc_sel		dxcc_sel */
+#define CLK_TOP_CAMTG2_SEL		65	/* camtg2_sel		camtg2_sel */
+#define CLK_TOP_AUD_ENGEN1_SEL		66	/* aud_engen1_sel	aud_engen1_sel */
+#define CLK_TOP_NR_CLK			67
+
+/* AUDIO */
+
+#define CLK_AUDIO_AFE			0	/* aud_afe		PDN_AFE */
+#define CLK_AUDIO_22M			1	/* aud_22m		PDN_22M */
+#define CLK_AUDIO_APLL_TUNER		2	/* aud_apll_tuner	PDN_APLL_TUNER */
+#define CLK_AUDIO_ADC			3	/* aud_adc		PDN_ADC */
+#define CLK_AUDIO_DAC			4	/* aud_dac		PDN_DAC */
+#define CLK_AUDIO_DAC_PREDIS		5	/* aud_dac_predis	PDN_DAC_PREDIS */
+#define CLK_AUDIO_TML			6	/* aud_tml		PDN_TML */
+#define CLK_AUDIO_I2S1_BCLK		7	/* aud_i2s1_bclk	I2S1_BCLK_SW_CG */
+#define CLK_AUDIO_I2S2_BCLK		8	/* aud_i2s2_bclk	I2S2_BCLK_SW_CG */
+#define CLK_AUDIO_I2S3_BCLK		9	/* aud_i2s3_bclk	I2S3_BCLK_SW_CG */
+#define CLK_AUDIO_I2S4_BCLK		10	/* aud_i2s4_bclk	I2S4_BCLK_SW_CG */
+#define CLK_AUDIO_NR_CLK		11
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB2_SMI		0	/* img_larb2_smi	LARB2_SMI_CKPDN */
+#define CLK_IMG_CAM_SMI			1	/* img_cam_smi		CAM_SMI_CKPDN */
+#define CLK_IMG_CAM_CAM			2	/* img_cam_cam		CAM_CAM_CKPDN */
+#define CLK_IMG_SEN_TG			3	/* img_sen_tg		SEN_TG_CKPDN */
+#define CLK_IMG_SEN_CAM			4	/* img_sen_cam		SEN_CAM_CKPDN */
+#define CLK_IMG_CAM_SV			5	/* img_cam_sv		CAM_SV_CKPDN */
+#define CLK_IMG_SUFOD			6	/* img_sufod		SUFOD_CKPDN */
+#define CLK_IMG_FD			7	/* img_fd		FD_CKPDN */
+#define CLK_IMG_NR_CLK			8
+
+/* INFRACFG_AO */
+
+#define CLK_INFRA_PMIC_TMR		0	/* infra_pmic_tmr	PMIC_CG_TMR */
+#define CLK_INFRA_PMIC_AP		1	/* infra_pmic_ap	PMIC_CG_AP */
+#define CLK_INFRA_PMIC_MD		2	/* infra_pmic_md	PMIC_CG_MD */
+#define CLK_INFRA_PMIC_CONN		3	/* infra_pmic_conn	PMIC_CG_CONN */
+#define CLK_INFRA_SEJ			4	/* infra_sej		SEJ_CG */
+#define CLK_INFRA_APXGPT		5	/* infra_apxgpt		APXGPT_CG */
+#define CLK_INFRA_ICUSB			6	/* infra_icusb		ICUSB_CG */
+#define CLK_INFRA_GCE			7	/* infra_gce		GCE_CG */
+#define CLK_INFRA_THERM			8	/* infra_therm		THERM_CG */
+#define CLK_INFRA_I2C0			9	/* infra_i2c0		I2C0_CG */
+#define CLK_INFRA_I2C1			10	/* infra_i2c1		I2C1_CG */
+#define CLK_INFRA_I2C2			11	/* infra_i2c2		I2C2_CG */
+#define CLK_INFRA_I2C3			12	/* infra_i2c3		I2C3_CG */
+#define CLK_INFRA_PWM_HCLK		13	/* infra_pwm_hclk	PWM_HCLK_CG */
+#define CLK_INFRA_PWM1			14	/* infra_pwm1		PWM1_CG */
+#define CLK_INFRA_PWM2			15	/* infra_pwm2		PWM2_CG */
+#define CLK_INFRA_PWM3			16	/* infra_pwm3		PWM3_CG */
+#define CLK_INFRA_PWM4			17	/* infra_pwm4		PWM4_CG */
+#define CLK_INFRA_PWM5			18	/* infra_pwm5		PWM5_CG */
+#define CLK_INFRA_PWM			19	/* infra_pwm		PWM_CG */
+#define CLK_INFRA_UART0			20	/* infra_uart0		UART0_CG */
+#define CLK_INFRA_UART1			21	/* infra_uart1		UART1_CG */
+#define CLK_INFRA_UART2			22	/* infra_uart2		UART2_CG */
+#define CLK_INFRA_UART3			23	/* infra_uart3		UART3_CG */
+#define CLK_INFRA_GCE_26M		24	/* infra_gce_26m	GCE_26M */
+#define CLK_INFRA_CQ_DMA_FPC		25	/* infra_dma		CQ_DMA_FPC */
+#define CLK_INFRA_BTIF			26	/* infra_btif		BTIF_CG */
+#define CLK_INFRA_SPI0			27	/* infra_spi0		SPI0_CG */
+#define CLK_INFRA_MSDC0			28	/* infra_msdc0		MSDC0_CG */
+#define CLK_INFRA_MSDC1			29	/* infra_msdc1		MSDC1_CG */
+#define CLK_INFRA_NFIECC_312M		30	/* infra_nfiecc		NFIECC_312M_CG */
+#define CLK_INFRA_DVFSRC		31	/* infra_dvfsrc		DVFSRC_CG */
+#define CLK_INFRA_GCPU			32	/* infra_gcpu		GCPU_CG */
+#define CLK_INFRA_TRNG			33	/* infra_trng		TRNG_CG */
+#define CLK_INFRA_AUXADC		34	/* infra_auxadc		AUXADC_CG */
+#define CLK_INFRA_CPUM			35	/* infra_cpum		CPUM_CG */
+#define CLK_INFRA_CCIF1_AP		36	/* infra_ccif1_ap	CCIF1_AP_CG */
+#define CLK_INFRA_CCIF1_MD		37	/* infra_ccif1_md	CCIF1_MD_CG */
+#define CLK_INFRA_AUXADC_MD		38	/* infra_auxadc_md	AUXADC_MD_CG */
+#define CLK_INFRA_NFI			39	/* infra_nfi		NFI_CG */
+#define CLK_INFRA_AP_DMA		40	/* infra_ap_dma		AP_DMA_CG */
+#define CLK_INFRA_XIU			41	/* infra_xiu		XIU_CG */
+#define CLK_INFRA_DEVICE_APC		42	/* infra_dapc		DEVICE_APC_CG */
+#define CLK_INFRA_CCIF_AP		43	/* infra_ccif_ap	CCIF_AP_CG */
+#define CLK_INFRA_DEBUGSYS		44	/* infra_debugsys	DEBUGSYS_CG */
+#define CLK_INFRA_AUDIO			45	/* infra_audio		AUDIO_CG */
+#define CLK_INFRA_CCIF_MD		46	/* infra_ccif_md	CCIF_MD_CG */
+#define CLK_INFRA_DXCC_SEC_CORE		47	/* infra_secore		DXCC_SEC_CORE_CG */
+#define CLK_INFRA_DXCC_AO		48	/* infra_dxcc_ao	DXCC_AO_CG */
+#define CLK_INFRA_DRAMC_F26M		49	/* infra_dramc26	DRAMC_F26M_CG */
+#define CLK_INFRA_RG_PWM_FBCLK6		50	/* infra_pwmfb		RG_PWM_FBCLK6_CK_CG */
+#define CLK_INFRA_DISP_PWM		51	/* infra_disp_pwm	DISP_PWM_CG */
+#define CLK_INFRA_CLDMA_BCLK		52	/* infra_cldmabclk	CLDMA_BCLK_CK */
+#define CLK_INFRA_AUDIO_26M_BCLK	53	/* infra_audio26m	AUDIO_26M_BCLK_CK */
+#define CLK_INFRA_SPI1			54	/* infra_spi1		SPI1_CG */
+#define CLK_INFRA_I2C4			55	/* infra_i2c4		I2C4_CG */
+#define CLK_INFRA_MODEM_TEMP_SHARE	56	/* infra_mdtemp		MODEM_TEMP_SHARE_CG */
+#define CLK_INFRA_SPI2			57	/* infra_spi2		SPI2_CG */
+#define CLK_INFRA_SPI3			58	/* infra_spi3		SPI3_CG */
+#define CLK_INFRA_I2C5			59	/* infra_i2c5		I2C5_CG */
+#define CLK_INFRA_I2C5_ARBITER		60	/* infra_i2c5a		I2C5_ARBITER_CG */
+#define CLK_INFRA_I2C5_IMM		61	/* infra_i2c5_imm	I2C5_IMM_CG */
+#define CLK_INFRA_I2C1_ARBITER		62	/* infra_i2c1a		I2C1_ARBITER_CG */
+#define CLK_INFRA_I2C1_IMM		63	/* infra_i2c1_imm	I2C1_IMM_CG */
+#define CLK_INFRA_I2C2_ARBITER		64	/* infra_i2c2a		I2C2_ARBITER_CG */
+#define CLK_INFRA_I2C2_IMM		65	/* infra_i2c2_imm	I2C2_IMM_CG */
+#define CLK_INFRA_SPI4			66	/* infra_spi4		SPI4_CG */
+#define CLK_INFRA_SPI5			67	/* infra_spi5		SPI5_CG */
+#define CLK_INFRA_CQ_DMA		68	/* infra_cq_dma		CQ_DMA_CG */
+#define CLK_INFRA_MSDC0_SELF		69	/* infra_msdc0sf	MSDC0_SELF_CG */
+#define CLK_INFRA_MSDC1_SELF		70	/* infra_msdc1sf	MSDC1_SELF_CG */
+#define CLK_INFRA_MSDC2_SELF		71	/* infra_msdc2sf	MSDC2_SELF_CG */
+#define CLK_INFRA_I2C6			72	/* infra_i2c6		I2C6_CG */
+#define CLK_INFRA_AP_MSDC0		73	/* infra_ap_msdc0	AP_MSDC0_CG */
+#define CLK_INFRA_MD_MSDC0		74	/* infra_md_msdc0	MD_MSDC0_CG */
+#define CLK_INFRA_MSDC0_SRC		75	/* infra_msdc0_clk	MSDC0_SRC_CLK_CG */
+#define CLK_INFRA_MSDC1_SRC		76	/* infra_msdc1_clk	MSDC1_SRC_CLK_CG */
+#define CLK_INFRA_MSDC2_SRC		77	/* infra_msdc2_clk	MSDC2_SRC_CLK_CG */
+#define CLK_INFRA_PERI_DCM_RG_FORCE_CLKOFF 78	/* infra_dcmforce	PERI_DCM_RG_FORCE_CLKOFF */
+#define CLK_INFRA_NFI_1X                79      /* infra_nfi_1x         NFI_1X_CG */
+#define CLK_INFRA_NR_CLK		80
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_SMI_COMMON		0	/* mm_smi_common	SMI_COMMON */
+#define CLK_MM_SMI_LARB0		1	/* mm_smi_larb0		SMI_LARB0 */
+#define CLK_MM_GALS_COMM0		2	/* mm_gals_comm0	GALS_COMM0 */
+#define CLK_MM_GALS_COMM1		3	/* mm_gals_comm1	GALS_COMM1 */
+#define CLK_MM_ISP_DL			4	/* mm_isp_dl		ISP_DL */
+#define CLK_MM_MDP_RDMA0		5	/* mm_mdp_rdma0		MDP_RDMA0 */
+#define CLK_MM_MDP_RSZ0			6	/* mm_mdp_rsz0		MDP_RSZ0 */
+#define CLK_MM_MDP_RSZ1			7	/* mm_mdp_rsz1		MDP_RSZ1 */
+#define CLK_MM_MDP_TDSHP		8	/* mm_mdp_tdshp		MDP_TDSHP */
+#define CLK_MM_MDP_WROT0		9	/* mm_mdp_wrot0		MDP_WROT0 */
+#define CLK_MM_MDP_WDMA0		10	/* mm_mdp_wdma0		MDP_WDMA0 */
+#define CLK_MM_FAKE_ENG			11	/* mm_fake_eng		FAKE_ENG */
+#define CLK_MM_DISP_OVL0		12	/* mm_disp_ovl0		DISP_OVL0 */
+#define CLK_MM_DISP_RDMA0		13	/* mm_disp_rdma0	DISP_RDMA0 */
+#define CLK_MM_DISP_WDMA0		14	/* mm_disp_wdma0	DISP_WDMA0 */
+#define CLK_MM_DISP_COLOR0		15	/* mm_disp_color0	DISP_COLOR0 */
+#define CLK_MM_DISP_CCORR0		16	/* mm_disp_ccorr0	DISP_CCORR0 */
+#define CLK_MM_DISP_AAL0		17	/* mm_disp_aal0		DISP_AAL0 */
+#define CLK_MM_DISP_GAMMA0		18	/* mm_disp_gamma0	DISP_GAMMA0 */
+#define CLK_MM_DISP_DITHER0		19	/* mm_disp_dither0	DISP_DITHER0 */
+#define CLK_MM_DSI_MM_CLOCK		20	/* mm_dsi_mm_clock	DSI_MM_CLOCK */
+#define CLK_MM_DSI_INTERF		21	/* mm_dsi_interf	DSI_INTERF */
+#define CLK_MM_DBI_MM_CLOCK		22	/* mm_dbi_mm_clock	DBI_MM_CLOCK */
+#define CLK_MM_DBI_INTERF		23	/* mm_dbi_interf	DBI_INTERF */
+#define CLK_MM_F26M_HRT			24	/* mm_f26m_hrt		F26M_HRT */
+#define CLK_MM_CG0_B25			25	/* mm_cg0_b25		CG0_B25 */
+#define CLK_MM_CG0_B26			26	/* mm_cg0_b26		CG0_B26 */
+#define CLK_MM_CG0_B27			27	/* mm_cg0_b27		CG0_B27 */
+#define CLK_MM_CG0_B28			28	/* mm_cg0_b28		CG0_B28 */
+#define CLK_MM_CG0_B29			29	/* mm_cg0_b29		CG0_B29 */
+#define CLK_MM_CG0_B30			30	/* mm_cg0_b30		CG0_B30 */
+#define CLK_MM_CG0_B31			31	/* mm_cg0_b31		CG0_B31 */
+#define CLK_MM_NR_CLK			32
+
+/* VENC_GCON */
+
+#define CLK_VENC_SET0_LARB		0	/* venc_set0_larb	SET0_LARB */
+#define CLK_VENC_SET1_VENC		1	/* venc_set1_venc	SET1_VENC */
+#define CLK_VENC_SET2_JPGENC		2	/* jpgenc		SET2_JPGENC */
+#define CLK_VENC_SET3_VDEC		3	/* venc_set3_vdec	SET3_VDEC */
+#define CLK_VENC_NR_CLK			4
+
+/* PERICFG */
+
+#define CLK_PERIAXI_DISABLE		0	/* periaxi_disable	PERIAXI_CG_DISABLE */
+#define CLK_PER_NR_CLK			1
+
+/* SCP_SYS */
+#define SCP_SYS_MFG0  0
+#define SCP_SYS_MFG1  1
+#define SCP_SYS_MD1  2
+#define SCP_SYS_CONN  3
+#define SCP_SYS_MM0  4
+#define SCP_SYS_ISP  5
+#define SCP_SYS_VEN  6
+#define SCP_NR_SYSS  7
+#endif

include/dt-bindings/clock/mt6761-clk.h

@@ -0,0 +1,398 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6761_H
+#define _DT_BINDINGS_CLK_MT6761_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_MFGPLL		2
+#define CLK_APMIXED_MMPLL		3
+#define CLK_APMIXED_UNIV2PLL		4
+#define CLK_APMIXED_MSDCPLL		5
+#define CLK_APMIXED_APLL1		6
+#define CLK_APMIXED_MPLL		7
+#define CLK_APMIXED_ULPOSC1		8
+#define CLK_APMIXED_ULPOSC2		9
+#define CLK_APMIXED_SSUSB26M		10
+#define CLK_APMIXED_APPLL26M		11
+#define CLK_APMIXED_MIPIC0_26M		12
+#define CLK_APMIXED_MDPLLGP26M		13
+#define CLK_APMIXED_MMSYS_F26M		14
+#define CLK_APMIXED_UFS26M		15
+#define CLK_APMIXED_MIPIC1_26M		16
+#define CLK_APMIXED_MEMPLL26M		17
+#define CLK_APMIXED_CLKSQ_LVPLL_26M	18
+#define CLK_APMIXED_MIPID0_26M		19
+#define CLK_APMIXED_NR_CLK		20
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK32K			0
+#define CLK_TOP_CLK26M			1
+#define CLK_TOP_SYSPLL			2
+#define CLK_TOP_SYSPLL_D2		3
+#define CLK_TOP_SYSPLL1_D2		4
+#define CLK_TOP_SYSPLL1_D4		5
+#define CLK_TOP_SYSPLL1_D8		6
+#define CLK_TOP_SYSPLL1_D16		7
+#define CLK_TOP_SYSPLL_D3		8
+#define CLK_TOP_SYSPLL2_D2		9
+#define CLK_TOP_SYSPLL2_D4		10
+#define CLK_TOP_SYSPLL2_D8		11
+#define CLK_TOP_SYSPLL_D5		12
+#define CLK_TOP_SYSPLL3_D2		13
+#define CLK_TOP_SYSPLL3_D4		14
+#define CLK_TOP_SYSPLL_D7		15
+#define CLK_TOP_SYSPLL4_D2		16
+#define CLK_TOP_SYSPLL4_D4		17
+#define CLK_TOP_USB20_192M		18
+#define CLK_TOP_USB20_192M_D4		19
+#define CLK_TOP_USB20_192M_D8		20
+#define CLK_TOP_USB20_192M_D16		21
+#define CLK_TOP_USB20_192M_D32		22
+#define CLK_TOP_USB_PHY48M		23
+#define CLK_TOP_UNIVPLL			24
+#define CLK_TOP_UNIVPLL_D2		25
+#define CLK_TOP_UNIVPLL1_D2		26
+#define CLK_TOP_UNIVPLL1_D4		27
+#define CLK_TOP_UNIVPLL_D3		28
+#define CLK_TOP_UNIVPLL2_D2		29
+#define CLK_TOP_UNIVPLL2_D4		30
+#define CLK_TOP_UNIVPLL2_D8		31
+#define CLK_TOP_UNIVPLL2_D32		32
+#define CLK_TOP_UNIVPLL_D5		33
+#define CLK_TOP_UNIVPLL3_D2		34
+#define CLK_TOP_UNIVPLL3_D4		35
+#define CLK_TOP_MMPLL			36
+#define CLK_TOP_MMPLL_D2		37
+#define CLK_TOP_MPLL_104M		38
+#define CLK_TOP_MPLL_52M		39
+#define CLK_TOP_MFGPLL			40
+#define CLK_TOP_MSDCPLL			41
+#define CLK_TOP_MSDCPLL_D2		42
+#define CLK_TOP_APLL1			43
+#define CLK_TOP_APLL1_D2		44
+#define CLK_TOP_APLL1_D4		45
+#define CLK_TOP_APLL1_D8		46
+#define CLK_TOP_ULPOSC1_D2		47
+#define CLK_TOP_ULPOSC1_D4		48
+#define CLK_TOP_ULPOSC1_D8		49
+#define CLK_TOP_ULPOSC1_D16		50
+#define CLK_TOP_ULPOSC1_D32		51
+#define CLK_TOP_DMPLL			52
+#define CLK_TOP_DA_USB20_48M_DIV	53
+#define CLK_TOP_DA_UNIV_48M_DIV		54
+#define CLK_TOP_DA_MPLL_104M_DIV	55
+#define CLK_TOP_DA_MPLL_52M_DIV		56
+#define CLK_TOP_CSW_FAXI		57
+#define CLK_TOP_CSW_FMSDC30_1		58
+#define CLK_TOP_CSW_FMSDC30_2		59
+#define CLK_TOP_AXI			60
+#define CLK_TOP_MEM			61
+#define CLK_TOP_MM			62
+#define CLK_TOP_SCP			63
+#define CLK_TOP_MFG			64
+#define CLK_TOP_F_FUART			65
+#define CLK_TOP_SPI			66
+#define CLK_TOP_MSDC50_0		67
+#define CLK_TOP_AUDIO			68
+#define CLK_TOP_AUD_1			69
+#define CLK_TOP_AUD_ENGEN1		70
+#define CLK_TOP_F_FDISP_PWM		71
+#define CLK_TOP_SSPM			72
+#define CLK_TOP_DXCC			73
+#define CLK_TOP_I2C			74
+#define CLK_TOP_F_FPWM			75
+#define CLK_TOP_F_FSENINF		76
+#define CLK_TOP_AES_FDE			77
+#define CLK_TOP_F_BIST2FPC		78
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0	79
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1	80
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2	81
+#define CLK_TOP_UFS_TICK1US		82
+#define CLK_TOP_APLL12_DIV0		83
+#define CLK_TOP_APLL12_DIV1		84
+#define CLK_TOP_APLL12_DIV2		85
+#define CLK_TOP_APLL12_DIV3		86
+#define CLK_TOP_APLL12_DIV4		87
+#define CLK_TOP_APLL12_DIVB		88
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN	89
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN	90
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN	91
+#define CLK_TOP_FMEM_OCC_DRC_EN		92
+#define CLK_TOP_USB20_48M_EN		93
+#define CLK_TOP_UNIVPLL_48M_EN		94
+#define CLK_TOP_MPLL_104M_EN		95
+#define CLK_TOP_MPLL_52M_EN		96
+#define CLK_TOP_F_UFS_MP_SAP_CFG_EN	97
+#define CLK_TOP_UFS_TICK1US_EN		98
+#define CLK_TOP_F_BIST2FPC_EN		99
+#define CLK_TOP_QS_CG			100
+#define CLK_TOP_MD_32K			101
+#define CLK_TOP_MD_26M			102
+#define CLK_TOP_CONN_32K		103
+#define CLK_TOP_CONN_26M		104
+#define CLK_TOP_AXI_SEL			105
+#define CLK_TOP_MEM_SEL			106
+#define CLK_TOP_MM_SEL			107
+#define CLK_TOP_SCP_SEL			108
+#define CLK_TOP_MFG_SEL			109
+#define CLK_TOP_ATB_SEL			110
+#define CLK_TOP_CAMTG_SEL		111
+#define CLK_TOP_CAMTG1_SEL		112
+#define CLK_TOP_CAMTG2_SEL		113
+#define CLK_TOP_CAMTG3_SEL		114
+#define CLK_TOP_UART_SEL		115
+#define CLK_TOP_SPI_SEL			116
+#define CLK_TOP_MSDC50_0_HCLK_SEL	117
+#define CLK_TOP_MSDC50_0_SEL		118
+#define CLK_TOP_MSDC30_1_SEL		119
+#define CLK_TOP_AUDIO_SEL		120
+#define CLK_TOP_AUD_INTBUS_SEL		121
+#define CLK_TOP_AUD_1_SEL		122
+#define CLK_TOP_AUD_ENGEN1_SEL		123
+#define CLK_TOP_DISP_PWM_SEL		124
+#define CLK_TOP_SSPM_SEL		125
+#define CLK_TOP_DXCC_SEL		126
+#define CLK_TOP_USB_TOP_SEL		127
+#define CLK_TOP_SPM_SEL			128
+#define CLK_TOP_I2C_SEL			129
+#define CLK_TOP_PWM_SEL			130
+#define CLK_TOP_SENINF_SEL		131
+#define CLK_TOP_AES_FDE_SEL		132
+#define CLK_TOP_PWRAP_ULPOSC_SEL	133
+#define CLK_TOP_CAMTM_SEL		134
+#define CLK_TOP_CLK13M			135
+#define CLK_TOP_NR_CLK			136
+
+/* INFRACFG */
+#define CLK_IFR_TOPAXI_DISABLE			0
+#define CLK_IFR_PMIC_TMR			1
+#define CLK_IFR_PMIC_AP				2
+#define CLK_IFR_PMIC_MD				3
+#define CLK_IFR_PMIC_CONN			4
+#define CLK_IFR_SCP_CORE			5
+#define CLK_IFR_SEJ				6
+#define CLK_IFR_APXGPT				7
+#define CLK_IFR_ICUSB				8
+#define CLK_IFR_GCE				9
+#define CLK_IFR_THERM				10
+#define CLK_IFR_I2C_AP				11
+#define CLK_IFR_I2C_CCU				12
+#define CLK_IFR_I2C_SSPM			13
+#define CLK_IFR_I2C_RSV				14
+#define CLK_IFR_PWM_HCLK			15
+#define CLK_IFR_PWM1				16
+#define CLK_IFR_PWM2				17
+#define CLK_IFR_PWM3				18
+#define CLK_IFR_PWM4				19
+#define CLK_IFR_PWM5				20
+#define CLK_IFR_PWM				21
+#define CLK_IFR_UART0				22
+#define CLK_IFR_UART1				23
+#define CLK_IFR_GCE_26M				24
+#define CLK_IFR_CQ_DMA_FPC			25
+#define CLK_IFR_BTIF				26
+#define CLK_IFR_SPI0				27
+#define CLK_IFR_MSDC0				28
+#define CLK_IFR_MSDC1				29
+#define CLK_IFR_DVFSRC				30
+#define CLK_IFR_GCPU				31
+#define CLK_IFR_TRNG				32
+#define CLK_IFR_AUXADC				33
+#define CLK_IFR_CPUM				34
+#define CLK_IFR_CCIF1_AP			35
+#define CLK_IFR_CCIF1_MD			36
+#define CLK_IFR_AUXADC_MD			37
+#define CLK_IFR_AP_DMA				38
+#define CLK_IFR_XIU				39
+#define CLK_IFR_DEVICE_APC			40
+#define CLK_IFR_CCIF_AP				41
+#define CLK_IFR_DEBUGSYS			42
+#define CLK_IFR_AUDIO				43
+#define CLK_IFR_CCIF_MD				44
+#define CLK_IFR_DXCC_SEC_CORE			45
+#define CLK_IFR_DXCC_AO				46
+#define CLK_IFR_DRAMC_F26M			47
+#define CLK_IFR_RG_PWM_FBCLK6			48
+#define CLK_IFR_DISP_PWM			49
+#define CLK_IFR_CLDMA_BCLK			50
+#define CLK_IFR_AUDIO_26M_BCLK			51
+#define CLK_IFR_SPI1				52
+#define CLK_IFR_I2C4				53
+#define CLK_IFR_MODEM_TEMP_SHARE		54
+#define CLK_IFR_SPI2				55
+#define CLK_IFR_SPI3				56
+#define CLK_IFR_SSPM				57
+#define CLK_IFR_I2C5				58
+#define CLK_IFR_I2C5_ARBITER			59
+#define CLK_IFR_I2C5_IMM			60
+#define CLK_IFR_I2C1_ARBITER			61
+#define CLK_IFR_I2C1_IMM			62
+#define CLK_IFR_I2C2_ARBITER			63
+#define CLK_IFR_I2C2_IMM			64
+#define CLK_IFR_SPI4				65
+#define CLK_IFR_SPI5				66
+#define CLK_IFR_CQ_DMA				67
+#define CLK_IFR_BIST2FPC			68
+#define CLK_IFR_FAES_FDE			69
+#define CLK_IFR_MSDC0_SELF			70
+#define CLK_IFR_MSDC1_SELF			71
+#define CLK_IFR_MSDC2_SELF			72
+#define CLK_IFR_SSPM_26M_SELF			73
+#define CLK_IFR_SSPM_32K_SELF			74
+#define CLK_IFR_UFS_AXI				75
+#define CLK_IFR_I2C6				76
+#define CLK_IFR_AP_MSDC0			77
+#define CLK_IFR_MD_MSDC0			78
+#define CLK_IFR_MSDC0_SRC			79
+#define CLK_IFR_MSDC1_SRC			80
+#define CLK_IFR_MSDC2_SRC			81
+#define CLK_IFR_PWRAP_TMR			82
+#define CLK_IFR_PWRAP_SPI			83
+#define CLK_IFR_PWRAP_SYS			84
+#define CLK_IFR_SEJ_F13M			85
+#define CLK_IFR_AES_TOP0_BCLK			86
+#define CLK_IFR_MCU_PM_BCLK			87
+#define CLK_IFR_CCIF2_AP			88
+#define CLK_IFR_CCIF2_MD			89
+#define CLK_IFR_CCIF3_AP			90
+#define CLK_IFR_CCIF3_MD			91
+#define CLK_IFR_PERI_DCM_RG_FORCE_CLKOFF	92
+#define CLK_IFR_NR_CLK				93
+
+/* PERICFG */
+#define CLK_PERIAXI_DISABLE		0
+#define CLK_PERI_NR_CLK			1
+
+/* GCE */
+
+#define CLK_GCE_FAXI			0
+#define CLK_GCE_NR_CLK			1
+
+/* AUDIO */
+#define CLK_AUDIO_AFE			0
+#define CLK_AUDIO_22M			1
+#define CLK_AUDIO_APLL_TUNER		2
+#define CLK_AUDIO_ADC			3
+#define CLK_AUDIO_DAC			4
+#define CLK_AUDIO_DAC_PREDIS		5
+#define CLK_AUDIO_TML			6
+#define CLK_AUDIO_I2S1_BCLK		7
+#define CLK_AUDIO_I2S2_BCLK		8
+#define CLK_AUDIO_I2S3_BCLK		9
+#define CLK_AUDIO_I2S4_BCLK		10
+#define CLK_AUDIO_NR_CLK		11
+
+/* MIPI_RX_ANA_CSI0A */
+
+#define CLK_MIPI0A_CSR_CSI_EN_0A	0
+#define CLK_MIPI0A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI0B */
+
+#define CLK_MIPI0B_CSR_CSI_EN_0B	0
+#define CLK_MIPI0B_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI1A */
+
+#define CLK_MIPI1A_CSR_CSI_EN_1A	0
+#define CLK_MIPI1A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI1B */
+
+#define CLK_MIPI1B_CSR_CSI_EN_1B	0
+#define CLK_MIPI1B_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI2A */
+
+#define CLK_MIPI2A_CSR_CSI_EN_2A	0
+#define CLK_MIPI2A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI2B */
+
+#define CLK_MIPI2B_CSR_CSI_EN_2B	0
+#define CLK_MIPI2B_NR_CLK		1
+
+/* MFG */
+
+#define CLK_MFGCFG_BAXI			0
+#define CLK_MFGCFG_BMEM			1
+#define CLK_MFGCFG_BG3D			2
+#define CLK_MFGCFG_B26M			3
+#define CLK_MFGCFG_NR_CLK		4
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_MDP_RDMA0		0
+#define CLK_MM_MDP_CCORR0		1
+#define CLK_MM_MDP_RSZ0			2
+#define CLK_MM_MDP_RSZ1			3
+#define CLK_MM_MDP_TDSHP0		4
+#define CLK_MM_MDP_WROT0		5
+#define CLK_MM_MDP_WDMA0		6
+#define CLK_MM_DISP_OVL0		7
+#define CLK_MM_DISP_OVL0_2L		8
+#define CLK_MM_DISP_RSZ0		9
+#define CLK_MM_DISP_RDMA0		10
+#define CLK_MM_DISP_WDMA0		11
+#define CLK_MM_DISP_COLOR0		12
+#define CLK_MM_DISP_CCORR0		13
+#define CLK_MM_DISP_AAL0		14
+#define CLK_MM_DISP_GAMMA0		15
+#define CLK_MM_DISP_DITHER0		16
+#define CLK_MM_DSI0			17
+#define CLK_MM_FAKE_ENG			18
+#define CLK_MM_SMI_COMMON		19
+#define CLK_MM_SMI_LARB0		20
+#define CLK_MM_SMI_COMM0		21
+#define CLK_MM_SMI_COMM1		22
+#define CLK_MM_CAM_MDP			23
+#define CLK_MM_SMI_IMG			24
+#define CLK_MM_SMI_CAM			25
+#define CLK_MM_IMG_DL_RELAY		26
+#define CLK_MM_IMG_DL_ASYNC_TOP		27
+#define CLK_MM_DIG_DSI			28
+#define CLK_MM_F26M_HRTWT		29
+#define CLK_MM_NR_CLK			30
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB2			0
+#define CLK_CAM				1
+#define CLK_CAMTG			2
+#define CLK_CAM_SENINF			3
+#define CLK_CAMSV0			4
+#define CLK_CAMSV1			5
+#define CLK_CAM_FDVT			6
+#define CLK_CAM_NR_CLK			7
+
+/* VENCSYS */
+
+#define CLK_VENC_SET0_LARB		0
+#define CLK_VENC_SET1_VENC		1
+#define CLK_VENC_SET2_JPGENC		2
+#define CLK_VENC_SET3_VDEC		3
+#define CLK_VENC_NR_CLK			4
+
+/* SCP_SYS */
+
+#define SCP_SYS_MD1		0
+#define SCP_SYS_CONN		1
+#define SCP_SYS_DPY		2
+#define SCP_SYS_DIS		3
+#define SCP_SYS_MFG		4
+#define SCP_SYS_IFR		5
+#define SCP_SYS_MFG_CORE0	6
+#define SCP_SYS_MFG_ASYNC	7
+#define SCP_SYS_CAM		8
+#define SCP_SYS_VCODEC		9
+#define SCP_NR_SYSS		10
+
+#endif /* _DT_BINDINGS_CLK_MT6761_H */

include/dt-bindings/clock/mt6765-clk.h

@@ -0,0 +1,395 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6765_H
+#define _DT_BINDINGS_CLK_MT6765_H
+
+/* FIX Clks */
+#define CLK_TOP_CLK26M			0
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_L		0
+#define CLK_APMIXED_ARMPLL		1
+#define CLK_APMIXED_CCIPLL		2
+#define CLK_APMIXED_MAINPLL		3
+#define CLK_APMIXED_MFGPLL		4
+#define CLK_APMIXED_MMPLL		5
+#define CLK_APMIXED_UNIV2PLL		6
+#define CLK_APMIXED_MSDCPLL		7
+#define CLK_APMIXED_APLL1		8
+#define CLK_APMIXED_MPLL		9
+#define CLK_APMIXED_ULPOSC1		10
+#define CLK_APMIXED_ULPOSC2		11
+#define CLK_APMIXED_SSUSB26M		12
+#define CLK_APMIXED_APPLL26M		13
+#define CLK_APMIXED_MIPIC0_26M		14
+#define CLK_APMIXED_MDPLLGP26M		15
+#define CLK_APMIXED_MMSYS_F26M		16
+#define CLK_APMIXED_UFS26M		17
+#define CLK_APMIXED_MIPIC1_26M		18
+#define CLK_APMIXED_MEMPLL26M		19
+#define CLK_APMIXED_CLKSQ_LVPLL_26M	20
+#define CLK_APMIXED_MIPID0_26M		21
+#define CLK_APMIXED_NR_CLK		22
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL			0
+#define CLK_TOP_SYSPLL_D2		1
+#define CLK_TOP_SYSPLL1_D2		2
+#define CLK_TOP_SYSPLL1_D4		3
+#define CLK_TOP_SYSPLL1_D8		4
+#define CLK_TOP_SYSPLL1_D16		5
+#define CLK_TOP_SYSPLL_D3		6
+#define CLK_TOP_SYSPLL2_D2		7
+#define CLK_TOP_SYSPLL2_D4		8
+#define CLK_TOP_SYSPLL2_D8		9
+#define CLK_TOP_SYSPLL_D5		10
+#define CLK_TOP_SYSPLL3_D2		11
+#define CLK_TOP_SYSPLL3_D4		12
+#define CLK_TOP_SYSPLL_D7		13
+#define CLK_TOP_SYSPLL4_D2		14
+#define CLK_TOP_SYSPLL4_D4		15
+#define CLK_TOP_USB20_192M		16
+#define CLK_TOP_USB20_192M_D4		17
+#define CLK_TOP_USB20_192M_D8		18
+#define CLK_TOP_USB20_192M_D16		19
+#define CLK_TOP_USB20_192M_D32		20
+#define CLK_TOP_UNIVPLL			21
+#define CLK_TOP_UNIVPLL_D2		22
+#define CLK_TOP_UNIVPLL1_D2		23
+#define CLK_TOP_UNIVPLL1_D4		24
+#define CLK_TOP_UNIVPLL_D3		25
+#define CLK_TOP_UNIVPLL2_D2		26
+#define CLK_TOP_UNIVPLL2_D4		27
+#define CLK_TOP_UNIVPLL2_D8		28
+#define CLK_TOP_UNIVPLL2_D32		29
+#define CLK_TOP_UNIVPLL_D5		30
+#define CLK_TOP_UNIVPLL3_D2		31
+#define CLK_TOP_UNIVPLL3_D4		32
+#define CLK_TOP_MMPLL			33
+#define CLK_TOP_MMPLL_D2		34
+#define CLK_TOP_MPLL			35
+#define CLK_TOP_DA_MPLL_104M_DIV	36
+#define CLK_TOP_DA_MPLL_52M_DIV		37
+#define CLK_TOP_MFGPLL			38
+#define CLK_TOP_MSDCPLL			39
+#define CLK_TOP_MSDCPLL_D2		40
+#define CLK_TOP_APLL1			41
+#define CLK_TOP_APLL1_D2		42
+#define CLK_TOP_APLL1_D4		43
+#define CLK_TOP_APLL1_D8		44
+#define CLK_TOP_ULPOSC1			45
+#define CLK_TOP_ULPOSC1_D2		46
+#define CLK_TOP_ULPOSC1_D4		47
+#define CLK_TOP_ULPOSC1_D8		48
+#define CLK_TOP_ULPOSC1_D16		49
+#define CLK_TOP_ULPOSC1_D32		50
+#define CLK_TOP_DMPLL			51
+#define CLK_TOP_F_FRTC			52
+#define CLK_TOP_F_F26M			53
+#define CLK_TOP_AXI			54
+#define CLK_TOP_MM			55
+#define CLK_TOP_SCP			56
+#define CLK_TOP_MFG			57
+#define CLK_TOP_F_FUART			58
+#define CLK_TOP_SPI			59
+#define CLK_TOP_MSDC50_0		60
+#define CLK_TOP_MSDC30_1		61
+#define CLK_TOP_AUDIO			62
+#define CLK_TOP_AUD_1			63
+#define CLK_TOP_AUD_ENGEN1		64
+#define CLK_TOP_F_FDISP_PWM		65
+#define CLK_TOP_SSPM			66
+#define CLK_TOP_DXCC			67
+#define CLK_TOP_I2C			68
+#define CLK_TOP_F_FPWM			69
+#define CLK_TOP_F_FSENINF		70
+#define CLK_TOP_AES_FDE			71
+#define CLK_TOP_F_BIST2FPC		72
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0	73
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1	74
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2	75
+#define CLK_TOP_DA_USB20_48M_DIV	76
+#define CLK_TOP_DA_UNIV_48M_DIV		77
+#define CLK_TOP_APLL12_DIV0		78
+#define CLK_TOP_APLL12_DIV1		79
+#define CLK_TOP_APLL12_DIV2		80
+#define CLK_TOP_APLL12_DIV3		81
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN	82
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN	83
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN	84
+#define CLK_TOP_FMEM_OCC_DRC_EN		85
+#define CLK_TOP_USB20_48M_EN		86
+#define CLK_TOP_UNIVPLL_48M_EN		87
+#define CLK_TOP_MPLL_104M_EN		88
+#define CLK_TOP_MPLL_52M_EN		89
+#define CLK_TOP_F_UFS_MP_SAP_CFG_EN	90
+#define CLK_TOP_F_BIST2FPC_EN		91
+#define CLK_TOP_MD_32K			92
+#define CLK_TOP_MD_26M			93
+#define CLK_TOP_MD2_32K			94
+#define CLK_TOP_MD2_26M			95
+#define CLK_TOP_AXI_SEL			96
+#define CLK_TOP_MEM_SEL			97
+#define CLK_TOP_MM_SEL			98
+#define CLK_TOP_SCP_SEL			99
+#define CLK_TOP_MFG_SEL			100
+#define CLK_TOP_ATB_SEL			101
+#define CLK_TOP_CAMTG_SEL		102
+#define CLK_TOP_CAMTG1_SEL		103
+#define CLK_TOP_CAMTG2_SEL		104
+#define CLK_TOP_CAMTG3_SEL		105
+#define CLK_TOP_UART_SEL		106
+#define CLK_TOP_SPI_SEL			107
+#define CLK_TOP_MSDC50_0_HCLK_SEL	108
+#define CLK_TOP_MSDC50_0_SEL		109
+#define CLK_TOP_MSDC30_1_SEL		110
+#define CLK_TOP_AUDIO_SEL		111
+#define CLK_TOP_AUD_INTBUS_SEL		112
+#define CLK_TOP_AUD_1_SEL		113
+#define CLK_TOP_AUD_ENGEN1_SEL		114
+#define CLK_TOP_DISP_PWM_SEL		115
+#define CLK_TOP_SSPM_SEL		116
+#define CLK_TOP_DXCC_SEL		117
+#define CLK_TOP_USB_TOP_SEL		118
+#define CLK_TOP_SPM_SEL			119
+#define CLK_TOP_I2C_SEL			120
+#define CLK_TOP_PWM_SEL			121
+#define CLK_TOP_SENINF_SEL		122
+#define CLK_TOP_AES_FDE_SEL		123
+#define CLK_TOP_PWRAP_ULPOSC_SEL	124
+#define CLK_TOP_CAMTM_SEL		125
+#define CLK_TOP_NR_CLK			126
+
+/* INFRACFG */
+#define CLK_IFR_TOPAXI_DISABLE			0
+#define CLK_IFR_PMIC_TMR			1
+#define CLK_IFR_PMIC_AP				2
+#define CLK_IFR_PMIC_MD				3
+#define CLK_IFR_PMIC_CONN			4
+#define CLK_IFR_SCP_CORE			5
+#define CLK_IFR_SEJ				6
+#define CLK_IFR_APXGPT				7
+#define CLK_IFR_ICUSB				8
+#define CLK_IFR_GCE				9
+#define CLK_IFR_THERM				10
+#define CLK_IFR_I2C_AP				11
+#define CLK_IFR_I2C_CCU				12
+#define CLK_IFR_I2C_SSPM			13
+#define CLK_IFR_I2C_RSV				14
+#define CLK_IFR_PWM_HCLK			15
+#define CLK_IFR_PWM1				16
+#define CLK_IFR_PWM2				17
+#define CLK_IFR_PWM3				18
+#define CLK_IFR_PWM4				19
+#define CLK_IFR_PWM5				20
+#define CLK_IFR_PWM				21
+#define CLK_IFR_UART0				22
+#define CLK_IFR_UART1				23
+#define CLK_IFR_GCE_26M				24
+#define CLK_IFR_CQ_DMA_FPC			25
+#define CLK_IFR_BTIF				26
+#define CLK_IFR_SPI0				27
+#define CLK_IFR_MSDC0				28
+#define CLK_IFR_MSDC1				29
+#define CLK_IFR_DVFSRC				30
+#define CLK_IFR_GCPU				31
+#define CLK_IFR_TRNG				32
+#define CLK_IFR_AUXADC				33
+#define CLK_IFR_CPUM				34
+#define CLK_IFR_CCIF1_AP			35
+#define CLK_IFR_CCIF1_MD			36
+#define CLK_IFR_AUXADC_MD			37
+#define CLK_IFR_AP_DMA				38
+#define CLK_IFR_XIU				39
+#define CLK_IFR_DEVICE_APC			40
+#define CLK_IFR_CCIF_AP				41
+#define CLK_IFR_DEBUGTOP			42
+#define CLK_IFR_AUDIO				43
+#define CLK_IFR_CCIF_MD				44
+#define CLK_IFR_DXCC_SEC_CORE			45
+#define CLK_IFR_DXCC_AO				46
+#define CLK_IFR_DRAMC_F26M			47
+#define CLK_IFR_RG_PWM_FBCLK6			48
+#define CLK_IFR_DISP_PWM			49
+#define CLK_IFR_CLDMA_BCLK			50
+#define CLK_IFR_AUDIO_26M_BCLK			51
+#define CLK_IFR_SPI1				52
+#define CLK_IFR_I2C4				53
+#define CLK_IFR_MODEM_TEMP_SHARE		54
+#define CLK_IFR_SPI2				55
+#define CLK_IFR_SPI3				56
+#define CLK_IFR_SSPM				57
+#define CLK_IFR_I2C5				58
+#define CLK_IFR_I2C5_ARBITER			59
+#define CLK_IFR_I2C5_IMM			60
+#define CLK_IFR_I2C1_ARBITER			61
+#define CLK_IFR_I2C1_IMM			62
+#define CLK_IFR_I2C2_ARBITER			63
+#define CLK_IFR_I2C2_IMM			64
+#define CLK_IFR_SPI4				65
+#define CLK_IFR_SPI5				66
+#define CLK_IFR_CQ_DMA				67
+#define CLK_IFR_FAES_FDE			68
+#define CLK_IFR_MSDC0_SELF			69
+#define CLK_IFR_MSDC1_SELF			70
+#define CLK_IFR_SSPM_26M_SELF			71
+#define CLK_IFR_SSPM_32K_SELF			72
+#define CLK_IFR_I2C6				73
+#define CLK_IFR_AP_MSDC0			74
+#define CLK_IFR_MD_MSDC0			75
+#define CLK_IFR_MSDC0_SRC			76
+#define CLK_IFR_MSDC1_SRC			77
+#define CLK_IFR_SEJ_F13M			78
+#define CLK_IFR_AES_TOP0_BCLK			79
+#define CLK_IFR_MCU_PM_BCLK			80
+#define CLK_IFR_CCIF2_AP			81
+#define CLK_IFR_CCIF2_MD			82
+#define CLK_IFR_CCIF3_AP			83
+#define CLK_IFR_CCIF3_MD			84
+#define CLK_IFR_PERI_DCM_RG_FORCE_CLKOFF	85
+#define CLK_IFR_NR_CLK				86
+
+/* PERICFG */
+#define CLK_PERIAXI_DISABLE		0
+#define CLK_PERI_NR_CLK			1
+
+/* GCE */
+#define CLK_GCE				0
+#define CLK_GCE_NR_CLK			1
+
+/* AUDIO */
+#define CLK_AUDIO_AFE			0
+#define CLK_AUDIO_22M			1
+#define CLK_AUDIO_APLL_TUNER		2
+#define CLK_AUDIO_ADC			3
+#define CLK_AUDIO_DAC			4
+#define CLK_AUDIO_DAC_PREDIS		5
+#define CLK_AUDIO_TML			6
+#define CLK_AUDIO_I2S1_BCLK		7
+#define CLK_AUDIO_I2S2_BCLK		8
+#define CLK_AUDIO_I2S3_BCLK		9
+#define CLK_AUDIO_I2S4_BCLK		10
+#define CLK_AUDIO_NR_CLK		11
+
+/* MIPI_RX_ANA_CSI0A */
+
+#define CLK_MIPI0A_CSR_CSI_EN_0A	0
+#define CLK_MIPI0A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI0B */
+
+#define CLK_MIPI0B_CSR_CSI_EN_0B	0
+#define CLK_MIPI0B_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI1A */
+
+#define CLK_MIPI1A_CSR_CSI_EN_1A	0
+#define CLK_MIPI1A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI1B */
+
+#define CLK_MIPI1B_CSR_CSI_EN_1B	0
+#define CLK_MIPI1B_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI2A */
+
+#define CLK_MIPI2A_CSR_CSI_EN_2A	0
+#define CLK_MIPI2A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI2B */
+
+#define CLK_MIPI2B_CSR_CSI_EN_2B	0
+#define CLK_MIPI2B_NR_CLK		1
+
+/* MFG */
+
+#define CLK_MFGCFG_BAXI			0
+#define CLK_MFGCFG_BMEM			1
+#define CLK_MFGCFG_BG3D			2
+#define CLK_MFGCFG_B26M			3
+#define CLK_MFGCFG_NR_CLK		4
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_MDP_RDMA0		0
+#define CLK_MM_MDP_CCORR0		1
+#define CLK_MM_MDP_RSZ0			2
+#define CLK_MM_MDP_RSZ1			3
+#define CLK_MM_MDP_TDSHP0		4
+#define CLK_MM_MDP_WROT0		5
+#define CLK_MM_MDP_WDMA0		6
+#define CLK_MM_DISP_OVL0		7
+#define CLK_MM_DISP_OVL0_2L		8
+#define CLK_MM_DISP_RSZ0		9
+#define CLK_MM_DISP_RDMA0		10
+#define CLK_MM_DISP_WDMA0		11
+#define CLK_MM_DISP_COLOR0		12
+#define CLK_MM_DISP_CCORR0		13
+#define CLK_MM_DISP_AAL0		14
+#define CLK_MM_DISP_GAMMA0		15
+#define CLK_MM_DISP_DITHER0		16
+#define CLK_MM_DSI0			17
+#define CLK_MM_FAKE_ENG			18
+#define CLK_MM_SMI_COMMON		19
+#define CLK_MM_SMI_LARB0		20
+#define CLK_MM_SMI_COMM0		21
+#define CLK_MM_SMI_COMM1		22
+#define CLK_MM_CAM_MDP			23
+#define CLK_MM_SMI_IMG			24
+#define CLK_MM_SMI_CAM			25
+#define CLK_MM_IMG_DL_RELAY		26
+#define CLK_MM_IMG_DL_ASYNC_TOP		27
+#define CLK_MM_DIG_DSI			28
+#define CLK_MM_F26M_HRTWT		29
+#define CLK_MM_NR_CLK			30
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB2			0
+#define CLK_IMG_DIP			1
+#define CLK_IMG_FDVT			2
+#define CLK_IMG_DPE			3
+#define CLK_IMG_RSC			4
+#define CLK_IMG_NR_CLK			5
+
+/* VENCSYS */
+
+#define CLK_VENC_SET0_LARB		0
+#define CLK_VENC_SET1_VENC		1
+#define CLK_VENC_SET2_JPGENC		2
+#define CLK_VENC_SET3_VDEC		3
+#define CLK_VENC_NR_CLK			4
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB3			0
+#define CLK_CAM_DFP_VAD			1
+#define CLK_CAM				2
+#define CLK_CAMTG			3
+#define CLK_CAM_SENINF			4
+#define CLK_CAMSV0			5
+#define CLK_CAMSV1			6
+#define CLK_CAMSV2			7
+#define CLK_CAM_CCU			8
+#define CLK_CAM_NR_CLK			9
+
+/* SCP_SYS */
+
+#define SCP_SYS_MD1		0
+#define SCP_SYS_CONN		1
+#define SCP_SYS_DPY		2
+#define SCP_SYS_DIS		3
+#define SCP_SYS_MFG		4
+#define SCP_SYS_ISP		5
+#define SCP_SYS_IFR		6
+#define SCP_SYS_MFG_CORE0	7
+#define SCP_SYS_MFG_ASYNC	8
+#define SCP_SYS_CAM		9
+#define SCP_SYS_VCODEC		10
+#define SCP_NR_SYSS		11
+
+#endif /* _DT_BINDINGS_CLK_MT6765_H */

include/dt-bindings/clock/mt6768-clk.h

@@ -0,0 +1,412 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+#ifndef _DT_BINDINGS_CLK_MT6768_H
+#define _DT_BINDINGS_CLK_MT6768_H
+
+/* FIX Clks */
+#define CLK_TOP_CLK26M			0
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_L		0
+#define CLK_APMIXED_ARMPLL		1
+#define CLK_APMIXED_CCIPLL		2
+#define CLK_APMIXED_MAINPLL		3
+#define CLK_APMIXED_MFGPLL		4
+#define CLK_APMIXED_MMPLL		5
+#define CLK_APMIXED_UNIV2PLL		6
+#define CLK_APMIXED_MSDCPLL		7
+#define CLK_APMIXED_APLL1		8
+#define CLK_APMIXED_MPLL		9
+#define CLK_APMIXED_ULPOSC1		10
+#define CLK_APMIXED_ULPOSC2		11
+#define CLK_APMIXED_SSUSB26M		12
+#define CLK_APMIXED_APPLL26M		13
+#define CLK_APMIXED_MIPIC0_26M		14
+#define CLK_APMIXED_MDPLLGP26M		15
+#define CLK_APMIXED_MMSYS_F26M		16
+#define CLK_APMIXED_UFS26M		17
+#define CLK_APMIXED_MIPIC1_26M		18
+#define CLK_APMIXED_MEMPLL26M		19
+#define CLK_APMIXED_CLKSQ_LVPLL_26M	20
+#define CLK_APMIXED_MIPID0_26M		21
+#define CLK_APMIXED_NR_CLK		22
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL			0
+#define CLK_TOP_SYSPLL_D2		1
+#define CLK_TOP_SYSPLL1_D2		2
+#define CLK_TOP_SYSPLL1_D4		3
+#define CLK_TOP_SYSPLL1_D8		4
+#define CLK_TOP_SYSPLL1_D16		5
+#define CLK_TOP_SYSPLL_D3		6
+#define CLK_TOP_SYSPLL2_D2		7
+#define CLK_TOP_SYSPLL2_D4		8
+#define CLK_TOP_SYSPLL2_D8		9
+#define CLK_TOP_SYSPLL_D5		10
+#define CLK_TOP_SYSPLL3_D2		11
+#define CLK_TOP_SYSPLL3_D4		12
+#define CLK_TOP_SYSPLL_D7		13
+#define CLK_TOP_SYSPLL4_D2		14
+#define CLK_TOP_SYSPLL4_D4		15
+#define CLK_TOP_USB20_192M		16
+#define CLK_TOP_USB20_192M_D4		17
+#define CLK_TOP_USB20_192M_D8		18
+#define CLK_TOP_USB20_192M_D16		19
+#define CLK_TOP_USB20_192M_D32		20
+#define CLK_TOP_UNIVPLL			21
+#define CLK_TOP_UNIVPLL_D2		22
+#define CLK_TOP_UNIVPLL1_D2		23
+#define CLK_TOP_UNIVPLL1_D4		24
+#define CLK_TOP_UNIVPLL_D3		25
+#define CLK_TOP_UNIVPLL2_D2		26
+#define CLK_TOP_UNIVPLL2_D4		27
+#define CLK_TOP_UNIVPLL2_D8		28
+#define CLK_TOP_UNIVPLL2_D32		29
+#define CLK_TOP_UNIVPLL_D5		30
+#define CLK_TOP_UNIVPLL3_D2		31
+#define CLK_TOP_UNIVPLL3_D4		32
+#define CLK_TOP_MMPLL			33
+#define CLK_TOP_MMPLL_D2		34
+#define CLK_TOP_MPLL			35
+#define CLK_TOP_DA_MPLL_104M_DIV	36
+#define CLK_TOP_DA_MPLL_52M_DIV		37
+#define CLK_TOP_MFGPLL			38
+#define CLK_TOP_MSDCPLL			39
+#define CLK_TOP_MSDCPLL_D2		40
+#define CLK_TOP_APLL1			41
+#define CLK_TOP_APLL1_D2		42
+#define CLK_TOP_APLL1_D4		43
+#define CLK_TOP_APLL1_D8		44
+#define CLK_TOP_ULPOSC1			45
+#define CLK_TOP_ULPOSC1_D2		46
+#define CLK_TOP_ULPOSC1_D4		47
+#define CLK_TOP_ULPOSC1_D8		48
+#define CLK_TOP_ULPOSC1_D16		49
+#define CLK_TOP_ULPOSC1_D32		50
+#define CLK_TOP_DMPLL			51
+#define CLK_TOP_F_FRTC			52
+#define CLK_TOP_F_F26M			53
+#define CLK_TOP_AXI			54
+#define CLK_TOP_MM			55
+#define CLK_TOP_SCP			56
+#define CLK_TOP_MFG			57
+#define CLK_TOP_F_FUART			58
+#define CLK_TOP_SPI			59
+#define CLK_TOP_MSDC50_0		60
+#define CLK_TOP_MSDC30_1		61
+#define CLK_TOP_AUDIO			62
+#define CLK_TOP_AUD_1			63
+#define CLK_TOP_AUD_ENGEN1		64
+#define CLK_TOP_F_FDISP_PWM		65
+#define CLK_TOP_SSPM			66
+#define CLK_TOP_DXCC			67
+#define CLK_TOP_I2C			68
+#define CLK_TOP_F_FPWM			69
+#define CLK_TOP_F_FSENINF		70
+#define CLK_TOP_AES_FDE			71
+#define CLK_TOP_VENC			72
+#define CLK_TOP_CAM			73
+#define CLK_TOP_F_BIST2FPC		74
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0	75
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1	76
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2	77
+#define CLK_TOP_DA_USB20_48M_DIV	78
+#define CLK_TOP_DA_UNIV_48M_DIV		79
+#define CLK_TOP_AXI_SEL			80
+#define CLK_TOP_MEM_SEL			81
+#define CLK_TOP_MM_SEL			82
+#define CLK_TOP_SCP_SEL			83
+#define CLK_TOP_MFG_SEL			84
+#define CLK_TOP_ATB_SEL			85
+#define CLK_TOP_CAMTG_SEL		86
+#define CLK_TOP_CAMTG1_SEL		87
+#define CLK_TOP_CAMTG2_SEL		88
+#define CLK_TOP_CAMTG3_SEL		89
+#define CLK_TOP_UART_SEL		90
+#define CLK_TOP_SPI_SEL			91
+#define CLK_TOP_MSDC50_0_HCLK_SEL	92
+#define CLK_TOP_MSDC50_0_SEL		93
+#define CLK_TOP_MSDC30_1_SEL		94
+#define CLK_TOP_AUDIO_SEL		95
+#define CLK_TOP_AUD_INTBUS_SEL		96
+#define CLK_TOP_AUD_1_SEL		97
+#define CLK_TOP_AUD_ENGEN1_SEL		98
+#define CLK_TOP_DISP_PWM_SEL		99
+#define CLK_TOP_SSPM_SEL		100
+#define CLK_TOP_DXCC_SEL		101
+#define CLK_TOP_USB_TOP_SEL		102
+#define CLK_TOP_SPM_SEL			103
+#define CLK_TOP_I2C_SEL			104
+#define CLK_TOP_PWM_SEL			105
+#define CLK_TOP_SENINF_SEL		106
+#define CLK_TOP_AES_FDE_SEL		107
+#define CLK_TOP_PWRAP_ULPOSC_SEL	108
+#define CLK_TOP_CAMTM_SEL		109
+#define CLK_TOP_VENC_SEL		110
+#define CLK_TOP_CAM_SEL			111
+#define CLK_TOP_APLL12_DIV0		112
+#define CLK_TOP_APLL12_DIV1		113
+#define CLK_TOP_APLL12_DIV2		114
+#define CLK_TOP_APLL12_DIV3		115
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN	116
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN	117
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN	118
+#define CLK_TOP_FMEM_OCC_DRC_EN		119
+#define CLK_TOP_USB20_48M_EN		120
+#define CLK_TOP_UNIVPLL_48M_EN		121
+#define CLK_TOP_MPLL_104M_EN		122
+#define CLK_TOP_MPLL_52M_EN		123
+#define CLK_TOP_F_UFS_MP_SAP_CFG_EN	124
+#define CLK_TOP_F_BIST2FPC_EN		125
+#define CLK_TOP_MD_32K			126
+#define CLK_TOP_MD_26M			127
+#define CLK_TOP_MD2_32K			128
+#define CLK_TOP_MD2_26M			129
+#define CLK_TOP_I2S0_M_SEL		130
+#define CLK_TOP_I2S1_M_SEL		131
+#define CLK_TOP_I2S2_M_SEL		132
+#define CLK_TOP_I2S3_M_SEL		133
+#define CLK_TOP_CLK13M			134
+#define CLK_TOP_MSDC50_0_HCLK		135
+#define CLK_TOP_NR_CLK			136
+
+/* INFRACFG */
+#define CLK_IFR_TOPAXI_DISABLE			0
+#define CLK_IFR_PMIC_TMR			1
+#define CLK_IFR_PMIC_AP				2
+#define CLK_IFR_PMIC_MD				3
+#define CLK_IFR_PMIC_CONN			4
+#define CLK_IFR_SCP_CORE			5
+#define CLK_IFR_SEJ				6
+#define CLK_IFR_APXGPT				7
+#define CLK_IFR_ICUSB				8
+#define CLK_IFR_GCE				9
+#define CLK_IFR_THERM				10
+#define CLK_IFR_I2C_AP				11
+#define CLK_IFR_I2C_CCU				12
+#define CLK_IFR_I2C_SSPM			13
+#define CLK_IFR_I2C_RSV				14
+#define CLK_IFR_PWM_HCLK			15
+#define CLK_IFR_PWM1				16
+#define CLK_IFR_PWM2				17
+#define CLK_IFR_PWM3				18
+#define CLK_IFR_PWM4				19
+#define CLK_IFR_PWM5				20
+#define CLK_IFR_PWM				21
+#define CLK_IFR_UART0				22
+#define CLK_IFR_UART1				23
+#define CLK_IFR_GCE_26M				24
+#define CLK_IFR_CQ_DMA_FPC			25
+#define CLK_IFR_BTIF				26
+#define CLK_IFR_SPI0				27
+#define CLK_IFR_MSDC0				28
+#define CLK_IFR_MSDC1				29
+#define CLK_IFR_DVFSRC				30
+#define CLK_IFR_GCPU				31
+#define CLK_IFR_TRNG				32
+#define CLK_IFR_AUXADC				33
+#define CLK_IFR_CPUM				34
+#define CLK_IFR_CCIF1_AP			35
+#define CLK_IFR_CCIF1_MD			36
+#define CLK_IFR_AUXADC_MD			37
+#define CLK_IFR_AP_DMA				38
+#define CLK_IFR_XIU				39
+#define CLK_IFR_DEVICE_APC			40
+#define CLK_IFR_CCIF_AP				41
+#define CLK_IFR_DEBUGTOP			42
+#define CLK_IFR_AUDIO				43
+#define CLK_IFR_CCIF_MD				44
+#define CLK_IFR_DXCC_SEC_CORE			45
+#define CLK_IFR_DXCC_AO				46
+#define CLK_IFR_DRAMC_F26M			47
+#define CLK_IFR_RG_PWM_FBCLK6			48
+#define CLK_IFR_DISP_PWM			49
+#define CLK_IFR_CLDMA_BCLK			50
+#define CLK_IFR_AUDIO_26M_BCLK			51
+#define CLK_IFR_SPI1				52
+#define CLK_IFR_I2C4				53
+#define CLK_IFR_MODEM_TEMP_SHARE		54
+#define CLK_IFR_SPI2				55
+#define CLK_IFR_SPI3				56
+#define CLK_IFR_SSPM				57
+#define CLK_IFR_I2C5				58
+#define CLK_IFR_I2C5_ARBITER			59
+#define CLK_IFR_I2C5_IMM			60
+#define CLK_IFR_I2C1_ARBITER			61
+#define CLK_IFR_I2C1_IMM			62
+#define CLK_IFR_I2C2_ARBITER			63
+#define CLK_IFR_I2C2_IMM			64
+#define CLK_IFR_SPI4				65
+#define CLK_IFR_SPI5				66
+#define CLK_IFR_CQ_DMA				67
+#define CLK_IFR_FAES_FDE			68
+#define CLK_IFR_MSDC0_SELF			69
+#define CLK_IFR_MSDC1_SELF			70
+#define CLK_IFR_SSPM_26M_SELF			71
+#define CLK_IFR_SSPM_32K_SELF			72
+#define CLK_IFR_I2C6				73
+#define CLK_IFR_AP_MSDC0			74
+#define CLK_IFR_MD_MSDC0			75
+#define CLK_IFR_MSDC0_SRC			76
+#define CLK_IFR_MSDC1_SRC			77
+#define CLK_IFR_SEJ_F13M			78
+#define CLK_IFR_AES_TOP0_BCLK			79
+#define CLK_IFR_MCU_PM_BCLK			80
+#define CLK_IFR_CCIF2_AP			81
+#define CLK_IFR_CCIF2_MD			82
+#define CLK_IFR_CCIF3_AP			83
+#define CLK_IFR_CCIF3_MD			84
+#define CLK_IFR_PERI_DCM_RG_FORCE_CLKOFF	85
+#define CLK_IFR_NR_CLK				86
+
+/* PERICFG */
+#define CLK_PERIAXI_DISABLE		0
+#define CLK_PERI_NR_CLK			1
+
+/* GCE */
+#define CLK_GCE				0
+#define CLK_GCE_NR_CLK			1
+
+/* AUDIO */
+#define CLK_AUDIO_AFE			0
+#define CLK_AUDIO_22M			1
+#define CLK_AUDIO_24M			2
+#define CLK_AUDIO_APLL_TUNER		3
+#define CLK_AUDIO_ADC			4
+#define CLK_AUDIO_DAC			5
+#define CLK_AUDIO_DAC_PREDIS		6
+#define CLK_AUDIO_TML			7
+#define CLK_AUDIO_I2S1_BCLK		8
+#define CLK_AUDIO_I2S2_BCLK		9
+#define CLK_AUDIO_I2S3_BCLK		10
+#define CLK_AUDIO_I2S4_BCLK		11
+#define CLK_AUDIO_NR_CLK		12
+
+/* MIPI_RX_ANA_CSI0A */
+
+#define CLK_MIPI0A_CSR_CSI_EN_0A	0
+#define CLK_MIPI0A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI0B */
+
+#define CLK_MIPI0B_CSR_CSI_EN_0B	0
+#define CLK_MIPI0B_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI1A */
+
+#define CLK_MIPI1A_CSR_CSI_EN_1A	0
+#define CLK_MIPI1A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI1B */
+
+#define CLK_MIPI1B_CSR_CSI_EN_1B	0
+#define CLK_MIPI1B_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI2A */
+
+#define CLK_MIPI2A_CSR_CSI_EN_2A	0
+#define CLK_MIPI2A_NR_CLK		1
+
+/* MIPI_RX_ANA_CSI2B */
+
+#define CLK_MIPI2B_CSR_CSI_EN_2B	0
+#define CLK_MIPI2B_NR_CLK		1
+
+/* MFG */
+
+#define CLK_MFGCFG_BG3D			0
+#define CLK_MFGCFG_NR_CLK		1
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_MDP_RDMA0		0
+#define CLK_MM_MDP_CCORR0		1
+#define CLK_MM_MDP_RSZ0			2
+#define CLK_MM_MDP_RSZ1			3
+#define CLK_MM_MDP_TDSHP0		4
+#define CLK_MM_MDP_WROT0		5
+#define CLK_MM_MDP_WDMA0		6
+#define CLK_MM_DISP_OVL0		7
+#define CLK_MM_DISP_OVL0_2L		8
+#define CLK_MM_DISP_RSZ0		9
+#define CLK_MM_DISP_RDMA0		10
+#define CLK_MM_DISP_WDMA0		11
+#define CLK_MM_DISP_COLOR0		12
+#define CLK_MM_DISP_CCORR0		13
+#define CLK_MM_DISP_AAL0		14
+#define CLK_MM_DISP_GAMMA0		15
+#define CLK_MM_DISP_DITHER0		16
+#define CLK_MM_DSI0			17
+#define CLK_MM_FAKE_ENG			18
+#define CLK_MM_SMI_COMMON		19
+#define CLK_MM_SMI_LARB0		20
+#define CLK_MM_SMI_COMM0		21
+#define CLK_MM_SMI_COMM1		22
+#define CLK_MM_CAM_MDP			23
+#define CLK_MM_SMI_IMG			24
+#define CLK_MM_SMI_CAM			25
+#define CLK_MM_SMI_VENC			26
+#define CLK_MM_SMI_VDEC			27
+#define CLK_MM_IMG_DL_RELAY		28
+#define CLK_MM_IMG_DL_ASYNC_TOP		29
+#define CLK_MM_DIG_DSI			30
+#define CLK_MM_F26M_HRTWT		31
+#define CLK_MM_NR_CLK			32
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB2			0
+#define CLK_IMG_DIP			1
+#define CLK_IMG_FDVT			2
+#define CLK_IMG_DPE			3
+#define CLK_IMG_RSC			4
+#define CLK_IMG_NR_CLK			5
+
+/* VENCSYS */
+
+#define CLK_VENC_SET0_LARB		0
+#define CLK_VENC_SET1_VENC		1
+#define CLK_VENC_SET2_JPGENC		2
+#define CLK_VENC_NR_CLK			3
+
+/* VDECSYS, add for mt6768 */
+
+#define CLK_VDEC_CKEN			0
+#define CLK_VDEC_ACTIVE			1
+#define CLK_VDEC_CKEN_ENG		2
+#define CLK_VDEC_LARB1_CKEN		3
+#define CLK_VDEC_NR_CLK			4
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB3			0
+#define CLK_CAM_DFP_VAD			1
+#define CLK_CAM				2
+#define CLK_CAMTG			3
+#define CLK_CAM_SENINF			4
+#define CLK_CAMSV0			5
+#define CLK_CAMSV1			6
+#define CLK_CAMSV2			7
+#define CLK_CAM_CCU			8
+#define CLK_CAM_NR_CLK			9
+
+/* SCP_SYS */
+
+#define SCP_SYS_MD1		0
+#define SCP_SYS_CONN		1
+#define SCP_SYS_DPY		2
+#define SCP_SYS_DIS		3
+#define SCP_SYS_MFG		4
+#define SCP_SYS_ISP		5
+#define SCP_SYS_IFR		6
+#define SCP_SYS_MFG_CORE0	7
+#define SCP_SYS_MFG_CORE1	8
+#define SCP_SYS_MFG_ASYNC	9
+#define SCP_SYS_CAM		10
+#define SCP_SYS_VENC		11
+#define SCP_SYS_VDEC		12
+#define SCP_NR_SYSS		13
+#endif /* _DT_BINDINGS_CLK_MT6768_H */

include/dt-bindings/clock/mt6779-clk.h

@@ -0,0 +1,993 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6779_H
+#define _DT_BINDINGS_CLK_MT6779_H
+
+/* TOPCKGEN */
+#define CLK_TOP_AXI			1
+#define CLK_TOP_MM			2
+#define CLK_TOP_CAM			3
+#define CLK_TOP_MFG			4
+#define CLK_TOP_CAMTG			5
+#define CLK_TOP_UART			6
+#define CLK_TOP_SPI			7
+#define CLK_TOP_MSDC50_0_HCLK		8
+#define CLK_TOP_MSDC50_0		9
+#define CLK_TOP_MSDC30_1		10
+#define CLK_TOP_MSDC30_2		11
+#define CLK_TOP_AUD			12
+#define CLK_TOP_AUD_INTBUS		13
+#define CLK_TOP_FPWRAP_ULPOSC		14
+#define CLK_TOP_SCP			15
+#define CLK_TOP_ATB			16
+#define CLK_TOP_SSPM			17
+#define CLK_TOP_DPI0			18
+#define CLK_TOP_SCAM			19
+#define CLK_TOP_AUD_1			20
+#define CLK_TOP_AUD_2			21
+#define CLK_TOP_DISP_PWM		22
+#define CLK_TOP_SSUSB_TOP_XHCI		23
+#define CLK_TOP_USB_TOP			24
+#define CLK_TOP_SPM			25
+#define CLK_TOP_I2C			26
+#define CLK_TOP_F52M_MFG		27
+#define CLK_TOP_SENINF			28
+#define CLK_TOP_DXCC			29
+#define CLK_TOP_CAMTG2			30
+#define CLK_TOP_AUD_ENG1		31
+#define CLK_TOP_AUD_ENG2		32
+#define CLK_TOP_FAES_UFSFDE		33
+#define CLK_TOP_FUFS			34
+#define CLK_TOP_IMG			35
+#define CLK_TOP_DSP			36
+#define CLK_TOP_DSP1			37
+#define CLK_TOP_DSP2			38
+#define CLK_TOP_IPU_IF			39
+#define CLK_TOP_CAMTG3			40
+#define CLK_TOP_CAMTG4			41
+#define CLK_TOP_PMICSPI			42
+#define CLK_TOP_MAINPLL_CK		43
+#define CLK_TOP_MAINPLL_D2		44
+#define CLK_TOP_MAINPLL_D3		45
+#define CLK_TOP_MAINPLL_D5		46
+#define CLK_TOP_MAINPLL_D7		47
+#define CLK_TOP_MAINPLL_D2_D2		48
+#define CLK_TOP_MAINPLL_D2_D4		49
+#define CLK_TOP_MAINPLL_D2_D8		50
+#define CLK_TOP_MAINPLL_D2_D16		51
+#define CLK_TOP_MAINPLL_D3_D2		52
+#define CLK_TOP_MAINPLL_D3_D4		53
+#define CLK_TOP_MAINPLL_D3_D8		54
+#define CLK_TOP_MAINPLL_D5_D2		55
+#define CLK_TOP_MAINPLL_D5_D4		56
+#define CLK_TOP_MAINPLL_D7_D2		57
+#define CLK_TOP_MAINPLL_D7_D4		58
+#define CLK_TOP_UNIVPLL_CK		59
+#define CLK_TOP_UNIVPLL_D2		60
+#define CLK_TOP_UNIVPLL_D3		61
+#define CLK_TOP_UNIVPLL_D5		62
+#define CLK_TOP_UNIVPLL_D7		63
+#define CLK_TOP_UNIVPLL_D2_D2		64
+#define CLK_TOP_UNIVPLL_D2_D4		65
+#define CLK_TOP_UNIVPLL_D2_D8		66
+#define CLK_TOP_UNIVPLL_D3_D2		67
+#define CLK_TOP_UNIVPLL_D3_D4		68
+#define CLK_TOP_UNIVPLL_D3_D8		69
+#define CLK_TOP_UNIVPLL_D5_D2		70
+#define CLK_TOP_UNIVPLL_D5_D4		71
+#define CLK_TOP_UNIVPLL_D5_D8		72
+#define CLK_TOP_APLL1_CK		73
+#define CLK_TOP_APLL1_D2		74
+#define CLK_TOP_APLL1_D4		75
+#define CLK_TOP_APLL1_D8		76
+#define CLK_TOP_APLL2_CK		77
+#define CLK_TOP_APLL2_D2		78
+#define CLK_TOP_APLL2_D4		79
+#define CLK_TOP_APLL2_D8		80
+#define CLK_TOP_TVDPLL_CK		81
+#define CLK_TOP_TVDPLL_D2		82
+#define CLK_TOP_TVDPLL_D4		83
+#define CLK_TOP_TVDPLL_D8		84
+#define CLK_TOP_TVDPLL_D16		85
+#define CLK_TOP_MSDCPLL_CK		86
+#define CLK_TOP_MSDCPLL_D2		87
+#define CLK_TOP_MSDCPLL_D4		88
+#define CLK_TOP_MSDCPLL_D8		89
+#define CLK_TOP_MSDCPLL_D16		90
+#define CLK_TOP_AD_OSC_CK		91
+#define CLK_TOP_OSC_D2			92
+#define CLK_TOP_OSC_D4			93
+#define CLK_TOP_OSC_D8			94
+#define CLK_TOP_OSC_D16			95
+#define CLK_TOP_F26M_CK_D2		96
+#define CLK_TOP_MFGPLL_CK		97
+#define CLK_TOP_UNIVP_192M_CK		98
+#define CLK_TOP_UNIVP_192M_D2		99
+#define CLK_TOP_UNIVP_192M_D4		100
+#define CLK_TOP_UNIVP_192M_D8		101
+#define CLK_TOP_UNIVP_192M_D16		102
+#define CLK_TOP_UNIVP_192M_D32		103
+#define CLK_TOP_MMPLL_CK		104
+#define CLK_TOP_MMPLL_D4		105
+#define CLK_TOP_MMPLL_D4_D2		106
+#define CLK_TOP_MMPLL_D4_D4		107
+#define CLK_TOP_MMPLL_D5		108
+#define CLK_TOP_MMPLL_D5_D2		109
+#define CLK_TOP_MMPLL_D5_D4		110
+#define CLK_TOP_MMPLL_D6		111
+#define CLK_TOP_MMPLL_D7		112
+#define CLK_TOP_CLK26M			113
+#define CLK_TOP_CLK13M			114
+#define CLK_TOP_ADSP			115
+#define CLK_TOP_DPMAIF			116
+#define CLK_TOP_VENC			117
+#define CLK_TOP_VDEC			118
+#define CLK_TOP_CAMTM			119
+#define CLK_TOP_PWM			120
+#define CLK_TOP_ADSPPLL_CK		121
+#define CLK_TOP_I2S0_M_SEL		122
+#define CLK_TOP_I2S1_M_SEL		123
+#define CLK_TOP_I2S2_M_SEL		124
+#define CLK_TOP_I2S3_M_SEL		125
+#define CLK_TOP_I2S4_M_SEL		126
+#define CLK_TOP_I2S5_M_SEL		127
+#define CLK_TOP_APLL12_DIV0		128
+#define CLK_TOP_APLL12_DIV1		129
+#define CLK_TOP_APLL12_DIV2		130
+#define CLK_TOP_APLL12_DIV3		131
+#define CLK_TOP_APLL12_DIV4		132
+#define CLK_TOP_APLL12_DIVB		133
+#define CLK_TOP_APLL12_DIV5		134
+#define CLK_TOP_IPE			135
+#define CLK_TOP_DPE			136
+#define CLK_TOP_CCU			137
+#define CLK_TOP_DSP3			138
+#define CLK_TOP_SENINF1			139
+#define CLK_TOP_SENINF2			140
+#define CLK_TOP_AUD_H			141
+#define CLK_TOP_CAMTG5			142
+#define CLK_TOP_TVDPLL_MAINPLL_D2_CK	143
+#define CLK_TOP_AD_OSC2_CK		144
+#define CLK_TOP_OSC2_D2			145
+#define CLK_TOP_OSC2_D3			146
+#define CLK_TOP_FMEM_466M_CK		147
+#define CLK_TOP_ADSPPLL_D4		148
+#define CLK_TOP_ADSPPLL_D5		149
+#define CLK_TOP_ADSPPLL_D6		150
+#define CLK_TOP_OSC_D10			151
+#define CLK_TOP_UNIVPLL_D3_D16		152
+#define CLK_TOP_NR_CLK			153
+
+/* APMIXED */
+#define CLK_APMIXED_ARMPLL_LL		1
+#define CLK_APMIXED_ARMPLL_BL		2
+#define CLK_APMIXED_ARMPLL_BB		3
+#define CLK_APMIXED_CCIPLL		4
+#define CLK_APMIXED_MAINPLL		5
+#define CLK_APMIXED_UNIV2PLL		6
+#define CLK_APMIXED_MSDCPLL		7
+#define CLK_APMIXED_ADSPPLL		8
+#define CLK_APMIXED_MMPLL		9
+#define CLK_APMIXED_MFGPLL		10
+#define CLK_APMIXED_TVDPLL		11
+#define CLK_APMIXED_APLL1		12
+#define CLK_APMIXED_APLL2		13
+#define CLK_APMIXED_SSUSB26M		14
+#define CLK_APMIXED_APPLL26M		15
+#define CLK_APMIXED_MIPIC0_26M		16
+#define CLK_APMIXED_MDPLLGP26M		17
+#define CLK_APMIXED_MM_F26M		18
+#define CLK_APMIXED_UFS26M		19
+#define CLK_APMIXED_MIPIC1_26M		20
+#define CLK_APMIXED_MEMPLL26M		21
+#define CLK_APMIXED_CLKSQ_LVPLL_26M	22
+#define CLK_APMIXED_MIPID0_26M		23
+#define CLK_APMIXED_MIPID1_26M		24
+#define CLK_APMIXED_NR_CLK		25
+
+/* CAMSYS */
+#define CLK_CAM_LARB10			1
+#define CLK_CAM_DFP_VAD			2
+#define CLK_CAM_LARB11			3
+#define CLK_CAM_LARB9			4
+#define CLK_CAM_CAM			5
+#define CLK_CAM_CAMTG			6
+#define CLK_CAM_SENINF			7
+#define CLK_CAM_CAMSV0			8
+#define CLK_CAM_CAMSV1			9
+#define CLK_CAM_CAMSV2			10
+#define CLK_CAM_CAMSV3			11
+#define CLK_CAM_CCU			12
+#define CLK_CAM_FAKE_ENG		13
+#define CLK_CAM_NR_CLK			14
+
+/* INFRA */
+#define CLK_INFRA_PMIC_TMR		1
+#define CLK_INFRA_PMIC_AP		2
+#define CLK_INFRA_PMIC_MD		3
+#define CLK_INFRA_PMIC_CONN		4
+#define CLK_INFRA_SCPSYS		5
+#define CLK_INFRA_SEJ			6
+#define CLK_INFRA_APXGPT		7
+#define CLK_INFRA_ICUSB			8
+#define CLK_INFRA_GCE			9
+#define CLK_INFRA_THERM			10
+#define CLK_INFRA_I2C0			11
+#define CLK_INFRA_I2C1			12
+#define CLK_INFRA_I2C2			13
+#define CLK_INFRA_I2C3			14
+#define CLK_INFRA_PWM_HCLK		15
+#define CLK_INFRA_PWM1			16
+#define CLK_INFRA_PWM2			17
+#define CLK_INFRA_PWM3			18
+#define CLK_INFRA_PWM4			19
+#define CLK_INFRA_PWM			20
+#define CLK_INFRA_UART0			21
+#define CLK_INFRA_UART1			22
+#define CLK_INFRA_UART2			23
+#define CLK_INFRA_UART3			24
+#define CLK_INFRA_GCE_26M		25
+#define CLK_INFRA_CQ_DMA_FPC		26
+#define CLK_INFRA_BTIF			27
+#define CLK_INFRA_SPI0			28
+#define CLK_INFRA_MSDC0			29
+#define CLK_INFRA_MSDC1			30
+#define CLK_INFRA_MSDC2			31
+#define CLK_INFRA_MSDC0_SCK		32
+#define CLK_INFRA_DVFSRC		33
+#define CLK_INFRA_GCPU			34
+#define CLK_INFRA_TRNG			35
+#define CLK_INFRA_AUXADC		36
+#define CLK_INFRA_CPUM			37
+#define CLK_INFRA_CCIF1_AP		38
+#define CLK_INFRA_CCIF1_MD		39
+#define CLK_INFRA_AUXADC_MD		40
+#define CLK_INFRA_MSDC1_SCK		41
+#define CLK_INFRA_MSDC2_SCK		42
+#define CLK_INFRA_AP_DMA		43
+#define CLK_INFRA_XIU			44
+#define CLK_INFRA_DEVICE_APC		45
+#define CLK_INFRA_CCIF_AP		46
+#define CLK_INFRA_DEBUGSYS		47
+#define CLK_INFRA_AUD			48
+#define CLK_INFRA_CCIF_MD		49
+#define CLK_INFRA_DXCC_SEC_CORE		50
+#define CLK_INFRA_DXCC_AO		51
+#define CLK_INFRA_DRAMC_F26M		52
+#define CLK_INFRA_IRTX			53
+#define CLK_INFRA_DISP_PWM		54
+#define CLK_INFRA_DPMAIF_CK		55
+#define CLK_INFRA_AUD_26M_BCLK_CK	56
+#define CLK_INFRA_SPI1			57
+#define CLK_INFRA_I2C4			58
+#define CLK_INFRA_MODEM_TEMP_SHARE	59
+#define CLK_INFRA_SPI2			60
+#define CLK_INFRA_SPI3			61
+#define CLK_INFRA_UNIPRO_SCK		62
+#define CLK_INFRA_UNIPRO_TICK		63
+#define CLK_INFRA_UFS_MP_SAP_BCLK	64
+#define CLK_INFRA_MD32_BCLK		65
+#define CLK_INFRA_SSPM			66
+#define CLK_INFRA_UNIPRO_MBIST		67
+#define CLK_INFRA_SSPM_BUS_HCLK		68
+#define CLK_INFRA_I2C5			69
+#define CLK_INFRA_I2C5_ARBITER		70
+#define CLK_INFRA_I2C5_IMM		71
+#define CLK_INFRA_I2C1_ARBITER		72
+#define CLK_INFRA_I2C1_IMM		73
+#define CLK_INFRA_I2C2_ARBITER		74
+#define CLK_INFRA_I2C2_IMM		75
+#define CLK_INFRA_SPI4			76
+#define CLK_INFRA_SPI5			77
+#define CLK_INFRA_CQ_DMA		78
+#define CLK_INFRA_UFS			79
+#define CLK_INFRA_AES_UFSFDE		80
+#define CLK_INFRA_UFS_TICK		81
+#define CLK_INFRA_MSDC0_SELF		82
+#define CLK_INFRA_MSDC1_SELF		83
+#define CLK_INFRA_MSDC2_SELF		84
+#define CLK_INFRA_SSPM_26M_SELF		85
+#define CLK_INFRA_SSPM_32K_SELF		86
+#define CLK_INFRA_UFS_AXI		87
+#define CLK_INFRA_I2C6			88
+#define CLK_INFRA_AP_MSDC0		89
+#define CLK_INFRA_MD_MSDC0		90
+#define CLK_INFRA_USB			91
+#define CLK_INFRA_DEVMPU_BCLK		92
+#define CLK_INFRA_CCIF2_AP		93
+#define CLK_INFRA_CCIF2_MD		94
+#define CLK_INFRA_CCIF3_AP		95
+#define CLK_INFRA_CCIF3_MD		96
+#define CLK_INFRA_SEJ_F13M		97
+#define CLK_INFRA_AES_BCLK		98
+#define CLK_INFRA_I2C7			99
+#define CLK_INFRA_I2C8			100
+#define CLK_INFRA_FBIST2FPC		101
+#define CLK_INFRA_CCIF4_AP		102
+#define CLK_INFRA_CCIF4_MD		103
+#define CLK_INFRA_FADSP			104
+#define CLK_INFRA_SSUSB_XHCI		105
+#define CLK_INFRA_SPI6			106
+#define CLK_INFRA_SPI7			107
+#define CLK_INFRA_NR_CLK		108
+
+/* MFGCFG */
+#define CLK_MFGCFG_BG3D			1
+#define CLK_MFGCFG_NR_CLK		2
+
+/* IMG */
+#define	CLK_IMG_WPE_A			1
+#define	CLK_IMG_MFB			2
+#define	CLK_IMG_DIP			3
+#define	CLK_IMG_LARB6			4
+#define	CLK_IMG_LARB5			5
+#define CLK_IMG_NR_CLK			6
+
+/* IPE */
+#define	CLK_IPE_LARB7			1
+#define	CLK_IPE_LARB8			2
+#define	CLK_IPE_SMI_SUBCOM		3
+#define	CLK_IPE_FD			4
+#define	CLK_IPE_FE			5
+#define CLK_IPE_RSC			6
+#define CLK_IPE_DPE			7
+#define CLK_IPE_NR_CLK			8
+
+/* MM_CONFIG */
+#define	CLK_MM_SMI_COMMON		1
+#define	CLK_MM_SMI_LARB0		2
+#define	CLK_MM_SMI_LARB1		3
+#define	CLK_MM_GALS_COMM0		4
+#define	CLK_MM_GALS_COMM1		5
+#define	CLK_MM_GALS_CCU2MM		6
+#define	CLK_MM_GALS_IPU12MM		7
+#define	CLK_MM_GALS_IMG2MM		8
+#define	CLK_MM_GALS_CAM2MM		9
+#define	CLK_MM_GALS_IPU2MM		10
+#define	CLK_MM_MDP_DL_TXCK		11
+#define	CLK_MM_IPU_DL_TXCK		12
+#define	CLK_MM_MDP_RDMA0		13
+#define	CLK_MM_MDP_RDMA1		14
+#define	CLK_MM_MDP_RSZ0			15
+#define	CLK_MM_MDP_RSZ1			16
+#define	CLK_MM_MDP_TDSHP		17
+#define	CLK_MM_MDP_WROT0		18
+#define	CLK_MM_FAKE_ENG			19
+#define	CLK_MM_DISP_OVL0		20
+#define	CLK_MM_DISP_OVL0_2L		21
+#define	CLK_MM_DISP_OVL1_2L		22
+#define	CLK_MM_DISP_RDMA0		23
+#define	CLK_MM_DISP_RDMA1		24
+#define	CLK_MM_DISP_WDMA0		25
+#define	CLK_MM_DISP_COLOR0		26
+#define	CLK_MM_DISP_CCORR0		27
+#define	CLK_MM_DISP_AAL0		28
+#define	CLK_MM_DISP_GAMMA0		29
+#define	CLK_MM_DISP_DITHER0		30
+#define	CLK_MM_DISP_SPLIT		31
+#define	CLK_MM_DSI0_MM_CK		32
+#define	CLK_MM_DSI0_IF_CK		33
+#define	CLK_MM_DPI_MM_CK		34
+#define	CLK_MM_DPI_IF_CK		35
+#define	CLK_MM_FAKE_ENG2		36
+#define	CLK_MM_MDP_DL_RX_CK		37
+#define	CLK_MM_IPU_DL_RX_CK		38
+#define	CLK_MM_26M			39
+#define	CLK_MM_MM_R2Y			40
+#define	CLK_MM_DISP_RSZ			41
+#define CLK_MM_MDP_WDMA0		42
+#define CLK_MM_MDP_AAL			43
+#define CLK_MM_MDP_HDR			44
+#define CLK_MM_DBI_MM_CK		45
+#define CLK_MM_DBI_IF_CK		46
+#define	CLK_MM_MDP_WROT1		47
+#define	CLK_MM_DISP_POSTMASK0		48
+#define	CLK_MM_DISP_HRT_BW		49
+#define	CLK_MM_DISP_OVL_FBDC		50
+#define CLK_MM_CONFIG_NR_CLK		51
+
+/* VDEC_GCON */
+#define	CLK_VDEC_VDEC			1
+#define	CLK_VDEC_LARB1			2
+#define CLK_VDEC_GCON_NR_CLK		3
+
+/* VENC_GCON */
+#define CLK_VENC_GCON_LARB		1
+#define CLK_VENC_GCON_VENC		2
+#define CLK_VENC_GCON_JPGENC		3
+#define CLK_VENC_GCON_GALS		4
+#define CLK_VENC_GCON_NR_CLK		5
+
+/* AUD */
+#define	CLK_AUD_AFE			1
+#define	CLK_AUD_22M			2
+#define	CLK_AUD_24M			3
+#define	CLK_AUD_APLL2_TUNER		4
+#define	CLK_AUD_APLL_TUNER		5
+#define	CLK_AUD_TDM			6
+#define	CLK_AUD_ADC			7
+#define	CLK_AUD_DAC			8
+#define	CLK_AUD_DAC_PREDIS		9
+#define	CLK_AUD_TML			10
+#define	CLK_AUD_NLE			11
+#define	CLK_AUD_I2S1_BCLK_SW		12
+#define CLK_AUD_I2S2_BCLK_SW		13
+#define CLK_AUD_I2S3_BCLK_SW		14
+#define CLK_AUD_I2S4_BCLK_SW		15
+#define CLK_AUD_I2S5_BCLK_SW		16
+#define	CLK_AUD_CONN_I2S_ASRC		17
+#define	CLK_AUD_GENERAL1_ASRC		18
+#define	CLK_AUD_GENERAL2_ASRC		19
+#define	CLK_AUD_DAC_HIRES		20
+#define CLK_AUD_PDN_ADDA6_ADC		21
+#define CLK_AUD_ADC_HIRES		22
+#define CLK_AUD_ADC_HIRES_TML		23
+#define CLK_AUD_ADDA6_ADC_HIRES		24
+#define CLK_AUD_3RD_DAC			25
+#define CLK_AUD_3RD_DAC_PREDIS		26
+#define CLK_AUD_3RD_DAC_TML		27
+#define CLK_AUD_3RD_DAC_HIRES		28
+#define CLK_AUD_NR_CLK			29
+
+/* APU_CONN */
+#define	CLK_APU_CONN_APU		1
+#define	CLK_APU_CONN_AHB		2
+#define	CLK_APU_CONN_AXI		3
+#define	CLK_APU_CONN_ISP		4
+#define	CLK_APU_CONN_CAM_ADL		5
+#define	CLK_APU_CONN_IMG_ADL		6
+#define CLK_APU_CONN_EMI_26M		7
+#define CLK_APU_CONN_VPU_UDI		8
+#define CLK_APU_CONN_NR_CLK		9
+
+/* APU_CORE0 */
+#define	CLK_APU0_JTAG			1
+#define	CLK_APU0_AXI_M			2
+#define	CLK_APU0_APU			3
+#define CLK_APU0_NR_CLK			4
+
+/* APU_CORE1 */
+#define	CLK_APU1_JTAG			1
+#define	CLK_APU1_AXI_M			2
+#define	CLK_APU1_APU			3
+#define CLK_APU1_NR_CLK			4
+
+/* APU_VCORE */
+#define	CLK_APU_VCORE_AHB		1
+#define	CLK_APU_VCORE_AXI		2
+#define	CLK_APU_VCORE_ADL		3
+#define	CLK_APU_VCORE_QOS		4
+#define CLK_APU_VCORE_NR_CLK		5
+
+/* APU_MDLA */
+#define	CLK_APU_MDLA_APB		1
+#define	CLK_APU_MDLA_B0			2
+#define	CLK_APU_MDLA_B1			3
+#define	CLK_APU_MDLA_B2			4
+#define	CLK_APU_MDLA_B3			5
+#define	CLK_APU_MDLA_B4			6
+#define	CLK_APU_MDLA_B5			7
+#define	CLK_APU_MDLA_B6			8
+#define	CLK_APU_MDLA_B7			9
+#define	CLK_APU_MDLA_B8			10
+#define	CLK_APU_MDLA_B9			11
+#define	CLK_APU_MDLA_B10		12
+#define	CLK_APU_MDLA_B11		13
+#define	CLK_APU_MDLA_B12		14
+#define	CLK_APU_MDLA_NR_CLK		15
+
+/* SCP_SYS */
+#define SCP_SYS_MD1			1
+#define SCP_SYS_CONN			2
+#define SCP_SYS_DIS			3
+#define SCP_SYS_MFG1			4
+#define SCP_SYS_ISP			5
+#define SCP_SYS_VEN			6
+#define SCP_SYS_MFG0			7
+#define SCP_SYS_AUD			8
+#define SCP_SYS_CAM			9
+#define SCP_SYS_MFG3			10
+#define SCP_SYS_MFG2			11
+#define SCP_SYS_IPE			12
+#define SCP_SYS_VDE			13
+#define SCP_SYS_VPU_VCORE_DORMANT	14
+#define SCP_SYS_VPU_VCORE_SHUTDOWN	15
+#define SCP_SYS_VPU_CORE0_DORMANT	16
+#define SCP_SYS_VPU_CORE0_SHUTDOWN	17
+#define SCP_SYS_VPU_CORE1_DORMANT	18
+#define SCP_SYS_VPU_CORE1_SHUTDOWN	19
+#define SCP_SYS_VPU_CONN_DORMANT	20
+#define SCP_SYS_VPU_CONN_SHUTDOWN	21
+#define SCP_SYS_VPU_CORE2_DORMANT	22
+#define SCP_SYS_VPU_CORE2_SHUTDOWN	23
+#define SCP_SYS_MFG4			24
+#define SCP_SYS_CONN_W			25
+#define SCP_NR_SYSS			26
+
+
+/*
+ * compatible with CLK name define in kernel-4.9,
+ * using new clk name redefine old one.
+ */
+
+/* TOPCKGEN */
+#define TOP_MUX_AXI			CLK_TOP_AXI
+#define TOP_MUX_MM			CLK_TOP_MM
+#define TOP_MUX_CAM			CLK_TOP_CAM
+#define TOP_MUX_MFG			CLK_TOP_MFG
+#define TOP_MUX_CAMTG		CLK_TOP_CAMTG
+#define TOP_MUX_UART		CLK_TOP_UART
+#define TOP_MUX_SPI			CLK_TOP_SPI
+#define TOP_MUX_MSDC50_0_HCLK	CLK_TOP_MSDC50_0_HCLK
+#define TOP_MUX_MSDC50_0	CLK_TOP_MSDC50_0
+#define TOP_MUX_MSDC30_1	CLK_TOP_MSDC30_1
+#define TOP_MUX_MSDC30_2	CLK_TOP_MSDC30_2
+#define TOP_MUX_AUDIO		CLK_TOP_AUD
+#define TOP_MUX_AUD_INTBUS	CLK_TOP_AUD_INTBUS
+#define TOP_MUX_FPWRAP_ULPOSC	CLK_TOP_FPWRAP_ULPOSC
+#define TOP_MUX_SCP			CLK_TOP_SCP
+#define TOP_MUX_ATB			CLK_TOP_ATB
+#define TOP_MUX_SSPM		CLK_TOP_SSPM
+#define TOP_MUX_DPI0		CLK_TOP_DPI0
+#define TOP_MUX_SCAM		CLK_TOP_SCAM
+#define TOP_MUX_AUD_1		CLK_TOP_AUD_1
+#define TOP_MUX_AUD_2		CLK_TOP_AUD_2
+#define TOP_MUX_DISP_PWM	CLK_TOP_DISP_PWM
+#define TOP_MUX_SSUSB_TOP_XHCI	CLK_TOP_SSUSB_TOP_XHCI
+#define TOP_MUX_USB_TOP		CLK_TOP_USB_TOP
+#define TOP_MUX_SPM			CLK_TOP_SPM
+#define TOP_MUX_I2C			CLK_TOP_I2C
+#define TOP_MUX_F52M_MFG	CLK_TOP_F52M_MFG
+#define TOP_MUX_SENINF		CLK_TOP_SENINF
+#define TOP_MUX_DXCC		CLK_TOP_DXCC
+#define TOP_MUX_CAMTG2		CLK_TOP_CAMTG2
+#define TOP_MUX_AUD_ENG1	CLK_TOP_AUD_ENG1
+#define TOP_MUX_AUD_ENG2	CLK_TOP_AUD_ENG2
+#define TOP_MUX_FAES_UFSFDE	CLK_TOP_FAES_UFSFDE
+#define TOP_MUX_FUFS		CLK_TOP_FUFS
+#define TOP_MUX_IMG			CLK_TOP_IMG
+#define TOP_MUX_DSP			CLK_TOP_DSP
+#define TOP_MUX_DSP1		CLK_TOP_DSP1
+#define TOP_MUX_DSP2		CLK_TOP_DSP2
+#define TOP_MUX_IPU_IF		CLK_TOP_IPU_IF
+#define TOP_MUX_CAMTG3		CLK_TOP_CAMTG3
+#define TOP_MUX_CAMTG4		CLK_TOP_CAMTG4
+#define TOP_MUX_PMICSPI		CLK_TOP_PMICSPI
+#define TOP_MAINPLL_CK		CLK_TOP_MAINPLL_CK
+#define TOP_MAINPLL_D2		CLK_TOP_MAINPLL_D2
+#define TOP_MAINPLL_D3		CLK_TOP_MAINPLL_D3
+#define TOP_MAINPLL_D5		CLK_TOP_MAINPLL_D5
+#define TOP_MAINPLL_D7		CLK_TOP_MAINPLL_D7
+#define TOP_MAINPLL_D2_D2	CLK_TOP_MAINPLL_D2_D2
+#define TOP_MAINPLL_D2_D4	CLK_TOP_MAINPLL_D2_D4
+#define TOP_MAINPLL_D2_D8	CLK_TOP_MAINPLL_D2_D8
+#define TOP_MAINPLL_D2_D16	CLK_TOP_MAINPLL_D2_D16
+#define TOP_MAINPLL_D3_D2	CLK_TOP_MAINPLL_D3_D2
+#define TOP_MAINPLL_D3_D4	CLK_TOP_MAINPLL_D3_D4
+#define TOP_MAINPLL_D3_D8	CLK_TOP_MAINPLL_D3_D8
+#define TOP_MAINPLL_D5_D2	CLK_TOP_MAINPLL_D5_D2
+#define TOP_MAINPLL_D5_D4	CLK_TOP_MAINPLL_D5_D4
+#define TOP_MAINPLL_D7_D2	CLK_TOP_MAINPLL_D7_D2
+#define TOP_MAINPLL_D7_D4	CLK_TOP_MAINPLL_D7_D4
+#define TOP_UNIVPLL_CK		CLK_TOP_UNIVPLL_CK
+#define TOP_UNIVPLL_D2		CLK_TOP_UNIVPLL_D2
+#define TOP_UNIVPLL_D3		CLK_TOP_UNIVPLL_D3
+#define TOP_UNIVPLL_D5		CLK_TOP_UNIVPLL_D5
+#define TOP_UNIVPLL_D7		CLK_TOP_UNIVPLL_D7
+#define TOP_UNIVPLL_D2_D2	CLK_TOP_UNIVPLL_D2_D2
+#define TOP_UNIVPLL_D2_D4	CLK_TOP_UNIVPLL_D2_D4
+#define TOP_UNIVPLL_D2_D8	CLK_TOP_UNIVPLL_D2_D8
+#define TOP_UNIVPLL_D3_D2	CLK_TOP_UNIVPLL_D3_D2
+#define TOP_UNIVPLL_D3_D4	CLK_TOP_UNIVPLL_D3_D4
+#define TOP_UNIVPLL_D3_D8	CLK_TOP_UNIVPLL_D3_D8
+#define TOP_UNIVPLL_D5_D2	CLK_TOP_UNIVPLL_D5_D2
+#define TOP_UNIVPLL_D5_D4	CLK_TOP_UNIVPLL_D5_D4
+#define TOP_UNIVPLL_D5_D8	CLK_TOP_UNIVPLL_D5_D8
+#define TOP_APLL1_CK		CLK_TOP_APLL1_CK
+#define TOP_APLL1_D2		CLK_TOP_APLL1_D2
+#define TOP_APLL1_D4		CLK_TOP_APLL1_D4
+#define TOP_APLL1_D8		CLK_TOP_APLL1_D8
+#define TOP_APLL2_CK		CLK_TOP_APLL2_CK
+#define TOP_APLL2_D2		CLK_TOP_APLL2_D2
+#define TOP_APLL2_D4		CLK_TOP_APLL2_D4
+#define TOP_APLL2_D8		CLK_TOP_APLL2_D8
+#define TOP_TVDPLL_CK		CLK_TOP_TVDPLL_CK
+#define TOP_TVDPLL_D2		CLK_TOP_TVDPLL_D2
+#define TOP_TVDPLL_D4		CLK_TOP_TVDPLL_D4
+#define TOP_TVDPLL_D8		CLK_TOP_TVDPLL_D8
+#define TOP_TVDPLL_D16		CLK_TOP_TVDPLL_D16
+#define TOP_MSDCPLL_CK		CLK_TOP_MSDCPLL_CK
+#define TOP_MSDCPLL_D2		CLK_TOP_MSDCPLL_D2
+#define TOP_MSDCPLL_D4		CLK_TOP_MSDCPLL_D4
+#define TOP_MSDCPLL_D8		CLK_TOP_MSDCPLL_D8
+#define TOP_MSDCPLL_D16		CLK_TOP_MSDCPLL_D16
+#define TOP_AD_OSC_CK		CLK_TOP_AD_OSC_CK
+#define TOP_OSC_D2			CLK_TOP_OSC_D2
+#define TOP_OSC_D4			CLK_TOP_OSC_D4
+#define TOP_OSC_D8			CLK_TOP_OSC_D8
+#define TOP_OSC_D16			CLK_TOP_OSC_D16
+#define TOP_F26M_CK_D2		CLK_TOP_F26M_CK_D2
+#define TOP_MFGPLL_CK		CLK_TOP_MFGPLL_CK
+#define TOP_UNIVP_192M_CK	CLK_TOP_UNIVP_192M_CK
+#define TOP_UNIVP_192M_D2	CLK_TOP_UNIVP_192M_D2
+#define TOP_UNIVP_192M_D4	CLK_TOP_UNIVP_192M_D4
+#define TOP_UNIVP_192M_D8	CLK_TOP_UNIVP_192M_D8
+#define TOP_UNIVP_192M_D16	CLK_TOP_UNIVP_192M_D16
+#define TOP_UNIVP_192M_D32	CLK_TOP_UNIVP_192M_D32
+#define TOP_MMPLL_CK		CLK_TOP_MMPLL_CK
+#define TOP_MMPLL_D4		CLK_TOP_MMPLL_D4
+#define TOP_MMPLL_D4_D2		CLK_TOP_MMPLL_D4_D2
+#define TOP_MMPLL_D4_D4		CLK_TOP_MMPLL_D4_D4
+#define TOP_MMPLL_D5		CLK_TOP_MMPLL_D5
+#define TOP_MMPLL_D5_D2		CLK_TOP_MMPLL_D5_D2
+#define TOP_MMPLL_D5_D4		CLK_TOP_MMPLL_D5_D4
+#define TOP_MMPLL_D6		CLK_TOP_MMPLL_D6
+#define TOP_MMPLL_D7		CLK_TOP_MMPLL_D7
+#define TOP_CLK26M			CLK_TOP_CLK26M
+#define TOP_CLK13M			CLK_TOP_CLK13M
+#define TOP_MUX_ADSP		CLK_TOP_ADSP
+#define TOP_MUX_DPMAIF		CLK_TOP_DPMAIF
+#define TOP_MUX_VENC		CLK_TOP_VENC
+#define TOP_MUX_VDEC		CLK_TOP_VDEC
+#define TOP_MUX_CAMTM		CLK_TOP_CAMTM
+#define TOP_MUX_PWM			CLK_TOP_PWM
+#define TOP_ADSPPLL_CK		CLK_TOP_ADSPPLL_CK
+#define TOP_I2S0_M_SEL		CLK_TOP_I2S0_M_SEL
+#define TOP_I2S1_M_SEL		CLK_TOP_I2S1_M_SEL
+#define TOP_I2S2_M_SEL		CLK_TOP_I2S2_M_SEL
+#define TOP_I2S3_M_SEL		CLK_TOP_I2S3_M_SEL
+#define TOP_I2S4_M_SEL		CLK_TOP_I2S4_M_SEL
+#define TOP_I2S5_M_SEL		CLK_TOP_I2S5_M_SEL
+#define TOP_APLL12_DIV0		CLK_TOP_APLL12_DIV0
+#define TOP_APLL12_DIV1		CLK_TOP_APLL12_DIV1
+#define TOP_APLL12_DIV2		CLK_TOP_APLL12_DIV2
+#define TOP_APLL12_DIV3		CLK_TOP_APLL12_DIV3
+#define TOP_APLL12_DIV4		CLK_TOP_APLL12_DIV4
+#define TOP_APLL12_DIVB		CLK_TOP_APLL12_DIVB
+#define TOP_APLL12_DIV5		CLK_TOP_APLL12_DIV5
+#define TOP_MUX_IPE			CLK_TOP_IPE
+#define TOP_MUX_DPE			CLK_TOP_DPE
+#define TOP_MUX_CCU			CLK_TOP_CCU
+#define TOP_MUX_DSP3		CLK_TOP_DSP3
+#define TOP_MUX_SENINF1		CLK_TOP_SENINF1
+#define TOP_MUX_SENINF2		CLK_TOP_SENINF2
+#define TOP_MUX_AUDIO_H		CLK_TOP_AUD_H
+#define TOP_MUX_CAMTG5		CLK_TOP_CAMTG5
+#define TOP_TVDPLL_MAINPLL_D2_CK	CLK_TOP_TVDPLL_MAINPLL_D2_CK
+#define TOP_AD_OSC2_CK		CLK_TOP_AD_OSC2_CK
+#define TOP_OSC2_D2			CLK_TOP_OSC2_D2
+#define TOP_OSC2_D3			CLK_TOP_OSC2_D3
+#define TOP_FMEM_466M_CK	CLK_TOP_FMEM_466M_CK
+#define TOP_ADSPPLL_D4		CLK_TOP_ADSPPLL_D4
+#define TOP_ADSPPLL_D5		CLK_TOP_ADSPPLL_D5
+#define TOP_ADSPPLL_D6		CLK_TOP_ADSPPLL_D6
+#define TOP_OSC_D10			CLK_TOP_OSC_D10
+#define TOP_UNIVPLL_D3_D16	CLK_TOP_UNIVPLL_D3_D16
+#define TOP_NR_CLK			CLK_TOP_NR_CLK
+
+/* APMIXED */
+#define APMIXED_ARMPLL_LL	CLK_APMIXED_ARMPLL_LL
+#define APMIXED_ARMPLL_BL	CLK_APMIXED_ARMPLL_BL
+#define APMIXED_ARMPLL_BB	CLK_APMIXED_ARMPLL_BB
+#define APMIXED_CCIPLL		CLK_APMIXED_CCIPLL
+#define APMIXED_MAINPLL		CLK_APMIXED_MAINPLL
+#define APMIXED_UNIV2PLL	CLK_APMIXED_UNIV2PLL
+#define APMIXED_MSDCPLL		CLK_APMIXED_MSDCPLL
+#define APMIXED_ADSPPLL		CLK_APMIXED_ADSPPLL
+#define APMIXED_MMPLL		CLK_APMIXED_MMPLL
+#define APMIXED_MFGPLL		CLK_APMIXED_MFGPLL
+#define APMIXED_TVDPLL		CLK_APMIXED_TVDPLL
+#define APMIXED_APLL1		CLK_APMIXED_APLL1
+#define APMIXED_APLL2		CLK_APMIXED_APLL2
+#define APMIXED_SSUSB26M	CLK_APMIXED_SSUSB26M
+#define APMIXED_APPLL26M	CLK_APMIXED_APPLL26M
+#define APMIXED_MIPIC0_26M	CLK_APMIXED_MIPIC0_26M
+#define APMIXED_MDPLLGP26M	CLK_APMIXED_MDPLLGP26M
+#define APMIXED_MMSYS_F26M	CLK_APMIXED_MM_F26M
+#define APMIXED_UFS26M		CLK_APMIXED_UFS26M
+#define APMIXED_MIPIC1_26M	CLK_APMIXED_MIPIC1_26M
+#define APMIXED_MEMPLL26M	CLK_APMIXED_MEMPLL26M
+#define APMIXED_CLKSQ_LVPLL_26M		CLK_APMIXED_CLKSQ_LVPLL_26M
+#define APMIXED_MIPID0_26M	CLK_APMIXED_MIPID0_26M
+#define APMIXED_MIPID1_26M	CLK_APMIXED_MIPID1_26M
+#define APMIXED_NR_CLK		CLK_APMIXED_NR_CLK
+
+/* CAMSYS */
+#define CAMSYS_LARB10_CGPDN		CLK_CAM_LARB10
+#define CAMSYS_DFP_VAD_CGPDN	CLK_CAM_DFP_VAD
+#define CAMSYS_LARB11_CGPDN		CLK_CAM_LARB11
+#define CAMSYS_LARB9_CGPDN		CLK_CAM_LARB9
+#define CAMSYS_CAM_CGPDN		CLK_CAM_CAM
+#define CAMSYS_CAMTG_CGPDN		CLK_CAM_CAMTG
+#define CAMSYS_SENINF_CGPDN		CLK_CAM_SENINF
+#define CAMSYS_CAMSV0_CGPDN		CLK_CAM_CAMSV0
+#define CAMSYS_CAMSV1_CGPDN		CLK_CAM_CAMSV1
+#define CAMSYS_CAMSV2_CGPDN		CLK_CAM_CAMSV2
+#define CAMSYS_CAMSV3_CGPDN		CLK_CAM_CAMSV3
+#define CAMSYS_CCU_CGPDN		CLK_CAM_CCU
+#define CAMSYS_FAKE_ENG_CGPDN	CLK_CAM_FAKE_ENG
+#define CAMSYS_NR_CLK			CLK_CAM_NR_CLK
+
+/* INFRACFG_AO */
+#define INFRACFG_AO_PMIC_CG_TMR		CLK_INFRA_PMIC_TMR
+#define INFRACFG_AO_PMIC_CG_AP		CLK_INFRA_PMIC_AP
+#define INFRACFG_AO_PMIC_CG_MD		CLK_INFRA_PMIC_MD
+#define INFRACFG_AO_PMIC_CG_CONN	CLK_INFRA_PMIC_CONN
+#define INFRACFG_AO_SCPSYS_CG		CLK_INFRA_SCPSYS
+#define INFRACFG_AO_SEJ_CG			CLK_INFRA_SEJ
+#define INFRACFG_AO_APXGPT_CG		CLK_INFRA_APXGPT
+#define INFRACFG_AO_ICUSB_CG		CLK_INFRA_ICUSB
+#define INFRACFG_AO_GCE_CG			CLK_INFRA_GCE
+#define INFRACFG_AO_THERM_CG		CLK_INFRA_THERM
+#define INFRACFG_AO_I2C0_CG			CLK_INFRA_I2C0
+#define INFRACFG_AO_I2C1_CG			CLK_INFRA_I2C1
+#define INFRACFG_AO_I2C2_CG			CLK_INFRA_I2C2
+#define INFRACFG_AO_I2C3_CG			CLK_INFRA_I2C3
+#define INFRACFG_AO_PWM_HCLK_CG		CLK_INFRA_PWM_HCLK
+#define INFRACFG_AO_PWM1_CG			CLK_INFRA_PWM1
+#define INFRACFG_AO_PWM2_CG			CLK_INFRA_PWM2
+#define INFRACFG_AO_PWM3_CG			CLK_INFRA_PWM3
+#define INFRACFG_AO_PWM4_CG			CLK_INFRA_PWM4
+#define INFRACFG_AO_PWM_CG			CLK_INFRA_PWM1
+#define INFRACFG_AO_UART0_CG		CLK_INFRA_UART0
+#define INFRACFG_AO_UART1_CG		CLK_INFRA_UART1
+#define INFRACFG_AO_UART2_CG		CLK_INFRA_UART2
+#define INFRACFG_AO_UART3_CG		CLK_INFRA_UART3
+#define INFRACFG_AO_GCE_26M_CG		CLK_INFRA_GCE_26M
+#define INFRACFG_AO_CQ_DMA_FPC_CG	CLK_INFRA_CQ_DMA_FPC
+#define INFRACFG_AO_BTIF_CG			CLK_INFRA_BTIF
+#define INFRACFG_AO_SPI0_CG			CLK_INFRA_SPI0
+#define INFRACFG_AO_MSDC0_CG		CLK_INFRA_MSDC0
+#define INFRACFG_AO_MSDC1_CG		CLK_INFRA_MSDC1
+#define INFRACFG_AO_MSDC2_CG		CLK_INFRA_MSDC2
+#define INFRACFG_AO_MSDC0_SCK_CG	CLK_INFRA_MSDC0_SCK
+#define INFRACFG_AO_DVFSRC_CG		CLK_INFRA_DVFSRC
+#define INFRACFG_AO_GCPU_CG			CLK_INFRA_GCPU
+#define INFRACFG_AO_TRNG_CG			CLK_INFRA_TRNG
+#define INFRACFG_AO_AUXADC_CG		CLK_INFRA_AUXADC
+#define INFRACFG_AO_CPUM_CG			CLK_INFRA_CPUM
+#define INFRACFG_AO_CCIF1_AP_CG		CLK_INFRA_CCIF1_AP
+#define INFRACFG_AO_CCIF1_MD_CG		CLK_INFRA_CCIF1_MD
+#define INFRACFG_AO_AUXADC_MD_CG	CLK_INFRA_AUXADC_MD
+#define INFRACFG_AO_MSDC1_SCK_CG	CLK_INFRA_MSDC1_SCK
+#define INFRACFG_AO_MSDC2_SCK_CG	CLK_INFRA_MSDC2_SCK
+#define INFRACFG_AO_AP_DMA_CG		CLK_INFRA_AP_DMA
+#define INFRACFG_AO_XIU_CG			CLK_INFRA_XIU
+#define INFRACFG_AO_DEVICE_APC_CG	CLK_INFRA_DEVICE_APC
+#define INFRACFG_AO_CCIF_AP_CG		CLK_INFRA_CCIF_AP
+#define INFRACFG_AO_DEBUGSYS_CG		CLK_INFRA_DEBUGSYS
+#define INFRACFG_AO_AUDIO_CG		CLK_INFRA_AUD
+#define INFRACFG_AO_CCIF_MD_CG		CLK_INFRA_CCIF_MD
+#define INFRACFG_AO_DXCC_SEC_CORE_CG	CLK_INFRA_DXCC_SEC_CORE
+#define INFRACFG_AO_DXCC_AO_CG		CLK_INFRA_DXCC_AO
+#define INFRACFG_AO_DRAMC_F26M_CG	CLK_INFRA_DRAMC_F26M
+#define INFRACFG_AO_IRTX_CG			CLK_INFRA_IRTX
+#define INFRACFG_AO_DISP_PWM_CG		CLK_INFRA_DISP_PWM
+#define INFRACFG_AO_DPMAIF_CK		CLK_INFRA_DPMAIF_CK
+#define INFRACFG_AO_AUDIO_26M_BCLK_CK	CLK_INFRA_AUD_26M_BCLK_CK
+#define INFRACFG_AO_SPI1_CG			CLK_INFRA_SPI1
+#define INFRACFG_AO_I2C4_CG			CLK_INFRA_I2C4
+#define INFRACFG_AO_MODEM_TEMP_SHARE_CG	CLK_INFRA_MODEM_TEMP_SHARE
+#define INFRACFG_AO_SPI2_CG			CLK_INFRA_SPI2
+#define INFRACFG_AO_SPI3_CG			CLK_INFRA_SPI3
+#define INFRACFG_AO_UNIPRO_SCK_CG	CLK_INFRA_UNIPRO_SCK
+#define INFRACFG_AO_UNIPRO_TICK_CG	CLK_INFRA_UNIPRO_TICK
+#define INFRACFG_AO_UFS_MP_SAP_BCLK_CG	CLK_INFRA_UFS_MP_SAP_BCLK
+#define INFRACFG_AO_MD32_BCLK_CG	CLK_INFRA_MD32_BCLK
+#define INFRACFG_AO_SSPM_CG			CLK_INFRA_SSPM
+#define INFRACFG_AO_UNIPRO_MBIST_CG	CLK_INFRA_UNIPRO_MBIST
+#define INFRACFG_AO_SSPM_BUS_HCLK_CG	CLK_INFRA_SSPM_BUS_HCLK
+#define INFRACFG_AO_I2C5_CG			CLK_INFRA_I2C5
+#define INFRACFG_AO_I2C5_ARBITER_CG	CLK_INFRA_I2C5_ARBITER
+#define INFRACFG_AO_I2C5_IMM_CG		CLK_INFRA_I2C5_IMM
+#define INFRACFG_AO_I2C1_ARBITER_CG	CLK_INFRA_I2C1_ARBITER
+#define INFRACFG_AO_I2C1_IMM_CG		CLK_INFRA_I2C1_IMM
+#define INFRACFG_AO_I2C2_ARBITER_CG	CLK_INFRA_I2C2_ARBITER
+#define INFRACFG_AO_I2C2_IMM_CG		CLK_INFRA_I2C2_IMM
+#define INFRACFG_AO_SPI4_CG			CLK_INFRA_SPI4
+#define INFRACFG_AO_SPI5_CG			CLK_INFRA_SPI5
+#define INFRACFG_AO_CQ_DMA_CG		CLK_INFRA_CQ_DMA
+#define INFRACFG_AO_UFS_CG			CLK_INFRA_UFS
+#define INFRACFG_AO_AES_UFSFDE_CG	CLK_INFRA_AES_UFSFDE
+#define INFRACFG_AO_UFS_TICK_CG		CLK_INFRA_UFS_TICK
+#define INFRACFG_AO_MSDC0_SELF_CG	CLK_INFRA_MSDC0_SELF
+#define INFRACFG_AO_MSDC1_SELF_CG	CLK_INFRA_MSDC1_SELF
+#define INFRACFG_AO_MSDC2_SELF_CG	CLK_INFRA_MSDC2_SELF
+#define INFRACFG_AO_SSPM_26M_SELF_CG	CLK_INFRA_SSPM_26M_SELF
+#define INFRACFG_AO_SSPM_32K_SELF_CG	CLK_INFRA_SSPM_32K_SELF
+#define INFRACFG_AO_UFS_AXI_CG		CLK_INFRA_UFS_AXI
+#define INFRACFG_AO_I2C6_CG			CLK_INFRA_I2C6
+#define INFRACFG_AO_AP_MSDC0_CG		CLK_INFRA_AP_MSDC0
+#define INFRACFG_AO_MD_MSDC0_CG		CLK_INFRA_MD_MSDC0
+#define INFRACFG_AO_USB_CG			CLK_INFRA_USB
+#define INFRACFG_AO_DEVMPU_BCLK_CG	CLK_INFRA_DEVMPU_BCLK
+#define INFRACFG_AO_CCIF2_AP_CG		CLK_INFRA_CCIF2_AP
+#define INFRACFG_AO_CCIF2_MD_CG		CLK_INFRA_CCIF2_MD
+#define INFRACFG_AO_CCIF3_AP_CG		CLK_INFRA_CCIF3_AP
+#define INFRACFG_AO_CCIF3_MD_CG		CLK_INFRA_CCIF3_MD
+#define INFRACFG_AO_SEJ_F13M_CG		CLK_INFRA_SEJ_F13M
+#define INFRACFG_AO_AES_BCLK_CG		CLK_INFRA_AES_BCLK
+#define INFRACFG_AO_I2C7_CG			CLK_INFRA_I2C7
+#define INFRACFG_AO_I2C8_CG			CLK_INFRA_I2C8
+#define INFRACFG_AO_FBIST2FPC_CG	CLK_INFRA_FBIST2FPC
+#define INFRACFG_AO_CCIF4_AP_CG		CLK_INFRA_CCIF4_AP
+#define INFRACFG_AO_CCIF4_MD_CG		CLK_INFRA_CCIF4_MD
+#define INFRACFG_AO_FADSP_CG		CLK_INFRA_FADSP
+#define INFRACFG_AO_SSUSB_XHCI_CG	CLK_INFRA_SSUSB_XHCI
+#define INFRACFG_AO_SPI6_CG			CLK_INFRA_SPI6
+#define INFRACFG_AO_SPI7_CG			CLK_INFRA_SPI7
+#define INFRACFG_AO_NR_CLK			CLK_INFRA_NR_CLK
+
+/* MFGCFG */
+#define MFGCFG_BG3D			CLK_MFGCFG_BG3D
+#define MFGCFG_NR_CLK		CLK_MFGCFG_NR_CLK
+
+/* IMG */
+#define	IMG_WPE_A		CLK_IMG_WPE_A
+#define	IMG_MFB			CLK_IMG_MFB
+#define	IMG_DIP			CLK_IMG_DIP
+#define	IMG_LARB6		CLK_IMG_LARB6
+#define	IMG_LARB5		CLK_IMG_LARB5
+#define IMG_NR_CLK		CLK_IMG_NR_CLK
+
+/* IPE */
+#define	IPE_LARB7		CLK_IPE_LARB7
+#define	IPE_LARB8		CLK_IPE_LARB8
+#define	IPE_SMI_SUBCOM	CLK_IPE_SMI_SUBCOM
+#define	IPE_FD			CLK_IPE_FD
+#define	IPE_FE			CLK_IPE_FE
+#define IPE_RSC			CLK_IPE_RSC
+#define IPE_DPE			CLK_IPE_DPE
+#define IPE_NR_CLK		CLK_IPE_NR_CLK
+
+/* MMSYS_CONFIG */
+#define	MMSYS_SMI_COMMON		CLK_MM_SMI_COMMON
+#define	MMSYS_SMI_LARB0			CLK_MM_SMI_LARB0
+#define	MMSYS_SMI_LARB1			CLK_MM_SMI_LARB1
+#define	MMSYS_GALS_COMM0		CLK_MM_GALS_COMM0
+#define	MMSYS_GALS_COMM1		CLK_MM_GALS_COMM1
+#define	MMSYS_GALS_CCU2MM		CLK_MM_GALS_CCU2MM
+#define	MMSYS_GALS_IPU12MM		CLK_MM_GALS_IPU12MM
+#define	MMSYS_GALS_IMG2MM		CLK_MM_GALS_IMG2MM
+#define	MMSYS_GALS_CAM2MM		CLK_MM_GALS_CAM2MM
+#define	MMSYS_GALS_IPU2MM		CLK_MM_GALS_IPU2MM
+#define	MMSYS_MDP_DL_TXCK		CLK_MM_MDP_DL_TXCK
+#define	MMSYS_IPU_DL_TXCK		CLK_MM_IPU_DL_TXCK
+#define	MMSYS_MDP_RDMA0			CLK_MM_MDP_RDMA0
+#define	MMSYS_MDP_RDMA1			CLK_MM_MDP_RDMA1
+#define	MMSYS_MDP_RSZ0			CLK_MM_MDP_RSZ0
+#define	MMSYS_MDP_RSZ1			CLK_MM_MDP_RSZ1
+#define	MMSYS_MDP_TDSHP			CLK_MM_MDP_TDSHP
+#define	MMSYS_MDP_WROT0			CLK_MM_MDP_WROT0
+#define	MMSYS_FAKE_ENG			CLK_MM_FAKE_ENG
+#define	MMSYS_DISP_OVL0			CLK_MM_DISP_OVL0
+#define	MMSYS_DISP_OVL0_2L		CLK_MM_DISP_OVL0_2L
+#define	MMSYS_DISP_OVL1_2L		CLK_MM_DISP_OVL1_2L
+#define	MMSYS_DISP_RDMA0		CLK_MM_DISP_RDMA0
+#define	MMSYS_DISP_RDMA1		CLK_MM_DISP_RDMA1
+#define	MMSYS_DISP_WDMA0		CLK_MM_DISP_WDMA0
+#define	MMSYS_DISP_COLOR0		CLK_MM_DISP_COLOR0
+#define	MMSYS_DISP_CCORR0		CLK_MM_DISP_CCORR0
+#define	MMSYS_DISP_AAL0			CLK_MM_DISP_AAL0
+#define	MMSYS_DISP_GAMMA0		CLK_MM_DISP_GAMMA0
+#define	MMSYS_DISP_DITHER0		CLK_MM_DISP_DITHER0
+#define	MMSYS_DISP_SPLIT		CLK_MM_DISP_SPLIT
+#define	MMSYS_DSI0_MM_CK		CLK_MM_DSI0_MM_CK
+#define	MMSYS_DSI0_IF_CK		CLK_MM_DSI0_IF_CK
+#define	MMSYS_DPI_MM_CK			CLK_MM_DPI_MM_CK
+#define	MMSYS_DPI_IF_CK			CLK_MM_DPI_IF_CK
+#define	MMSYS_FAKE_ENG2			CLK_MM_FAKE_ENG2
+#define	MMSYS_MDP_DL_RX_CK		CLK_MM_MDP_DL_RX_CK
+#define	MMSYS_IPU_DL_RX_CK		CLK_MM_IPU_DL_RX_CK
+#define	MMSYS_26M				CLK_MM_26M
+#define	MMSYS_MMSYS_R2Y			CLK_MM_MM_R2Y
+#define	MMSYS_DISP_RSZ			CLK_MM_DISP_RSZ
+#define MMSYS_MDP_WDMA0			CLK_MM_MDP_WDMA0
+#define MMSYS_MDP_AAL			CLK_MM_MDP_AAL
+#define MMSYS_MDP_HDR			CLK_MM_MDP_HDR
+#define MMSYS_DBI_MM_CK			CLK_MM_DBI_MM_CK
+#define MMSYS_DBI_IF_CK			CLK_MM_DBI_IF_CK
+#define	MMSYS_MDP_WROT1			CLK_MM_MDP_WROT1
+#define	MMSYS_DISP_POSTMASK0	CLK_MM_DISP_POSTMASK0
+#define	MMSYS_DISP_HRT_BW		CLK_MM_DISP_HRT_BW
+#define	MMSYS_DISP_OVL_FBDC		CLK_MM_DISP_OVL_FBDC
+#define MMSYS_CONFIG_NR_CLK		CLK_MM_CONFIG_NR_CLK
+
+/* VDEC_GCON */
+#define	VDEC_VDEC			CLK_VDEC_VDEC
+#define	VDEC_LARB1			CLK_VDEC_LARB1
+#define VDEC_GCON_NR_CLK	CLK_VDEC_GCON_NR_CLK
+
+/* VENC_GCON */
+#define VENC_GCON_LARB		CLK_VENC_GCON_LARB
+#define VENC_GCON_VENC		CLK_VENC_GCON_VENC
+#define VENC_GCON_JPGENC	CLK_VENC_GCON_JPGENC
+#define VENC_GCON_GALS		CLK_VENC_GCON_GALS
+#define VENC_GCON_NR_CLK	CLK_VENC_GCON_NR_CLK
+
+/* AUDIO */
+#define	AUDIO_AFE			CLK_AUD_AFE
+#define	AUDIO_22M			CLK_AUD_22M
+#define	AUDIO_24M			CLK_AUD_24M
+#define	AUDIO_APLL2_TUNER	CLK_AUD_APLL2_TUNER
+#define	AUDIO_APLL_TUNER	CLK_AUD_APLL_TUNER
+#define	AUDIO_TDM			CLK_AUD_TDM
+#define	AUDIO_ADC			CLK_AUD_ADC
+#define	AUDIO_DAC			CLK_AUD_DAC
+#define	AUDIO_DAC_PREDIS	CLK_AUD_DAC_PREDIS
+#define	AUDIO_TML			CLK_AUD_TML
+#define	AUDIO_NLE			CLK_AUD_NLE
+#define	AUDIO_I2S1_BCLK_SW	CLK_AUD_I2S1_BCLK_SW
+#define AUDIO_I2S2_BCLK_SW	CLK_AUD_I2S2_BCLK_SW
+#define AUDIO_I2S3_BCLK_SW	CLK_AUD_I2S3_BCLK_SW
+#define AUDIO_I2S4_BCLK_SW	CLK_AUD_I2S4_BCLK_SW
+#define AUDIO_I2S5_BCLK_SW	CLK_AUD_I2S5_BCLK_SW
+#define	AUDIO_CONN_I2S_ASRC	CLK_AUD_CONN_I2S_ASRC
+#define	AUDIO_GENERAL1_ASRC	CLK_AUD_GENERAL1_ASRC
+#define	AUDIO_GENERAL2_ASRC	CLK_AUD_GENERAL2_ASRC
+#define	AUDIO_DAC_HIRES		CLK_AUD_DAC_HIRES
+#define AUDIO_PDN_ADDA6_ADC	CLK_AUD_PDN_ADDA6_ADC
+#define AUDIO_ADC_HIRES		CLK_AUD_ADC_HIRES
+#define AUDIO_ADC_HIRES_TML	CLK_AUD_ADC_HIRES_TML
+#define AUDIO_ADDA6_ADC_HIRES	CLK_AUD_ADDA6_ADC_HIRES
+#define AUDIO_3RD_DAC		CLK_AUD_3RD_DAC
+#define AUDIO_3RD_DAC_PREDIS	CLK_AUD_3RD_DAC_PREDIS
+#define AUDIO_3RD_DAC_TML	CLK_AUD_3RD_DAC_TML
+#define AUDIO_3RD_DAC_HIRES	CLK_AUD_3RD_DAC_HIRES
+#define AUDIO_NR_CLK		CLK_AUD_NR_CLK
+
+/* APU_CONN */
+#define	APU_CONN_APU_CG		CLK_APU_CONN_APU
+#define	APU_CONN_AHB_CG		CLK_APU_CONN_AHB
+#define	APU_CONN_AXI_CG		CLK_APU_CONN_AXI
+#define	APU_CONN_ISP_CG		CLK_APU_CONN_ISP
+#define	APU_CONN_CAM_ADL_CG	CLK_APU_CONN_CAM_ADL
+#define	APU_CONN_IMG_ADL_CG	CLK_APU_CONN_IMG_ADL
+#define APU_CONN_EMI_26M_CG	CLK_APU_CONN_EMI_26M
+#define APU_CONN_VPU_UDI_CG	CLK_APU_CONN_VPU_UDI
+#define APU_CONN_NR_CLK		CLK_APU_CONN_NR_CLK
+
+/* APU_CORE0 */
+#define	APU0_JTAG_CG		CLK_APU0_JTAG
+#define	APU0_AXI_M_CG		CLK_APU0_AXI_M
+#define	APU0_APU_CG			CLK_APU0_APU
+#define APU0_NR_CLK			CLK_APU0_NR_CLK
+
+/* APU_CORE1 */
+#define	APU1_JTAG_CG		CLK_APU1_JTAG
+#define	APU1_AXI_M_CG		CLK_APU1_AXI_M
+#define	APU1_APU_CG			CLK_APU1_APU
+#define APU1_NR_CLK			CLK_APU1_NR_CLK
+
+/* APU_VCORE */
+#define	APU_VCORE_AHB_CG	CLK_APU_VCORE_AHB
+#define	APU_VCORE_AXI_CG	CLK_APU_VCORE_AXI
+#define	APU_VCORE_ADL_CG	CLK_APU_VCORE_ADL
+#define	APU_VCORE_QOS_CG	CLK_APU_VCORE_QOS
+#define APU_VCORE_NR_CLK	CLK_APU_VCORE_NR_CLK
+
+/* APU_MDLA */
+#define	APU_MDLA_APB_CG		CLK_APU_MDLA_APB
+#define	APU_MDLA_CG_B0		CLK_APU_MDLA_B0
+#define	APU_MDLA_CG_B1		CLK_APU_MDLA_B1
+#define	APU_MDLA_CG_B2		CLK_APU_MDLA_B2
+#define	APU_MDLA_CG_B3		CLK_APU_MDLA_B3
+#define	APU_MDLA_CG_B4		CLK_APU_MDLA_B4
+#define	APU_MDLA_CG_B5		CLK_APU_MDLA_B5
+#define	APU_MDLA_CG_B6		CLK_APU_MDLA_B6
+#define	APU_MDLA_CG_B7		CLK_APU_MDLA_B7
+#define	APU_MDLA_CG_B8		CLK_APU_MDLA_B8
+#define	APU_MDLA_CG_B9		CLK_APU_MDLA_B9
+#define	APU_MDLA_CG_B10		CLK_APU_MDLA_B10
+#define	APU_MDLA_CG_B11		CLK_APU_MDLA_B11
+#define	APU_MDLA_CG_B12		CLK_APU_MDLA_B12
+#define	APU_MDLA_NR_CLK		CLK_APU_MDLA_NR_CLK
+
+/* SCP_SYS */
+#define SCP_SYS_AUDIO			SCP_SYS_AUD
+
+#endif /* _DT_BINDINGS_CLK_MT6779_H */

include/dt-bindings/clock/mt6781-clk.h

@@ -0,0 +1,514 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MT6781_H
+#define _DT_BINDINGS_CLK_MT6781_H
+
+/* TOPCKGEN */
+#define	TOP_MUX_AXI	1
+#define	TOP_MUX_SCP	2
+#define	TOP_MUX_MFG	3
+#define	TOP_MUX_CAMTG	4
+#define	TOP_MUX_CAMTG1	5
+#define	TOP_MUX_CAMTG2	6
+#define	TOP_MUX_CAMTG3	7
+#define	TOP_MUX_CAMTG4	8
+#define	TOP_MUX_CAMTG5	9
+#define	TOP_MUX_CAMTG6	10
+#define	TOP_MUX_UART	11
+#define	TOP_MUX_SPI	12
+#define	TOP_MUX_MSDC50_0_HCLK	13
+#define	TOP_MUX_MSDC50_0	14
+#define	TOP_MUX_MSDC30_1	15
+#define	TOP_MUX_AUDIO	16
+#define	TOP_MUX_AUD_INTBUS	17
+#define	TOP_MUX_AUD_1	18
+#define	TOP_MUX_AUD_2	19
+#define	TOP_MUX_AUD_ENG1	20
+#define	TOP_MUX_AUD_ENG2	21
+#define	TOP_MUX_DISP_PWM	22
+#define	TOP_MUX_SSPM	23
+#define	TOP_MUX_DXCC	24
+#define	TOP_MUX_USB_TOP	25
+#define	TOP_MUX_SRCK	26
+#define	TOP_MUX_SPM	27
+#define	TOP_MUX_I2C	28
+#define	TOP_MUX_PWM	29
+#define	TOP_MUX_SENINF	30
+#define	TOP_MUX_SENINF1	31
+#define	TOP_MUX_SENINF2	32
+#define	TOP_MUX_SENINF3	33
+#define	TOP_MUX_AES_MSDCFDE	34
+#define	TOP_MUX_FPWRAP_ULPOSC	35
+#define	TOP_MUX_CAMTM	36
+#define	TOP_MUX_VENC	37
+#define	TOP_MUX_CAM	38
+#define	TOP_MUX_IMG1	39
+#define	TOP_MUX_IPE	40
+#define	TOP_MUX_DPMAIF	41
+#define	TOP_MUX_VDEC	42
+#define	TOP_MUX_DISP	43
+#define	TOP_MUX_MDP	44
+#define	TOP_MUX_AUDIO_H	45
+#define	TOP_MUX_UFS	46
+#define	TOP_MUX_AES_FDE	47
+#define	TOP_MUX_ADSP	48
+#define	TOP_MUX_DVFSRC	49
+#define	TOP_MUX_DSI_OCC	50
+#define	TOP_MUX_SPMI_MST	51
+#define	TOP_MAINPLL_CK	52
+#define	TOP_MAINPLL_D2	53
+#define	TOP_MAINPLL_D3	54
+#define	TOP_MAINPLL_D5	55
+#define	TOP_MAINPLL_D7	56
+#define	TOP_MAINPLL_D2_D2	57
+#define	TOP_MAINPLL_D2_D4	58
+#define	TOP_MAINPLL_D2_D8	59
+#define	TOP_MAINPLL_D2_D16	60
+#define	TOP_MAINPLL_D3_D2	61
+#define	TOP_MAINPLL_D3_D4	62
+#define	TOP_MAINPLL_D3_D8	63
+#define	TOP_MAINPLL_D5_D2	64
+#define	TOP_MAINPLL_D5_D4	65
+#define	TOP_MAINPLL_D7_D2	66
+#define	TOP_MAINPLL_D7_D4	67
+#define	TOP_UNIVPLL_CK	68
+#define	TOP_UNIVPLL_D2	69
+#define	TOP_UNIVPLL_D3	70
+#define	TOP_UNIVPLL_D5	71
+#define	TOP_UNIVPLL_D7	72
+#define	TOP_UNIVPLL_D2_D2	73
+#define	TOP_UNIVPLL_D2_D4	74
+#define	TOP_UNIVPLL_D2_D8	75
+#define	TOP_UNIVPLL_D3_D2	76
+#define	TOP_UNIVPLL_D3_D4	77
+#define	TOP_UNIVPLL_D3_D8	78
+#define	TOP_UNIVPLL_D5_D2	79
+#define	TOP_UNIVPLL_D5_D4	80
+#define	TOP_UNIVPLL_D5_D8	81
+#define	TOP_APLL1_CK	82
+#define	TOP_APLL1_D2	83
+#define	TOP_APLL1_D4	84
+#define	TOP_APLL1_D8	85
+#define	TOP_APLL2_CK	86
+#define	TOP_APLL2_D2	87
+#define	TOP_APLL2_D4	88
+#define	TOP_APLL2_D8	89
+#define	TOP_MSDCPLL_CK	90
+#define	TOP_MSDCPLL_D2	91
+#define	TOP_MSDCPLL_D4	92
+#define	TOP_MSDCPLL_D8	93
+#define	TOP_MSDCPLL_D16	94
+#define	TOP_OSC	95
+#define	TOP_OSC_D2	96
+#define	TOP_OSC_D4	97
+#define	TOP_OSC_D8	98
+#define	TOP_OSC_D10	99
+#define	TOP_OSC_D16	100
+#define	TOP_OSC_D32	101
+#define	TOP_F26M_CK_D2	102
+#define	TOP_UNIVP_192M_D2	103
+#define	TOP_UNIVP_192M_D4	104
+#define	TOP_UNIVP_192M_D8	105
+#define	TOP_UNIVP_192M_D16	106
+#define	TOP_UNIVP_192M_D32	107
+#define	TOP_MMPLL_CK	108
+#define	TOP_MMPLL_D4	109
+#define	TOP_MMPLL_D4_D2	110
+#define	TOP_MMPLL_D4_D4	111
+#define	TOP_MMPLL_D5	112
+#define	TOP_MMPLL_D5_D2	113
+#define	TOP_MMPLL_D5_D4	114
+#define	TOP_MMPLL_D6	115
+#define	TOP_MMPLL_D7	116
+#define	TOP_ADSPPLL_CK	117
+#define	TOP_I2S0_M_SEL	118
+#define	TOP_I2S1_M_SEL	119
+#define	TOP_I2S2_M_SEL	120
+#define	TOP_I2S3_M_SEL	121
+#define	TOP_I2S4_M_SEL	122
+#define	TOP_I2S5_M_SEL	123
+#define	TOP_APLL12_DIV0	124
+#define	TOP_APLL12_DIV1	125
+#define	TOP_APLL12_DIV2	126
+#define	TOP_APLL12_DIV3	127
+#define	TOP_APLL12_DIV4	128
+#define	TOP_APLL12_DIVB	129
+#define	TOP_APLL12_DIV5	130
+#define	TOP_ADSPPLL_D4	131
+#define	TOP_ADSPPLL_D5	132
+#define	TOP_ADSPPLL_D6	133
+#define	TOP_UNIVPLL_D3_D16	134
+#define	TOP_UNIVP_192M_CK 135
+#define	TOP_MFGPLL_CK 136
+#define	TOP_UNIVPLL_D3_D32	137
+#define	TOP_MMPLL_D2	138
+#define	TOP_ADSPPLL_D2	139
+#define	TOP_ADSPPLL_D8	140
+#define	TOP_NR_CLK	141
+
+
+
+
+/* APMIXED */
+#define APMIXED_ARMPLL_LL 1
+#define APMIXED_ARMPLL_BL 2
+#define APMIXED_ARMPLL_BB 3
+#define APMIXED_CCIPLL 4
+#define APMIXED_MAINPLL 5
+#define APMIXED_UNIV2PLL 6
+#define APMIXED_MSDCPLL 7
+#define APMIXED_ADSPPLL 8
+#define APMIXED_MMPLL 9
+#define APMIXED_MFGPLL 10
+#define APMIXED_APLL1 11
+#define APMIXED_APLL2 12
+#define APMIXED_SSUSB26M 13
+#define APMIXED_APPLL26M 14
+#define APMIXED_MIPIC0_26M 15
+#define APMIXED_MDPLLGP26M 16
+#define APMIXED_MMSYS_F26M 17
+#define APMIXED_UFS26M 18
+#define APMIXED_MIPIC1_26M 19
+#define APMIXED_MEMPLL26M 20
+#define APMIXED_CLKSQ_LVPLL_26M 21
+#define APMIXED_MIPID0_26M 22
+#define APMIXED_MIPID1_26M 23
+#define APMIXED_NR_CLK 24
+
+/* INFRACFG_AO */
+#define INFRACFG_AO_PMIC_CG_TMR 1
+#define INFRACFG_AO_PMIC_CG_AP 2
+#define INFRACFG_AO_PMIC_CG_MD 3
+#define INFRACFG_AO_PMIC_CG_CONN 4
+#define INFRACFG_AO_SCPSYS_CG 5
+#define INFRACFG_AO_SEJ_CG 6
+#define INFRACFG_AO_APXGPT_CG 7
+#define INFRACFG_AO_ICUSB_CG 8
+#define INFRACFG_AO_GCE_CG 9
+#define INFRACFG_AO_THERM_CG 10
+#define INFRACFG_AO_I2C_AP_CG 11
+#define INFRACFG_AO_I2C_CCU_CG 12
+#define INFRACFG_AO_I2C_SSPM_CG 13
+#define INFRACFG_AO_I2C_RSV_CG 14
+#define INFRACFG_AO_PWM_HCLK_CG 15
+#define INFRACFG_AO_PWM1_CG 16
+#define INFRACFG_AO_PWM2_CG 17
+#define INFRACFG_AO_PWM3_CG 18
+#define INFRACFG_AO_PWM4_CG 19
+#define INFRACFG_AO_PWM_CG 20
+#define INFRACFG_AO_UART0_CG 21
+#define INFRACFG_AO_UART1_CG 22
+#define INFRACFG_AO_UART2_CG 23
+#define INFRACFG_AO_UART3_CG 24
+#define INFRACFG_AO_GCE_26M_CG 25
+#define INFRACFG_AO_CQ_DMA_FPC_CG 26
+#define INFRACFG_AO_BTIF_CG 27
+#define INFRACFG_AO_SPI0_CG 28
+#define INFRACFG_AO_MSDC0_CG 29
+#define INFRACFG_AO_MSDC1_CG 30
+#define INFRACFG_AO_MSDC2_CG 31
+#define INFRACFG_AO_MSDC0_SCK_CG 32
+#define INFRACFG_AO_DVFSRC_CG 33
+#define INFRACFG_AO_GCPU_CG 34
+#define INFRACFG_AO_TRNG_CG 35
+#define INFRACFG_AO_AUXADC_CG 36
+#define INFRACFG_AO_CPUM_CG 37
+#define INFRACFG_AO_CCIF1_AP_CG 38
+#define INFRACFG_AO_CCIF1_MD_CG 39
+#define INFRACFG_AO_AUXADC_MD_CG 40
+#define INFRACFG_AO_MSDC1_SCK_CG 41
+#define INFRACFG_AO_MSDC2_SCK_CG 42
+#define INFRACFG_AO_AP_DMA_CG 43
+#define INFRACFG_AO_XIU_CG 44
+#define INFRACFG_AO_DEVICE_APC_CG 45
+#define INFRACFG_AO_CCIF_AP_CG 46
+#define INFRACFG_AO_DEBUGSYS_CG 47
+#define INFRACFG_AO_AUDIO_CG 48
+#define INFRACFG_AO_CCIF_MD_CG 49
+#define INFRACFG_AO_DXCC_SEC_CORE_CG 50
+#define INFRACFG_AO_DXCC_AO_CG 51
+#define INFRACFG_AO_DRAMC_F26M_CG 52
+#define INFRACFG_AO_IRTX_CG 53
+#define INFRACFG_AO_DISP_PWM_CG 54
+#define INFRACFG_AO_DPMAIF_CK  55
+#define INFRACFG_AO_AUDIO_26M_BCLK_CK 56
+#define INFRACFG_AO_SPI1_CG 57
+#define INFRACFG_AO_I2C4_CG 58
+#define INFRACFG_AO_MODEM_TEMP_SHARE_CG 59
+#define INFRACFG_AO_SPI2_CG 60
+#define INFRACFG_AO_SPI3_CG 61
+#define INFRACFG_AO_UNIPRO_SCK_CG 62
+#define INFRACFG_AO_UNIPRO_TICK_CG 63
+#define INFRACFG_AO_UFS_MP_SAP_BCLK_CG 64
+#define INFRACFG_AO_MD32_BCLK_CG 65
+#define INFRACFG_AO_SSPM_CG 66
+#define INFRACFG_AO_UNIPRO_MBIST_CG 67
+#define INFRACFG_AO_SSPM_BUS_HCLK_CG 68
+#define INFRACFG_AO_I2C5_CG 69
+#define INFRACFG_AO_I2C5_ARBITER_CG 70
+#define INFRACFG_AO_I2C5_IMM_CG 71
+#define INFRACFG_AO_I2C1_ARBITER_CG 72
+#define INFRACFG_AO_I2C1_IMM_CG 73
+#define INFRACFG_AO_I2C2_ARBITER_CG 74
+#define INFRACFG_AO_I2C2_IMM_CG 75
+#define INFRACFG_AO_SPI4_CG 76
+#define INFRACFG_AO_SPI5_CG 77
+#define INFRACFG_AO_CQ_DMA_CG 78
+#define INFRACFG_AO_UFS_CG 79
+#define INFRACFG_AO_AES_UFSFDE_CG 80
+#define INFRACFG_AO_UFS_TICK_CG 81
+#define INFRACFG_AO_MSDC0_SELF_CG 82
+#define INFRACFG_AO_MSDC1_SELF_CG 83
+#define INFRACFG_AO_MSDC2_SELF_CG 84
+#define INFRACFG_AO_SSPM_26M_SELF_CG 85
+#define INFRACFG_AO_SSPM_32K_SELF_CG 86
+#define INFRACFG_AO_UFS_AXI_CG 87
+#define INFRACFG_AO_I2C6_CG 88
+#define INFRACFG_AO_AP_MSDC0_CG 89
+#define INFRACFG_AO_MD_MSDC0_CG 90
+#define INFRACFG_AO_USB_CG 91
+#define INFRACFG_AO_DEVMPU_BCLK_CG 92
+#define INFRACFG_AO_CCIF2_AP_CG 93
+#define INFRACFG_AO_CCIF2_MD_CG 94
+#define INFRACFG_AO_CCIF3_AP_CG 95
+#define INFRACFG_AO_CCIF3_MD_CG 96
+#define INFRACFG_AO_SEJ_F13M_CG 97
+#define INFRACFG_AO_AES_BCLK_CG 98
+#define INFRACFG_AO_I2C7_CG 99
+#define INFRACFG_AO_I2C8_CG 100
+#define INFRACFG_AO_FBIST2FPC_CG 101
+#define INFRACFG_AO_CCIF4_AP_CG 102
+#define INFRACFG_AO_CCIF4_MD_CG 103
+#define INFRACFG_AO_FADSP_CG 104
+#define INFRACFG_AO_SSUSB_XHCI_CG 105
+#define INFRACFG_AO_SPI6_CG 106
+#define INFRACFG_AO_SPI7_CG 107
+#define INFRACFG_AO_FADSP_26M_CG 108
+#define INFRACFG_AO_FADSP_32K_CG 109
+#define INFRACFG_AO_DEVICE_APC_SYNC_CG 110
+#define INFRACFG_AO_PWM5_CG 111
+#define INFRACFG_AO_MSDCFDE_CG 112
+#define INFRACFG_AO_IMP_IIC_CG 113
+#define INFRACFG_AO_PWM_BCLK6_CG 114
+#define INFRACFG_AO_CLDMA_BCLK_CG 115
+#define INFRACFG_AO_BIST2FPC_CG 116
+#define INFRACFG_AO_AES_UFS_CG 117
+#define INFRACFG_AO_MSDC0_SRCLK_CG 118
+#define INFRACFG_AO_MSDC1_SRCLK_CG 119
+#define INFRACFG_AO_PWRAP_TMR_FO_CG 120
+#define INFRACFG_AO_PWRAP_SPI_FO_CG 121
+#define INFRACFG_AO_PWRAP_SYS_FO_CG 123
+#define INFRACFG_AO_AES_TOP0_BCLK_CG 124
+#define INFRACFG_AO_MCUPM_BCLK_CG 125
+#define INFRACFG_AO_NR_CLK 126
+
+/* MFGCFG */
+#define MFGCFG_BG3D 1
+#define MFGCFG_NR_CLK 2
+
+
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_DISP_MUTEX0		0
+#define CLK_MM_APB_BUS			1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_DISP_RDMA0		3
+#define CLK_MM_DISP_OVL0_2L		4
+#define CLK_MM_DISP_WDMA0		5
+#define CLK_MM_DISP_CCORR1		6
+#define CLK_MM_DISP_RSZ0		7
+#define CLK_MM_DISP_AAL0		8
+#define CLK_MM_DISP_CCORR0		9
+#define CLK_MM_DISP_COLOR0		10
+#define CLK_MM_SMI_INFRA		11
+#define CLK_MM_DISP_DSC_WRAP		12
+#define CLK_MM_DISP_GAMMA0		13
+#define CLK_MM_DISP_POSTMASK0		14
+#define CLK_MM_DISP_SPR0		15
+#define CLK_MM_DISP_DITHER0		16
+#define CLK_MM_SMI_COMMON		17
+#define CLK_MM_DISP_CM0			18
+#define CLK_MM_DSI0			19
+#define CLK_MM_DISP_FAKE_ENG0		20
+#define CLK_MM_DISP_FAKE_ENG1		21
+#define CLK_MM_SMI_GALS			22
+#define CLK_MM_SMI_IOMMU		23
+#define CLK_MM_DSI0_DSI_CK_DOMAIN	24
+#define CLK_MM_DISP_26M			25
+#define CLK_MM_NR_CLK			26
+
+
+/* IMGSYS1 */
+
+#define CLK_IMGSYS1_LARB9		0
+#define CLK_IMGSYS1_LARB10		1
+#define CLK_IMGSYS1_DIP			2
+#define CLK_IMGSYS1_GALS		3
+#define CLK_IMGSYS1_NR_CLK		4
+
+/* IMGSYS2 */
+
+#define CLK_IMGSYS2_LARB9		0
+#define CLK_IMGSYS2_LARB10		1
+#define CLK_IMGSYS2_MFB			2
+#define CLK_IMGSYS2_WPE			3
+#define CLK_IMGSYS2_MSS			4
+#define CLK_IMGSYS2_GALS		5
+#define CLK_IMGSYS2_NR_CLK		6
+
+/* VDEC_GCON */
+#define	VDEC_VDEC	1
+#define	VDEC_LARB1	2
+#define VDEC_LAT	3
+#define VDEC_GCON_NR_CLK 4
+
+/* VENC_GCON */
+#define VENC_GCON_LARB 1
+#define VENC_GCON_VENC 2
+#define VENC_GCON_JPGENC 3
+#define VENC_GCON_GALS 4
+#define VENC_GCON_NR_CLK 5
+
+/* AUDIO */
+#define	AUDIO_AFE		1
+#define	AUDIO_22M		2
+#define	AUDIO_24M		3
+#define	AUDIO_APLL2_TUNER	4
+#define	AUDIO_APLL_TUNER	5
+#define	AUDIO_TDM		6
+#define	AUDIO_ADC		7
+#define	AUDIO_DAC		8
+#define	AUDIO_DAC_PREDIS	9
+#define	AUDIO_TML		10
+#define	AUDIO_NLE		11
+#define	AUDIO_I2S1_BCLK_SW	12
+#define AUDIO_I2S2_BCLK_SW	13
+#define AUDIO_I2S3_BCLK_SW	14
+#define AUDIO_I2S4_BCLK_SW	15
+#define AUDIO_I2S5_BCLK_SW	16
+#define	AUDIO_CONN_I2S_ASRC	17
+#define	AUDIO_GENERAL1_ASRC	18
+#define	AUDIO_GENERAL2_ASRC	19
+#define	AUDIO_DAC_HIRES		20
+#define AUDIO_PDN_ADDA6_ADC	21
+#define AUDIO_ADC_HIRES		22
+#define AUDIO_ADC_HIRES_TML	23
+#define AUDIO_ADDA6_ADC_HIRES	24
+#define AUDIO_3RD_DAC		25
+#define AUDIO_3RD_DAC_PREDIS	26
+#define AUDIO_3RD_DAC_TML	27
+#define AUDIO_3RD_DAC_HIRES	28
+#define AUDIO_ETDM_IN1_BCLK_SW	29
+#define AUDIO_ETDM_OUT1_BCLK_SW	30
+#define AUDIO_NR_CLK		31
+
+/* CAMSYS_MAIN */
+
+#define CLK_CAM_M_LARB13		0
+#define CLK_CAM_M_LARB14		1
+#define CLK_CAM_M_RESERVED0		2
+#define CLK_CAM_M_CAM			3
+#define CLK_CAM_M_CAMTG			4
+#define CLK_CAM_M_SENINF		5
+#define CLK_CAM_M_CAMSV1		6
+#define CLK_CAM_M_CAMSV2		7
+#define CLK_CAM_M_CAMSV3		8
+#define CLK_CAM_M_CCU0			9
+#define CLK_CAM_M_CCU1			10
+#define CLK_CAM_M_MRAW0			11
+#define CLK_CAM_M_RESERVED2		12
+#define CLK_CAM_M_FAKE_ENG		13
+#define CLK_CAM_M_CCU_GALS		14
+#define CLK_CAM_M_CAM2MM_GALS		15
+#define CLK_CAM_M_DFP_VAD		16
+#define CLK_CAM_M_NR_CLK		17
+
+/* CAMSYS_RAWA */
+
+#define CLK_CAM_RA_LARBX		0
+#define CLK_CAM_RA_CAM			1
+#define CLK_CAM_RA_CAMTG		2
+#define CLK_CAM_RA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+
+#define CLK_CAM_RB_LARBX		0
+#define CLK_CAM_RB_CAM			1
+#define CLK_CAM_RB_CAMTG		2
+#define CLK_CAM_RB_NR_CLK		3
+
+/* IPESYS */
+
+#define CLK_IPE_LARB19			0
+#define CLK_IPE_LARB20			1
+#define CLK_IPE_SMI_SUBCOM		2
+#define CLK_IPE_FD			3
+#define CLK_IPE_FE			4
+#define CLK_IPE_RSC			5
+#define CLK_IPE_DPE			6
+#define CLK_IPE_GALS			7
+#define CLK_IPE_NR_CLK			8
+
+/* MDPSYS_CONFIG */
+
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_TDSHP0			1
+#define CLK_MDP_IMG_DL_ASYNC0		2
+#define CLK_MDP_IMG_DL_ASYNC1		3
+#define CLK_MDP_RDMA1			4
+#define CLK_MDP_TDSHP1			5
+#define CLK_MDP_SMI0			6
+#define CLK_MDP_APB_BUS			7
+#define CLK_MDP_WROT0			8
+#define CLK_MDP_RSZ0			9
+#define CLK_MDP_HDR0			10
+#define CLK_MDP_MUTEX0			11
+#define CLK_MDP_WROT1			12
+#define CLK_MDP_RSZ1			13
+#define CLK_MDP_FAKE_ENG0		14
+#define CLK_MDP_AAL0			15
+#define CLK_MDP_AAL1			16
+#define CLK_MDP_COLOR0			17
+#define CLK_MDP_IMG_DL_RELAY0_ASYNC0	18
+#define CLK_MDP_IMG_DL_RELAY1_ASYNC1	19
+#define CLK_MDP_NR_CLK			20
+
+/* IMP_IIC_WRAP */
+
+#define CLK_IMP_AP_CLOCK_RO_I2C0	0
+#define CLK_IMP_AP_CLOCK_RO_I2C1	1
+#define CLK_IMP_AP_CLOCK_RO_I2C2	2
+#define CLK_IMP_AP_CLOCK_RO_I2C3	3
+#define CLK_IMP_AP_CLOCK_RO_I2C4	4
+#define CLK_IMP_AP_CLOCK_RO_I2C5	5
+#define CLK_IMP_AP_CLOCK_RO_I2C6	6
+#define CLK_IMP_AP_CLOCK_RO_I2C7	7
+#define CLK_IMP_AP_CLOCK_RO_I2C8	8
+#define CLK_IMP_AP_CLOCK_RO_I2C9	9
+#define CLK_IMP_NR_CLK			10
+
+/* SCP_SYS */
+#define SCP_SYS_MD1  1
+#define SCP_SYS_CONN  2
+#define SCP_SYS_DIS  3
+#define SCP_SYS_MFG1  4
+#define SCP_SYS_ISP  5
+#define SCP_SYS_VEN  6
+#define SCP_SYS_MFG0  7
+#define SCP_SYS_CAM  8
+#define SCP_SYS_MFG3  9
+#define SCP_SYS_MFG2  10
+#define SCP_SYS_ISP2  11
+#define SCP_SYS_VDE  12
+#define SCP_SYS_IPE  13
+#define SCP_SYS_CAM_RAWA  14
+#define SCP_SYS_CAM_RAWB  15
+#define SCP_SYS_CSI  16
+#define SCP_NR_SYSS  17
+
+#endif				/* _DT_BINDINGS_CLK_MT6781_H */

include/dt-bindings/clock/mt6785-clk.h

@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MT6779_H
+#define _DT_BINDINGS_CLK_MT6779_H
+
+/* TOPCKGEN */
+#define TOP_MUX_AXI 1
+#define TOP_MUX_MM 2
+#define TOP_MUX_CAM 3
+#define TOP_MUX_MFG 4
+#define TOP_MUX_CAMTG 5
+#define TOP_MUX_UART 6
+#define TOP_MUX_SPI 7
+#define TOP_MUX_MSDC50_0_HCLK 8
+#define TOP_MUX_MSDC50_0 9
+#define TOP_MUX_MSDC30_1 10
+#define TOP_MUX_MSDC30_2 11
+#define TOP_MUX_AUDIO 12
+#define TOP_MUX_AUD_INTBUS 13
+#define TOP_MUX_FPWRAP_ULPOSC 14
+#define TOP_MUX_SCP 15
+#define TOP_MUX_ATB 16
+#define TOP_MUX_SSPM 17
+#define TOP_MUX_DPI0 18
+#define TOP_MUX_SCAM 19
+#define TOP_MUX_AUD_1 20
+#define TOP_MUX_AUD_2 21
+#define TOP_MUX_DISP_PWM 22
+#define TOP_MUX_SSUSB_TOP_XHCI 23
+#define TOP_MUX_USB_TOP 24
+#define TOP_MUX_SPM 25
+#define TOP_MUX_I2C 26
+#define TOP_MUX_F52M_MFG 27
+#define TOP_MUX_SENINF 28
+#define TOP_MUX_DXCC 29
+#define TOP_MUX_CAMTG2 30
+#define TOP_MUX_AUD_ENG1 31
+#define TOP_MUX_AUD_ENG2 32
+#define TOP_MUX_FAES_UFSFDE 33
+#define TOP_MUX_FUFS 34
+#define TOP_MUX_IMG	35
+#define TOP_MUX_DSP	36
+#define TOP_MUX_DSP1	37
+#define TOP_MUX_DSP2	38
+#define TOP_MUX_IPU_IF	39
+#define TOP_MUX_CAMTG3	40
+#define TOP_MUX_CAMTG4	41
+#define TOP_MUX_PMICSPI	42
+#define TOP_MAINPLL_CK 43
+#define TOP_MAINPLL_D2 44
+#define TOP_MAINPLL_D3 45
+#define TOP_MAINPLL_D5 46
+#define TOP_MAINPLL_D7 47
+#define TOP_MAINPLL_D2_D2 48
+#define TOP_MAINPLL_D2_D4 49
+#define TOP_MAINPLL_D2_D8 50
+#define TOP_MAINPLL_D2_D16 51
+#define TOP_MAINPLL_D3_D2 52
+#define TOP_MAINPLL_D3_D4 53
+#define TOP_MAINPLL_D3_D8 54
+#define TOP_MAINPLL_D5_D2 55
+#define TOP_MAINPLL_D5_D4 56
+#define TOP_MAINPLL_D7_D2 57
+#define TOP_MAINPLL_D7_D4 58
+#define TOP_UNIVPLL_CK 59
+#define TOP_UNIVPLL_D2 60
+#define TOP_UNIVPLL_D3 61
+#define TOP_UNIVPLL_D5 62
+#define TOP_UNIVPLL_D7 63
+#define TOP_UNIVPLL_D2_D2 64
+#define TOP_UNIVPLL_D2_D4 65
+#define TOP_UNIVPLL_D2_D8 66
+#define TOP_UNIVPLL_D3_D2 67
+#define TOP_UNIVPLL_D3_D4 68
+#define TOP_UNIVPLL_D3_D8 69
+#define TOP_UNIVPLL_D5_D2 70
+#define TOP_UNIVPLL_D5_D4 71
+#define TOP_UNIVPLL_D5_D8 72
+#define TOP_APLL1_CK 73
+#define TOP_APLL1_D2 74
+#define TOP_APLL1_D4 75
+#define TOP_APLL1_D8 76
+#define TOP_APLL2_CK 77
+#define TOP_APLL2_D2 78
+#define TOP_APLL2_D4 79
+#define TOP_APLL2_D8 80
+#define TOP_TVDPLL_CK 81
+#define TOP_TVDPLL_D2 82
+#define TOP_TVDPLL_D4 83
+#define TOP_TVDPLL_D8 84
+#define TOP_TVDPLL_D16 85
+#define TOP_MSDCPLL_CK 86
+#define TOP_MSDCPLL_D2 87
+#define TOP_MSDCPLL_D4 88
+#define TOP_MSDCPLL_D8 89
+#define TOP_MSDCPLL_D16 90
+#define TOP_AD_OSC_CK 91
+#define TOP_OSC_D2 92
+#define TOP_OSC_D4 93
+#define TOP_OSC_D8 94
+#define TOP_OSC_D16 95
+#define TOP_F26M_CK_D2 96
+#define TOP_MFGPLL_CK	97
+#define TOP_UNIVP_192M_CK	98
+#define TOP_UNIVP_192M_D2	99
+#define TOP_UNIVP_192M_D4	100
+#define TOP_UNIVP_192M_D8	101
+#define TOP_UNIVP_192M_D16	102
+#define TOP_UNIVP_192M_D32	103
+#define TOP_MMPLL_CK 104
+#define TOP_MMPLL_D4	105
+#define TOP_MMPLL_D4_D2	106
+#define TOP_MMPLL_D4_D4	107
+#define TOP_MMPLL_D5	108
+#define TOP_MMPLL_D5_D2	109
+#define TOP_MMPLL_D5_D4	110
+#define TOP_MMPLL_D6	111
+#define TOP_MMPLL_D7	112
+#define TOP_CLK26M	113
+#define TOP_CLK13M	114
+#define TOP_MUX_ADSP	115
+#define TOP_MUX_DPMAIF	116
+#define TOP_MUX_VENC	117
+#define TOP_MUX_VDEC	118
+#define TOP_MUX_CAMTM	119
+#define TOP_MUX_PWM	120
+#define TOP_ADSPPLL_CK	121
+#define TOP_I2S0_M_SEL	122
+#define TOP_I2S1_M_SEL	123
+#define TOP_I2S2_M_SEL	124
+#define TOP_I2S3_M_SEL	125
+#define TOP_I2S4_M_SEL	126
+#define TOP_I2S5_M_SEL	127
+#define TOP_APLL12_DIV0	128
+#define TOP_APLL12_DIV1	129
+#define TOP_APLL12_DIV2	130
+#define TOP_APLL12_DIV3	131
+#define TOP_APLL12_DIV4	132
+#define TOP_APLL12_DIVB	133
+#define TOP_APLL12_DIV5	134
+#define TOP_MUX_IPE	135
+#define TOP_MUX_DPE	136
+#define TOP_MUX_CCU	137
+#define TOP_MUX_DSP3	138
+#define TOP_MUX_SENINF1	139
+#define TOP_MUX_SENINF2	140
+#define TOP_MUX_AUDIO_H	141
+#define TOP_MUX_CAMTG5	142
+#define TOP_TVDPLL_MAINPLL_D2_CK 143
+#define TOP_AD_OSC2_CK 144
+#define TOP_OSC2_D2 145
+#define TOP_OSC2_D3 146
+#define TOP_FMEM_466M_CK 147
+#define TOP_ADSPPLL_D4	148
+#define TOP_ADSPPLL_D5	149
+#define TOP_ADSPPLL_D6	150
+#define TOP_OSC_D10 151
+#define TOP_UNIVPLL_D3_D16 152
+#define TOP_APUPLL_CK	153
+#define TOP_NR_CLK	154
+
+/* APMIXED */
+#define APMIXED_ARMPLL_LL 1
+#define APMIXED_ARMPLL_BL 2
+#define APMIXED_ARMPLL_BB 3
+#define APMIXED_CCIPLL 4
+#define APMIXED_MAINPLL 5
+#define APMIXED_UNIV2PLL 6
+#define APMIXED_MSDCPLL 7
+#define APMIXED_ADSPPLL 8
+#define APMIXED_MMPLL 9
+#define APMIXED_MFGPLL 10
+#define APMIXED_TVDPLL 11
+#define APMIXED_APLL1 12
+#define APMIXED_APLL2 13
+#define APMIXED_SSUSB26M 14
+#define APMIXED_APPLL26M 15
+#define APMIXED_MIPIC0_26M 16
+#define APMIXED_MDPLLGP26M 17
+#define APMIXED_MMSYS_F26M 18
+#define APMIXED_UFS26M 19
+#define APMIXED_MIPIC1_26M 20
+#define APMIXED_MEMPLL26M 21
+#define APMIXED_CLKSQ_LVPLL_26M 22
+#define APMIXED_MIPID0_26M 23
+#define APMIXED_MIPID1_26M 24
+#define APMIXED_APUPLL 25
+#define APMIXED_NR_CLK 26
+
+/* CAMSYS */
+#define CAMSYS_LARB6_CGPDN 1
+#define CAMSYS_LARB7_CGPDN 2
+#define CAMSYS_GALS_CGPDN 3
+#define CAMSYS_CAM_CGPDN 4
+#define CAMSYS_CAMTG_CGPDN 5
+#define CAMSYS_SENINF_CGPDN 6
+#define CAMSYS_CAMSV0_CGPDN 7
+#define CAMSYS_CAMSV1_CGPDN 8
+#define CAMSYS_CCU_CGPDN 9
+#define CAMSYS_FAKE_ENG_CGPDN 10
+#define CAMSYS_NR_CLK 11
+
+/* INFRACFG_AO */
+#define INFRACFG_AO_PMIC_CG_TMR 1
+#define INFRACFG_AO_PMIC_CG_AP 2
+#define INFRACFG_AO_PMIC_CG_MD 3
+#define INFRACFG_AO_PMIC_CG_CONN 4
+#define INFRACFG_AO_SCPSYS_CG 5
+#define INFRACFG_AO_SEJ_CG 6
+#define INFRACFG_AO_APXGPT_CG 7
+#define INFRACFG_AO_ICUSB_CG 8
+#define INFRACFG_AO_GCE_CG 9
+#define INFRACFG_AO_THERM_CG 10
+#define INFRACFG_AO_I2C0_CG 11
+#define INFRACFG_AO_I2C1_CG 12
+#define INFRACFG_AO_I2C2_CG 13
+#define INFRACFG_AO_I2C3_CG 14
+#define INFRACFG_AO_PWM_HCLK_CG 15
+#define INFRACFG_AO_PWM1_CG 16
+#define INFRACFG_AO_PWM2_CG 17
+#define INFRACFG_AO_PWM3_CG 18
+#define INFRACFG_AO_PWM4_CG 19
+#define INFRACFG_AO_PWM_CG 20
+#define INFRACFG_AO_UART0_CG 21
+#define INFRACFG_AO_UART1_CG 22
+#define INFRACFG_AO_UART2_CG 23
+#define INFRACFG_AO_UART3_CG 24
+#define INFRACFG_AO_GCE_26M_CG 25
+#define INFRACFG_AO_CQ_DMA_FPC_CG 26
+#define INFRACFG_AO_BTIF_CG 27
+#define INFRACFG_AO_SPI0_CG 28
+#define INFRACFG_AO_MSDC0_CG 29
+#define INFRACFG_AO_MSDC1_CG 30
+#define INFRACFG_AO_MSDC2_CG 31
+#define INFRACFG_AO_MSDC0_SCK_CG 32
+#define INFRACFG_AO_DVFSRC_CG 33
+#define INFRACFG_AO_GCPU_CG 34
+#define INFRACFG_AO_TRNG_CG 35
+#define INFRACFG_AO_AUXADC_CG 36
+#define INFRACFG_AO_CPUM_CG 37
+#define INFRACFG_AO_CCIF1_AP_CG 38
+#define INFRACFG_AO_CCIF1_MD_CG 39
+#define INFRACFG_AO_AUXADC_MD_CG 40
+#define INFRACFG_AO_MSDC1_SCK_CG 41
+#define INFRACFG_AO_MSDC2_SCK_CG 42
+#define INFRACFG_AO_AP_DMA_CG 43
+#define INFRACFG_AO_XIU_CG 44
+#define INFRACFG_AO_DEVICE_APC_CG 45
+#define INFRACFG_AO_CCIF_AP_CG 46
+#define INFRACFG_AO_DEBUGSYS_CG 47
+#define INFRACFG_AO_AUDIO_CG 48
+#define INFRACFG_AO_CCIF_MD_CG 49
+#define INFRACFG_AO_DXCC_SEC_CORE_CG 50
+#define INFRACFG_AO_DXCC_AO_CG 51
+#define INFRACFG_AO_DRAMC_F26M_CG 52
+#define INFRACFG_AO_IRTX_CG 53
+#define INFRACFG_AO_DISP_PWM_CG 54
+#define INFRACFG_AO_DPMAIF_CK  55
+#define INFRACFG_AO_AUDIO_26M_BCLK_CK 56
+#define INFRACFG_AO_SPI1_CG 57
+#define INFRACFG_AO_I2C4_CG 58
+#define INFRACFG_AO_MODEM_TEMP_SHARE_CG 59
+#define INFRACFG_AO_SPI2_CG 60
+#define INFRACFG_AO_SPI3_CG 61
+#define INFRACFG_AO_UNIPRO_SCK_CG 62
+#define INFRACFG_AO_UNIPRO_TICK_CG 63
+#define INFRACFG_AO_UFS_MP_SAP_BCLK_CG 64
+#define INFRACFG_AO_MD32_BCLK_CG 65
+#define INFRACFG_AO_SSPM_CG 66
+#define INFRACFG_AO_UNIPRO_MBIST_CG 67
+#define INFRACFG_AO_SSPM_BUS_HCLK_CG 68
+#define INFRACFG_AO_I2C5_CG 69
+#define INFRACFG_AO_I2C5_ARBITER_CG 70
+#define INFRACFG_AO_I2C5_IMM_CG 71
+#define INFRACFG_AO_I2C1_ARBITER_CG 72
+#define INFRACFG_AO_I2C1_IMM_CG 73
+#define INFRACFG_AO_I2C2_ARBITER_CG 74
+#define INFRACFG_AO_I2C2_IMM_CG 75
+#define INFRACFG_AO_SPI4_CG 76
+#define INFRACFG_AO_SPI5_CG 77
+#define INFRACFG_AO_CQ_DMA_CG 78
+#define INFRACFG_AO_UFS_CG 79
+#define INFRACFG_AO_AES_UFSFDE_CG 80
+#define INFRACFG_AO_UFS_TICK_CG 81
+#define INFRACFG_AO_MSDC0_SELF_CG 82
+#define INFRACFG_AO_MSDC1_SELF_CG 83
+#define INFRACFG_AO_MSDC2_SELF_CG 84
+#define INFRACFG_AO_SSPM_26M_SELF_CG 85
+#define INFRACFG_AO_SSPM_32K_SELF_CG 86
+#define INFRACFG_AO_UFS_AXI_CG 87
+#define INFRACFG_AO_I2C6_CG 88
+#define INFRACFG_AO_AP_MSDC0_CG 89
+#define INFRACFG_AO_MD_MSDC0_CG 90
+#define INFRACFG_AO_USB_CG 91
+#define INFRACFG_AO_DEVMPU_BCLK_CG 92
+#define INFRACFG_AO_CCIF2_AP_CG 93
+#define INFRACFG_AO_CCIF2_MD_CG 94
+#define INFRACFG_AO_CCIF3_AP_CG 95
+#define INFRACFG_AO_CCIF3_MD_CG 96
+#define INFRACFG_AO_SEJ_F13M_CG 97
+#define INFRACFG_AO_AES_BCLK_CG 98
+#define INFRACFG_AO_I2C7_CG 99
+#define INFRACFG_AO_I2C8_CG 100
+#define INFRACFG_AO_FBIST2FPC_CG 101
+#define INFRACFG_AO_CCIF4_AP_CG 102
+#define INFRACFG_AO_CCIF4_MD_CG 103
+#define INFRACFG_AO_FADSP_CG 104
+#define INFRACFG_AO_SSUSB_XHCI_CG 105
+#define INFRACFG_AO_SPI6_CG 106
+#define INFRACFG_AO_SPI7_CG 107
+#define INFRACFG_AO_FADSP_26M_CG 108
+#define INFRACFG_AO_FADSP_32K_CG 109
+#define INFRACFG_AO_DEVICE_APC_SYNC_CG 110
+#define INFRACFG_AO_NR_CLK 111
+
+/* MFGCFG */
+#define MFGCFG_BG3D 1
+#define MFGCFG_NR_CLK 2
+
+/* IMG */
+#define	IMG_LARB5 1
+#define	IMG_LARB4 2
+#define	IMG_DIP 3
+#define	IMG_FDVT 4
+#define	IMG_DPE 5
+#define	IMG_RSC 6
+#define	IMG_MFB	7
+#define	IMG_WPE_A	8
+#define	IMG_WPE_B 9
+#define	IMG_OWE 10
+#define IMG_NR_CLK 11
+
+
+/* MMSYS_CONFIG */
+#define	MMSYS_SMI_COMMON 1
+#define	MMSYS_SMI_LARB0	2
+#define	MMSYS_SMI_LARB1	3
+#define	MMSYS_GALS_COMM0	4
+#define	MMSYS_GALS_COMM1	5
+#define	MMSYS_GALS_CCU2MM	6
+#define	MMSYS_GALS_IPU12MM	7
+#define	MMSYS_GALS_IMG2MM	8
+#define	MMSYS_GALS_CAM2MM	9
+#define	MMSYS_GALS_IPU2MM	10
+#define	MMSYS_MDP_DL_TXCK	11
+#define	MMSYS_IPU_DL_TXCK	12
+#define	MMSYS_MDP_RDMA0	13
+#define	MMSYS_MDP_RDMA1	14
+#define	MMSYS_MDP_RSZ0	15
+#define	MMSYS_MDP_RSZ1	16
+#define	MMSYS_MDP_TDSHP	17
+#define	MMSYS_MDP_WROT0	18
+#define	MMSYS_FAKE_ENG	19
+#define	MMSYS_DISP_OVL0	20
+#define	MMSYS_DISP_OVL0_2L	21
+#define	MMSYS_DISP_OVL1_2L	22
+#define	MMSYS_DISP_RDMA0	23
+#define	MMSYS_DISP_RDMA1	24
+#define	MMSYS_DISP_WDMA0	25
+#define	MMSYS_DISP_COLOR0	26
+#define	MMSYS_DISP_CCORR0	27
+#define	MMSYS_DISP_AAL0		28
+#define	MMSYS_DISP_GAMMA0	29
+#define	MMSYS_DISP_DITHER0	30
+#define	MMSYS_DISP_SPLIT	31
+#define	MMSYS_DSI0_MM_CK	32
+#define	MMSYS_DSI0_IF_CK	33
+#define	MMSYS_DPI_MM_CK	34
+#define	MMSYS_DPI_IF_CK	35
+#define	MMSYS_FAKE_ENG2	36
+#define	MMSYS_MDP_DL_RX_CK	37
+#define	MMSYS_IPU_DL_RX_CK	38
+#define	MMSYS_26M	39
+#define	MMSYS_MMSYS_R2Y	40
+#define	MMSYS_DISP_RSZ	41
+#define MMSYS_MDP_WDMA0 42
+#define MMSYS_MDP_AAL 43
+#define MMSYS_MDP_HDR 44
+#define MMSYS_DBI_MM_CK 45
+#define MMSYS_DBI_IF_CK 46
+#define	MMSYS_MDP_WROT1	47
+#define	MMSYS_DISP_POSTMASK0 48
+#define	MMSYS_DISP_HRT_BW 49
+#define	MMSYS_DISP_OVL_FBDC 50
+#define MMSYS_CONFIG_NR_CLK 51
+
+/* VDEC_GCON */
+#define	VDEC_VDEC	1
+#define	VDEC_LARB1	2
+#define VDEC_GCON_NR_CLK 3
+
+/* VENC_GCON */
+#define VENC_GCON_LARB 1
+#define VENC_GCON_VENC 2
+#define VENC_GCON_JPGENC 3
+#define VENC_GCON_GALS 4
+#define VENC_GCON_NR_CLK 5
+
+/* AUDIO */
+#define	AUDIO_AFE		1
+#define	AUDIO_22M		2
+#define	AUDIO_24M		3
+#define	AUDIO_APLL2_TUNER	4
+#define	AUDIO_APLL_TUNER	5
+#define	AUDIO_TDM		6
+#define	AUDIO_ADC		7
+#define	AUDIO_DAC		8
+#define	AUDIO_DAC_PREDIS	9
+#define	AUDIO_TML		10
+#define	AUDIO_NLE		11
+#define	AUDIO_I2S1_BCLK_SW	12
+#define AUDIO_I2S2_BCLK_SW	13
+#define AUDIO_I2S3_BCLK_SW	14
+#define AUDIO_I2S4_BCLK_SW	15
+#define AUDIO_I2S5_BCLK_SW	16
+#define	AUDIO_CONN_I2S_ASRC	17
+#define	AUDIO_GENERAL1_ASRC	18
+#define	AUDIO_GENERAL2_ASRC	19
+#define	AUDIO_DAC_HIRES		20
+#define AUDIO_PDN_ADDA6_ADC	21
+#define AUDIO_ADC_HIRES		22
+#define AUDIO_ADC_HIRES_TML	23
+#define AUDIO_ADDA6_ADC_HIRES	24
+#define AUDIO_3RD_DAC		25
+#define AUDIO_3RD_DAC_PREDIS	26
+#define AUDIO_3RD_DAC_TML	27
+#define AUDIO_3RD_DAC_HIRES	28
+#define AUDIO_NR_CLK		29
+
+/* APU_CONN */
+#define	APU_CONN_APU_CG	1
+#define	APU_CONN_AHB_CG	2
+#define	APU_CONN_AXI_CG	3
+#define	APU_CONN_ISP_CG	4
+#define	APU_CONN_CAM_ADL_CG	5
+#define	APU_CONN_IMG_ADL_CG	6
+#define APU_CONN_EMI_26M_CG	7
+#define APU_CONN_VPU_UDI_CG	8
+#define APU_CONN_NR_CLK		9
+
+/* APU_CORE0 */
+#define	APU0_JTAG_CG	1
+#define	APU0_AXI_M_CG	2
+#define	APU0_APU_CG	3
+#define APU0_NR_CLK	4
+
+/* APU_CORE1 */
+#define	APU1_JTAG_CG	1
+#define	APU1_AXI_M_CG	2
+#define	APU1_APU_CG	3
+#define APU1_NR_CLK	4
+
+/* APU_VCORE */
+#define	APU_VCORE_AHB_CG	1
+#define	APU_VCORE_AXI_CG	2
+#define	APU_VCORE_ADL_CG	3
+#define	APU_VCORE_QOS_CG	4
+#define APU_VCORE_NR_CLK	5
+
+/* SCP_SYS */
+#define SCP_SYS_MD1  1
+#define SCP_SYS_CONN  2
+#define SCP_SYS_DIS  3
+#define SCP_SYS_MFG1  4
+#define SCP_SYS_ISP  5
+#define SCP_SYS_VEN  6
+#define SCP_SYS_MFG0  7
+#define SCP_SYS_AUDIO  8
+#define SCP_SYS_CAM  9
+#define SCP_SYS_MFG3  10
+#define SCP_SYS_MFG2  11
+#define SCP_SYS_MFG5  12
+#define SCP_SYS_VDE  13
+#define SCP_SYS_VPU_VCORE_DORMANT  14
+#define SCP_SYS_VPU_VCORE_SHUTDOWN  15
+#define SCP_SYS_VPU_CORE0_DORMANT  16
+#define SCP_SYS_VPU_CORE0_SHUTDOWN  17
+#define SCP_SYS_VPU_CORE1_DORMANT  18
+#define SCP_SYS_VPU_CORE1_SHUTDOWN  19
+#define SCP_SYS_VPU_CONN_DORMANT  20
+#define SCP_SYS_VPU_CONN_SHUTDOWN  21
+#define SCP_SYS_VPU_CORE2_DORMANT  22
+#define SCP_SYS_VPU_CORE2_SHUTDOWN  23
+#define SCP_SYS_MFG4  24
+#define SCP_NR_SYSS  25
+
+#endif				/* _DT_BINDINGS_CLK_MT6779_H */

include/dt-bindings/clock/mt6797-clk.h

@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6797_H
+#define _DT_BINDINGS_CLK_MT6797_H
+
+/* TOPCKGEN */
+#define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE	1
+#define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX		2
+#define	CLK_TOP_MUX_AXI				3
+#define	CLK_TOP_MUX_MEM				4
+#define	CLK_TOP_MUX_DDRPHYCFG			5
+#define	CLK_TOP_MUX_MM				6
+#define	CLK_TOP_MUX_PWM				7
+#define	CLK_TOP_MUX_VDEC			8
+#define	CLK_TOP_MUX_VENC			9
+#define	CLK_TOP_MUX_MFG				10
+#define	CLK_TOP_MUX_CAMTG			11
+#define	CLK_TOP_MUX_UART			12
+#define	CLK_TOP_MUX_SPI				13
+#define	CLK_TOP_MUX_ULPOSC_SPI_CK_MUX		14
+#define	CLK_TOP_MUX_USB20			15
+#define	CLK_TOP_MUX_MSDC50_0_HCLK		16
+#define	CLK_TOP_MUX_MSDC50_0			17
+#define	CLK_TOP_MUX_MSDC30_1			18
+#define	CLK_TOP_MUX_MSDC30_2			19
+#define	CLK_TOP_MUX_AUDIO			20
+#define	CLK_TOP_MUX_AUD_INTBUS			21
+#define	CLK_TOP_MUX_PMICSPI			22
+#define	CLK_TOP_MUX_SCP				23
+#define	CLK_TOP_MUX_ATB				24
+#define	CLK_TOP_MUX_MJC				25
+#define	CLK_TOP_MUX_DPI0			26
+#define	CLK_TOP_MUX_AUD_1			27
+#define	CLK_TOP_MUX_AUD_2			28
+#define	CLK_TOP_MUX_SSUSB_TOP_SYS		29
+#define	CLK_TOP_MUX_SPM				30
+#define	CLK_TOP_MUX_BSI_SPI			31
+#define	CLK_TOP_MUX_AUDIO_H			32
+#define	CLK_TOP_MUX_ANC_MD32			33
+#define	CLK_TOP_MUX_MFG_52M			34
+#define	CLK_TOP_SYSPLL_CK			35
+#define	CLK_TOP_SYSPLL_D2			36
+#define	CLK_TOP_SYSPLL1_D2			37
+#define	CLK_TOP_SYSPLL1_D4			38
+#define	CLK_TOP_SYSPLL1_D8			39
+#define	CLK_TOP_SYSPLL1_D16			40
+#define	CLK_TOP_SYSPLL_D3			41
+#define	CLK_TOP_SYSPLL_D3_D3			42
+#define	CLK_TOP_SYSPLL2_D2			43
+#define	CLK_TOP_SYSPLL2_D4			44
+#define	CLK_TOP_SYSPLL2_D8			45
+#define	CLK_TOP_SYSPLL_D5			46
+#define	CLK_TOP_SYSPLL3_D2			47
+#define	CLK_TOP_SYSPLL3_D4			48
+#define	CLK_TOP_SYSPLL_D7			49
+#define	CLK_TOP_SYSPLL4_D2			50
+#define	CLK_TOP_SYSPLL4_D4			51
+#define	CLK_TOP_UNIVPLL_CK			52
+#define	CLK_TOP_UNIVPLL_D7			53
+#define	CLK_TOP_UNIVPLL_D26			54
+#define	CLK_TOP_SSUSB_PHY_48M_CK		55
+#define	CLK_TOP_USB_PHY48M_CK			56
+#define	CLK_TOP_UNIVPLL_D2			57
+#define	CLK_TOP_UNIVPLL1_D2			58
+#define	CLK_TOP_UNIVPLL1_D4			59
+#define	CLK_TOP_UNIVPLL1_D8			60
+#define	CLK_TOP_UNIVPLL_D3			61
+#define	CLK_TOP_UNIVPLL2_D2			62
+#define	CLK_TOP_UNIVPLL2_D4			63
+#define	CLK_TOP_UNIVPLL2_D8			64
+#define	CLK_TOP_UNIVPLL_D5			65
+#define	CLK_TOP_UNIVPLL3_D2			66
+#define	CLK_TOP_UNIVPLL3_D4			67
+#define	CLK_TOP_UNIVPLL3_D8			68
+#define	CLK_TOP_ULPOSC_CK_ORG			69
+#define	CLK_TOP_ULPOSC_CK			70
+#define	CLK_TOP_ULPOSC_D2			71
+#define	CLK_TOP_ULPOSC_D3			72
+#define	CLK_TOP_ULPOSC_D4			73
+#define	CLK_TOP_ULPOSC_D8			74
+#define	CLK_TOP_ULPOSC_D10			75
+#define	CLK_TOP_APLL1_CK			76
+#define	CLK_TOP_APLL2_CK			77
+#define	CLK_TOP_MFGPLL_CK			78
+#define	CLK_TOP_MFGPLL_D2			79
+#define	CLK_TOP_IMGPLL_CK			80
+#define	CLK_TOP_IMGPLL_D2			81
+#define	CLK_TOP_IMGPLL_D4			82
+#define	CLK_TOP_CODECPLL_CK			83
+#define	CLK_TOP_CODECPLL_D2			84
+#define	CLK_TOP_VDECPLL_CK			85
+#define	CLK_TOP_TVDPLL_CK			86
+#define	CLK_TOP_TVDPLL_D2			87
+#define	CLK_TOP_TVDPLL_D4			88
+#define	CLK_TOP_TVDPLL_D8			89
+#define	CLK_TOP_TVDPLL_D16			90
+#define	CLK_TOP_MSDCPLL_CK			91
+#define	CLK_TOP_MSDCPLL_D2			92
+#define	CLK_TOP_MSDCPLL_D4			93
+#define	CLK_TOP_MSDCPLL_D8			94
+#define	CLK_TOP_NR				95
+
+/* APMIXED_SYS */
+#define CLK_APMIXED_MAINPLL			1
+#define CLK_APMIXED_UNIVPLL			2
+#define CLK_APMIXED_MFGPLL			3
+#define CLK_APMIXED_MSDCPLL			4
+#define CLK_APMIXED_IMGPLL			5
+#define CLK_APMIXED_TVDPLL			6
+#define CLK_APMIXED_CODECPLL			7
+#define CLK_APMIXED_VDECPLL			8
+#define CLK_APMIXED_APLL1			9
+#define CLK_APMIXED_APLL2			10
+#define CLK_APMIXED_NR				11
+
+/* INFRA_SYS */
+#define	CLK_INFRA_PMIC_TMR			1
+#define	CLK_INFRA_PMIC_AP			2
+#define	CLK_INFRA_PMIC_MD			3
+#define	CLK_INFRA_PMIC_CONN			4
+#define	CLK_INFRA_SCP				5
+#define	CLK_INFRA_SEJ				6
+#define	CLK_INFRA_APXGPT			7
+#define	CLK_INFRA_SEJ_13M			8
+#define	CLK_INFRA_ICUSB				9
+#define	CLK_INFRA_GCE				10
+#define	CLK_INFRA_THERM				11
+#define	CLK_INFRA_I2C0				12
+#define	CLK_INFRA_I2C1				13
+#define	CLK_INFRA_I2C2				14
+#define	CLK_INFRA_I2C3				15
+#define	CLK_INFRA_PWM_HCLK			16
+#define	CLK_INFRA_PWM1				17
+#define	CLK_INFRA_PWM2				18
+#define	CLK_INFRA_PWM3				19
+#define	CLK_INFRA_PWM4				20
+#define	CLK_INFRA_PWM				21
+#define	CLK_INFRA_UART0				22
+#define	CLK_INFRA_UART1				23
+#define	CLK_INFRA_UART2				24
+#define	CLK_INFRA_UART3				25
+#define	CLK_INFRA_MD2MD_CCIF_0			26
+#define	CLK_INFRA_MD2MD_CCIF_1			27
+#define	CLK_INFRA_MD2MD_CCIF_2			28
+#define	CLK_INFRA_FHCTL				29
+#define	CLK_INFRA_BTIF				30
+#define	CLK_INFRA_MD2MD_CCIF_3			31
+#define	CLK_INFRA_SPI				32
+#define	CLK_INFRA_MSDC0				33
+#define	CLK_INFRA_MD2MD_CCIF_4			34
+#define	CLK_INFRA_MSDC1				35
+#define	CLK_INFRA_MSDC2				36
+#define	CLK_INFRA_MD2MD_CCIF_5			37
+#define	CLK_INFRA_GCPU				38
+#define	CLK_INFRA_TRNG				39
+#define	CLK_INFRA_AUXADC			40
+#define	CLK_INFRA_CPUM				41
+#define	CLK_INFRA_AP_C2K_CCIF_0			42
+#define	CLK_INFRA_AP_C2K_CCIF_1			43
+#define	CLK_INFRA_CLDMA				44
+#define	CLK_INFRA_DISP_PWM			45
+#define	CLK_INFRA_AP_DMA			46
+#define	CLK_INFRA_DEVICE_APC			47
+#define	CLK_INFRA_L2C_SRAM			48
+#define	CLK_INFRA_CCIF_AP			49
+#define	CLK_INFRA_AUDIO				50
+#define	CLK_INFRA_CCIF_MD			51
+#define	CLK_INFRA_DRAMC_F26M			52
+#define	CLK_INFRA_I2C4				53
+#define	CLK_INFRA_I2C_APPM			54
+#define	CLK_INFRA_I2C_GPUPM			55
+#define	CLK_INFRA_I2C2_IMM			56
+#define	CLK_INFRA_I2C2_ARB			57
+#define	CLK_INFRA_I2C3_IMM			58
+#define	CLK_INFRA_I2C3_ARB			59
+#define	CLK_INFRA_I2C5				60
+#define	CLK_INFRA_SYS_CIRQ			61
+#define	CLK_INFRA_SPI1				62
+#define	CLK_INFRA_DRAMC_B_F26M			63
+#define	CLK_INFRA_ANC_MD32			64
+#define	CLK_INFRA_ANC_MD32_32K			65
+#define	CLK_INFRA_DVFS_SPM1			66
+#define	CLK_INFRA_AES_TOP0			67
+#define	CLK_INFRA_AES_TOP1			68
+#define	CLK_INFRA_SSUSB_BUS			69
+#define	CLK_INFRA_SPI2				70
+#define	CLK_INFRA_SPI3				71
+#define	CLK_INFRA_SPI4				72
+#define	CLK_INFRA_SPI5				73
+#define	CLK_INFRA_IRTX				74
+#define	CLK_INFRA_SSUSB_SYS			75
+#define	CLK_INFRA_SSUSB_REF			76
+#define	CLK_INFRA_AUDIO_26M			77
+#define	CLK_INFRA_AUDIO_26M_PAD_TOP		78
+#define	CLK_INFRA_MODEM_TEMP_SHARE		79
+#define	CLK_INFRA_VAD_WRAP_SOC			80
+#define	CLK_INFRA_DRAMC_CONF			81
+#define	CLK_INFRA_DRAMC_B_CONF			82
+#define	CLK_INFRA_MFG_VCG			83
+#define	CLK_INFRA_13M				84
+#define	CLK_INFRA_NR				85
+
+/* IMG_SYS */
+#define	CLK_IMG_FDVT				1
+#define	CLK_IMG_DPE				2
+#define	CLK_IMG_DIP				3
+#define	CLK_IMG_LARB6				4
+#define	CLK_IMG_NR				5
+
+/* MM_SYS */
+#define	CLK_MM_SMI_COMMON			1
+#define	CLK_MM_SMI_LARB0			2
+#define	CLK_MM_SMI_LARB5			3
+#define	CLK_MM_CAM_MDP				4
+#define	CLK_MM_MDP_RDMA0			5
+#define	CLK_MM_MDP_RDMA1			6
+#define	CLK_MM_MDP_RSZ0				7
+#define	CLK_MM_MDP_RSZ1				8
+#define	CLK_MM_MDP_RSZ2				9
+#define	CLK_MM_MDP_TDSHP			10
+#define	CLK_MM_MDP_COLOR			11
+#define	CLK_MM_MDP_WDMA				12
+#define	CLK_MM_MDP_WROT0			13
+#define	CLK_MM_MDP_WROT1			14
+#define	CLK_MM_FAKE_ENG				15
+#define	CLK_MM_DISP_OVL0			16
+#define	CLK_MM_DISP_OVL1			17
+#define	CLK_MM_DISP_OVL0_2L			18
+#define	CLK_MM_DISP_OVL1_2L			19
+#define	CLK_MM_DISP_RDMA0			20
+#define	CLK_MM_DISP_RDMA1			21
+#define	CLK_MM_DISP_WDMA0			22
+#define	CLK_MM_DISP_WDMA1			23
+#define	CLK_MM_DISP_COLOR			24
+#define	CLK_MM_DISP_CCORR			25
+#define	CLK_MM_DISP_AAL				26
+#define	CLK_MM_DISP_GAMMA			27
+#define	CLK_MM_DISP_OD				28
+#define	CLK_MM_DISP_DITHER			29
+#define	CLK_MM_DISP_UFOE			30
+#define	CLK_MM_DISP_DSC				31
+#define	CLK_MM_DISP_SPLIT			32
+#define	CLK_MM_DSI0_MM_CLOCK			33
+#define	CLK_MM_DSI1_MM_CLOCK			34
+#define	CLK_MM_DPI_MM_CLOCK			35
+#define	CLK_MM_DPI_INTERFACE_CLOCK		36
+#define	CLK_MM_LARB4_AXI_ASIF_MM_CLOCK		37
+#define	CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK		38
+#define	CLK_MM_DISP_OVL0_MOUT_CLOCK		39
+#define	CLK_MM_FAKE_ENG2			40
+#define	CLK_MM_DSI0_INTERFACE_CLOCK		41
+#define	CLK_MM_DSI1_INTERFACE_CLOCK		42
+#define	CLK_MM_NR				43
+
+/* VDEC_SYS */
+#define	CLK_VDEC_CKEN_ENG			1
+#define	CLK_VDEC_ACTIVE				2
+#define	CLK_VDEC_CKEN				3
+#define	CLK_VDEC_LARB1_CKEN			4
+#define	CLK_VDEC_NR				5
+
+/* VENC_SYS */
+#define	CLK_VENC_0				1
+#define	CLK_VENC_1				2
+#define	CLK_VENC_2				3
+#define	CLK_VENC_3				4
+#define	CLK_VENC_NR				5
+
+#endif /* _DT_BINDINGS_CLK_MT6797_H */

include/dt-bindings/clock/mt6833-clk.h

@@ -0,0 +1,676 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+#ifndef _DT_BINDINGS_CLK_MT6833_H
+#define _DT_BINDINGS_CLK_MT6833_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL_LL		0
+#define CLK_APMIXED_ARMPLL_BL0		1
+#define CLK_APMIXED_CCIPLL		2
+#define CLK_APMIXED_MPLL		3
+#define CLK_APMIXED_MAINPLL		4
+#define CLK_APMIXED_UNIVPLL		5
+#define CLK_APMIXED_MSDCPLL		6
+#define CLK_APMIXED_MMPLL		7
+#define CLK_APMIXED_ADSPPLL		8
+#define CLK_APMIXED_MFGPLL		9
+#define CLK_APMIXED_TVDPLL		10
+#define CLK_APMIXED_APLL1		11
+#define CLK_APMIXED_APLL2		12
+#define CLK_APMIXED_NPUPLL		13
+#define CLK_APMIXED_USBPLL		14
+#define CLK_APMIXED_PLL_MIPIC0_26M_EN	15
+#define CLK_APMIXED_PLL_MIPIC1_26M_EN	16
+#define CLK_APMIXED_PLL_MIPID0_26M_EN	17
+#define CLK_APMIXED_NR_CLK		18
+
+/* TOPCKGEN */
+
+#define CLK_TOP_MAINPLL			0
+#define CLK_TOP_MAINPLL_D3		1
+#define CLK_TOP_MAINPLL_D4		2
+#define CLK_TOP_MAINPLL_D4_D2		3
+#define CLK_TOP_MAINPLL_D4_D4		4
+#define CLK_TOP_MAINPLL_D4_D8		5
+#define CLK_TOP_MAINPLL_D4_D16		6
+#define CLK_TOP_MAINPLL_D5		7
+#define CLK_TOP_MAINPLL_D5_D2		8
+#define CLK_TOP_MAINPLL_D5_D4		9
+#define CLK_TOP_MAINPLL_D5_D8		10
+#define CLK_TOP_MAINPLL_D6		11
+#define CLK_TOP_MAINPLL_D6_D2		12
+#define CLK_TOP_MAINPLL_D6_D4		13
+#define CLK_TOP_MAINPLL_D6_D8		14
+#define CLK_TOP_MAINPLL_D7		15
+#define CLK_TOP_MAINPLL_D7_D2		16
+#define CLK_TOP_MAINPLL_D7_D4		17
+#define CLK_TOP_MAINPLL_D7_D8		18
+#define CLK_TOP_MAINPLL_D9		19
+#define CLK_TOP_UNIVPLL_192M		20
+#define CLK_TOP_UNIVPLL_192M_D2		21
+#define CLK_TOP_UNIVPLL_192M_D4		22
+#define CLK_TOP_UNIVPLL_192M_D8		23
+#define CLK_TOP_UNIVPLL_192M_D16	24
+#define CLK_TOP_UNIVPLL_192M_D32	25
+#define CLK_TOP_UNIVPLL			26
+#define CLK_TOP_UNIVPLL_D2		27
+#define CLK_TOP_UNIVPLL_D3		28
+#define CLK_TOP_UNIVPLL_D4		29
+#define CLK_TOP_UNIVPLL_D4_D2		30
+#define CLK_TOP_UNIVPLL_D4_D4		31
+#define CLK_TOP_UNIVPLL_D4_D8		32
+#define CLK_TOP_UNIVPLL_D5		33
+#define CLK_TOP_UNIVPLL_D5_D2		34
+#define CLK_TOP_UNIVPLL_D5_D4		35
+#define CLK_TOP_UNIVPLL_D5_D8		36
+#define CLK_TOP_UNIVPLL_D5_D16		37
+#define CLK_TOP_UNIVPLL_D6		38
+#define CLK_TOP_UNIVPLL_D6_D2		39
+#define CLK_TOP_UNIVPLL_D6_D4		40
+#define CLK_TOP_UNIVPLL_D6_D8		41
+#define CLK_TOP_UNIVPLL_D6_D16		42
+#define CLK_TOP_UNIVPLL_D7		43
+#define CLK_TOP_UNIVPLL_D7_D2		44
+#define CLK_TOP_MFGPLL			45
+#define CLK_TOP_APLL1			46
+#define CLK_TOP_APLL1_D2		47
+#define CLK_TOP_APLL1_D4		48
+#define CLK_TOP_APLL1_D8		49
+#define CLK_TOP_APLL2			50
+#define CLK_TOP_APLL2_D2		51
+#define CLK_TOP_APLL2_D4		52
+#define CLK_TOP_APLL2_D8		53
+#define CLK_TOP_ADSPPLL			54
+#define CLK_TOP_MMPLL_D3		55
+#define CLK_TOP_MMPLL_D4		56
+#define CLK_TOP_MMPLL_D4_D2		57
+#define CLK_TOP_MMPLL_D4_D4		58
+#define CLK_TOP_MMPLL_D5		59
+#define CLK_TOP_MMPLL_D5_D2		60
+#define CLK_TOP_MMPLL_D5_D4		61
+#define CLK_TOP_MMPLL_D6		62
+#define CLK_TOP_MMPLL_D6_D2		63
+#define CLK_TOP_MMPLL_D7		64
+#define CLK_TOP_MMPLL_D9		65
+#define CLK_TOP_NPUPLL			66
+#define CLK_TOP_TVDPLL			67
+#define CLK_TOP_TVDPLL_D2		68
+#define CLK_TOP_TVDPLL_D4		69
+#define CLK_TOP_TVDPLL_D8		70
+#define CLK_TOP_TVDPLL_D16		71
+#define CLK_TOP_MSDCPLL			72
+#define CLK_TOP_MSDCPLL_D2		73
+#define CLK_TOP_MSDCPLL_D4		74
+#define CLK_TOP_MSDCPLL_D8		75
+#define CLK_TOP_MSDCPLL_D16		76
+#define CLK_TOP_OSC			77
+#define CLK_TOP_OSC_D2			78
+#define CLK_TOP_OSC_D4			79
+#define CLK_TOP_OSC_D8			80
+#define CLK_TOP_OSC_D16			81
+#define CLK_TOP_OSC_D10			82
+#define CLK_TOP_OSC_D20			83
+#define CLK_TOP_OSC_CK_2		84
+#define CLK_TOP_OSC2_D2			85
+#define CLK_TOP_TCK_26M_MX9		86
+#define CLK_TOP_CSW_F26M_CK_D2		87
+#define CLK_TOP_F26M			88
+#define CLK_TOP_FRTC			89
+#define CLK_TOP_AXI			90
+#define CLK_TOP_SPM			91
+#define CLK_TOP_SCP			92
+#define CLK_TOP_BUS			93
+#define CLK_TOP_DISP			94
+#define CLK_TOP_MDP			95
+#define CLK_TOP_IMG1			96
+#define CLK_TOP_IMG2			97
+#define CLK_TOP_IPE			98
+#define CLK_TOP_DPE			99
+#define CLK_TOP_CAM			100
+#define CLK_TOP_CCU			101
+#define CLK_TOP_DSP			102
+#define CLK_TOP_DSP1			103
+#define CLK_TOP_DSP2			104
+#define CLK_TOP_IPU_IF			105
+#define CLK_TOP_MFG_REF			106
+#define CLK_TOP_FCAMTG			107
+#define CLK_TOP_FCAMTG2			108
+#define CLK_TOP_FCAMTG3			109
+#define CLK_TOP_FCAMTG4			110
+#define CLK_TOP_FCAMTG5			111
+#define CLK_TOP_FUART			112
+#define CLK_TOP_SPI			113
+#define CLK_TOP_MSDC50_0_HCLK		114
+#define CLK_TOP_MSDC50_0		115
+#define CLK_TOP_MSDC30_1		116
+#define CLK_TOP_AUDIO			117
+#define CLK_TOP_AUD_INTBUS		118
+#define CLK_TOP_FPWRAP_ULPOSC		119
+#define CLK_TOP_ATB			120
+#define CLK_TOP_SSPM			121
+#define CLK_TOP_SCAM			122
+#define CLK_TOP_FDISP_PWM		123
+#define CLK_TOP_FUSB_TOP		124
+#define CLK_TOP_FSSUSB_XHCI		125
+#define CLK_TOP_I2C			126
+#define CLK_TOP_FSENINF			127
+#define CLK_TOP_FSENINF1		128
+#define CLK_TOP_FSENINF2		129
+#define CLK_TOP_DXCC			130
+#define CLK_TOP_AUD_ENGEN1		131
+#define CLK_TOP_AUD_ENGEN2		132
+#define CLK_TOP_AES_UFSFDE		133
+#define CLK_TOP_UFS			134
+#define CLK_TOP_AUD_1			135
+#define CLK_TOP_AUD_2			136
+#define CLK_TOP_ADSP			137
+#define CLK_TOP_DPMAIF_MAIN		138
+#define CLK_TOP_VENC			139
+#define CLK_TOP_VDEC			140
+#define CLK_TOP_CAMTM			141
+#define CLK_TOP_PWM			142
+#define CLK_TOP_AUDIO_H			143
+#define CLK_TOP_SPMI_MST		144
+#define CLK_TOP_DVFSRC			145
+#define CLK_TOP_AES_MSDCFDE		146
+#define CLK_TOP_MCUPM			147
+#define CLK_TOP_SFLASH			148
+#define CLK_TOP_DSI_OCC			149
+#define CLK_TOP_UNIPLL_SES		150
+#define CLK_TOP_I2C_PSEUDO		151
+#define CLK_TOP_APDMA_PSEUDO		152
+#define CLK_TOP_AXI_SEL			153
+#define CLK_TOP_SPM_SEL			154
+#define CLK_TOP_SCP_SEL			155
+#define CLK_TOP_BUS_AXIMEM_SEL		156
+#define CLK_TOP_DISP_SEL		157
+#define CLK_TOP_MDP_SEL			158
+#define CLK_TOP_IMG1_SEL		159
+#define CLK_TOP_IMG2_SEL		160
+#define CLK_TOP_IPE_SEL			161
+#define CLK_TOP_DPE_SEL			162
+#define CLK_TOP_CAM_SEL			163
+#define CLK_TOP_CCU_SEL			164
+#define CLK_TOP_DSP_SEL			165
+#define CLK_TOP_DSP1_SEL		166
+#define CLK_TOP_DSP1_NPUPLL_SEL		167
+#define CLK_TOP_DSP2_SEL		168
+#define CLK_TOP_DSP2_NPUPLL_SEL		169
+#define CLK_TOP_IPU_IF_SEL		170
+#define CLK_TOP_MFG_REF_SEL		171
+#define CLK_TOP_MFG_PLL_SEL		172
+#define CLK_TOP_CAMTG_SEL		173
+#define CLK_TOP_CAMTG2_SEL		174
+#define CLK_TOP_CAMTG3_SEL		175
+#define CLK_TOP_CAMTG4_SEL		176
+#define CLK_TOP_CAMTG5_SEL		177
+#define CLK_TOP_UART_SEL		178
+#define CLK_TOP_SPI_SEL			179
+#define CLK_TOP_MSDC50_0_HCLK_SEL	180
+#define CLK_TOP_MSDC50_0_SEL		181
+#define CLK_TOP_MSDC30_1_SEL		182
+#define CLK_TOP_AUDIO_SEL		183
+#define CLK_TOP_AUD_INTBUS_SEL		184
+#define CLK_TOP_PWRAP_ULPOSC_SEL	185
+#define CLK_TOP_ATB_SEL			186
+#define CLK_TOP_SSPM_SEL		187
+#define CLK_TOP_SCAM_SEL		188
+#define CLK_TOP_DISP_PWM_SEL		189
+#define CLK_TOP_USB_TOP_SEL		190
+#define CLK_TOP_SSUSB_XHCI_SEL		191
+#define CLK_TOP_I2C_SEL			192
+#define CLK_TOP_SENINF_SEL		193
+#define CLK_TOP_SENINF1_SEL		194
+#define CLK_TOP_SENINF2_SEL		195
+#define CLK_TOP_DXCC_SEL		196
+#define CLK_TOP_AUD_ENGEN1_SEL		197
+#define CLK_TOP_AUD_ENGEN2_SEL		198
+#define CLK_TOP_AES_UFSFDE_SEL		199
+#define CLK_TOP_UFS_SEL			200
+#define CLK_TOP_AUD_1_SEL		201
+#define CLK_TOP_AUD_2_SEL		202
+#define CLK_TOP_ADSP_SEL		203
+#define CLK_TOP_DPMAIF_MAIN_SEL		204
+#define CLK_TOP_VENC_SEL		205
+#define CLK_TOP_VDEC_SEL		206
+#define CLK_TOP_CAMTM_SEL		207
+#define CLK_TOP_PWM_SEL			208
+#define CLK_TOP_AUDIO_H_SEL		209
+#define CLK_TOP_SPMI_MST_SEL		210
+#define CLK_TOP_DVFSRC_SEL		211
+#define CLK_TOP_AES_MSDCFDE_SEL		212
+#define CLK_TOP_MCUPM_SEL		213
+#define CLK_TOP_SFLASH_SEL		214
+#define CLK_TOP_APLL_I2S0_MCK_SEL	215
+#define CLK_TOP_APLL_I2S1_MCK_SEL	216
+#define CLK_TOP_APLL_I2S2_MCK_SEL	217
+#define CLK_TOP_APLL_I2S3_MCK_SEL	218
+#define CLK_TOP_APLL_I2S4_MCK_SEL	219
+#define CLK_TOP_APLL_I2S5_MCK_SEL	220
+#define CLK_TOP_APLL_I2S6_MCK_SEL	221
+#define CLK_TOP_APLL_I2S7_MCK_SEL	222
+#define CLK_TOP_APLL_I2S8_MCK_SEL	223
+#define CLK_TOP_APLL_I2S9_MCK_SEL	224
+#define CLK_TOP_APLL12_CK_DIV0		225
+#define CLK_TOP_APLL12_CK_DIV1		226
+#define CLK_TOP_APLL12_CK_DIV2		227
+#define CLK_TOP_APLL12_CK_DIV3		228
+#define CLK_TOP_APLL12_CK_DIV4		229
+#define CLK_TOP_APLL12_CK_DIVB		230
+#define CLK_TOP_APLL12_CK_DIV5		231
+#define CLK_TOP_APLL12_CK_DIV6		232
+#define CLK_TOP_APLL12_CK_DIV7		233
+#define CLK_TOP_APLL12_CK_DIV8		234
+#define CLK_TOP_APLL12_CK_DIV9		235
+#define CLK_TOP_NR_CLK			236
+
+/* INFRACFG_AO */
+
+#define CLK_IFRAO_INFRA_DCM_RG_FORCE		0
+#define CLK_IFRAO_PMIC_TMR			1
+#define CLK_IFRAO_PMIC_AP			2
+#define CLK_IFRAO_PMIC_MD			3
+#define CLK_IFRAO_PMIC_CONN			4
+#define CLK_IFRAO_SEJ				5
+#define CLK_IFRAO_APXGPT			6
+#define CLK_IFRAO_GCE				7
+#define CLK_IFRAO_GCE2				8
+#define CLK_IFRAO_THERM				9
+#define CLK_IFRAO_I2C0				10
+#define CLK_IFRAO_I2C1				11
+#define CLK_IFRAO_I2C2				12
+#define CLK_IFRAO_I2C3				13
+#define CLK_IFRAO_PWM_HCLK			14
+#define CLK_IFRAO_PWM1				15
+#define CLK_IFRAO_PWM2				16
+#define CLK_IFRAO_PWM3				17
+#define CLK_IFRAO_PWM4				18
+#define CLK_IFRAO_PWM				19
+#define CLK_IFRAO_UART0				20
+#define CLK_IFRAO_UART1				21
+#define CLK_IFRAO_UART2				22
+#define CLK_IFRAO_UART3				23
+#define CLK_IFRAO_GCE_26M			24
+#define CLK_IFRAO_CQ_DMA_FPC			25
+#define CLK_IFRAO_BTIF				26
+#define CLK_IFRAO_SPI0				27
+#define CLK_IFRAO_MSDC0				28
+#define CLK_IFRAO_MSDC1				29
+#define CLK_IFRAO_MSDC0_SRC			30
+#define CLK_IFRAO_DVFSRC			31
+#define CLK_IFRAO_TRNG				32
+#define CLK_IFRAO_AUXADC			33
+#define CLK_IFRAO_CPUM				34
+#define CLK_IFRAO_CCIF1_AP			35
+#define CLK_IFRAO_CCIF1_MD			36
+#define CLK_IFRAO_AUXADC_MD			37
+#define CLK_IFRAO_PCIE_TL_26M			38
+#define CLK_IFRAO_MSDC1_SRC			39
+#define CLK_IFRAO_MSDC0_AES			40
+#define CLK_IFRAO_PCIE_TL_96M			41
+#define CLK_IFRAO_PCIE_PL_PCLK_250M		42
+#define CLK_IFRAO_DEVICE_APC			43
+#define CLK_IFRAO_CCIF_AP			44
+#define CLK_IFRAO_DEBUGSYS			45
+#define CLK_IFRAO_AUDIO				46
+#define CLK_IFRAO_CCIF_MD			47
+#define CLK_IFRAO_DXCC_SEC_CORE			48
+#define CLK_IFRAO_DXCC_AO			49
+#define CLK_IFRAO_DBG_TRACE			50
+#define CLK_IFRAO_DRAMC_F26M			51
+#define CLK_IFRAO_SSUSB				52
+#define CLK_IFRAO_DISP_PWM			53
+#define CLK_IFRAO_CLDMA_BCLK			54
+#define CLK_IFRAO_AUDIO_26M_BCLK		55
+#define CLK_IFRAO_MODEM_TEMP_SHARE		56
+#define CLK_IFRAO_SPI1				57
+#define CLK_IFRAO_I2C4				58
+#define CLK_IFRAO_SPI2				59
+#define CLK_IFRAO_SPI3				60
+#define CLK_IFRAO_UNIPRO_SYSCLK			61
+#define CLK_IFRAO_UNIPRO_TICK			62
+#define CLK_IFRAO_UFS_MP_SAP_BCLK		63
+#define CLK_IFRAO_FSSPM				64
+#define CLK_IFRAO_SSPM_BUS_HCLK			65
+#define CLK_IFRAO_I2C5				66
+#define CLK_IFRAO_I2C5_ARBITER			67
+#define CLK_IFRAO_I2C5_IMM			68
+#define CLK_IFRAO_I2C1_ARBITER			69
+#define CLK_IFRAO_I2C1_IMM			70
+#define CLK_IFRAO_I2C2_ARBITER			71
+#define CLK_IFRAO_I2C2_IMM			72
+#define CLK_IFRAO_SPI4				73
+#define CLK_IFRAO_SPI5				74
+#define CLK_IFRAO_CQ_DMA			75
+#define CLK_IFRAO_UFS				76
+#define CLK_IFRAO_AES				77
+#define CLK_IFRAO_UFS_TICK			78
+#define CLK_IFRAO_SSUSB_XHCI			79
+#define CLK_IFRAO_MSDC0_SELF			80
+#define CLK_IFRAO_MSDC1_SELF			81
+#define CLK_IFRAO_MSDC2_SELF			82
+#define CLK_IFRAO_SSPM_26M_SELF			83
+#define CLK_IFRAO_SSPM_32K_SELF			84
+#define CLK_IFRAO_I2C6				85
+#define CLK_IFRAO_AP_MSDC0			86
+#define CLK_IFRAO_MD_MSDC0			87
+#define CLK_IFRAO_CCIF5_AP			88
+#define CLK_IFRAO_CCIF5_MD			89
+#define CLK_IFRAO_FLASHIF_TOP_HCLK_133M		90
+#define CLK_IFRAO_CCIF2_AP			91
+#define CLK_IFRAO_CCIF2_MD			92
+#define CLK_IFRAO_CCIF3_AP			93
+#define CLK_IFRAO_CCIF3_MD			94
+#define CLK_IFRAO_SEJ_F13M			95
+#define CLK_IFRAO_I2C7				96
+#define CLK_IFRAO_I2C8				97
+#define CLK_IFRAO_FBIST2FPC			98
+#define CLK_IFRAO_DEVICE_APC_SYNC		99
+#define CLK_IFRAO_DPMAIF_MAIN			100
+#define CLK_IFRAO_CCIF4_AP			101
+#define CLK_IFRAO_CCIF4_MD			102
+#define CLK_IFRAO_SPI6_CK			103
+#define CLK_IFRAO_SPI7_CK			104
+#define CLK_IFRAO_133M_MCLK_CK			105
+#define CLK_IFRAO_66M_MCLK_CK			106
+#define CLK_IFRAO_66M_PERI_BUS_MCLK_CK		107
+#define CLK_IFRAO_INFRA_FREE_DCM_133M		108
+#define CLK_IFRAO_INFRA_FREE_DCM_66M		109
+#define CLK_IFRAO_PERU_BUS_DCM_133M		110
+#define CLK_IFRAO_PERU_BUS_DCM_66M		111
+#define CLK_IFRAO_RG_FLASHIF_PERI_26M_CK	112
+#define CLK_IFRAO_RG_FLASHIF_SFLASH_CK		113
+#define CLK_IFRAO_AP_DMA			114
+#define CLK_IFRAO_PERI_DCM_RG_FORCE		115
+#define CLK_IFRAO_NR_CLK			116
+
+/* PERICFG */
+
+#define CLK_PERIAXI_DISABLE		0
+#define CLK_PERI_NR_CLK			1
+
+/* SCP */
+
+#define CLK_SCP_PAR_ADSP_PLL		0
+#define CLK_SCP_PAR_NR_CLK		1
+
+/* IMP_IIC_WRAP_C */
+
+#define CLK_IMPC_AP_CLOCK_RO_I2C10	0
+#define CLK_IMPC_AP_CLOCK_RO_I2C11	1
+#define CLK_IMPC_NR_CLK			2
+
+/* AUDIO */
+
+#define CLK_AUDSYS_AFE			0
+#define CLK_AUDSYS_22M			1
+#define CLK_AUDSYS_24M			2
+#define CLK_AUDSYS_APLL2_TUNER		3
+#define CLK_AUDSYS_APLL_TUNER		4
+#define CLK_AUDSYS_TDM			5
+#define CLK_AUDSYS_ADC			6
+#define CLK_AUDSYS_DAC			7
+#define CLK_AUDSYS_DAC_PREDIS		8
+#define CLK_AUDSYS_TML			9
+#define CLK_AUDSYS_NLE			10
+#define CLK_AUDSYS_I2S1_BCLK		11
+#define CLK_AUDSYS_I2S2_BCLK		12
+#define CLK_AUDSYS_I2S3_BCLK		13
+#define CLK_AUDSYS_I2S4_BCLK		14
+#define CLK_AUDSYS_CONNSYS_I2S_ASRC	15
+#define CLK_AUDSYS_GENERAL1_ASRC	16
+#define CLK_AUDSYS_GENERAL2_ASRC	17
+#define CLK_AUDSYS_DAC_HIRES		18
+#define CLK_AUDSYS_ADC_HIRES		19
+#define CLK_AUDSYS_ADC_HIRES_TML	20
+#define CLK_AUDSYS_ADDA6_ADC		21
+#define CLK_AUDSYS_ADDA6_ADC_HIRES	22
+#define CLK_AUDSYS_3RD_DAC		23
+#define CLK_AUDSYS_3RD_DAC_PREDIS	24
+#define CLK_AUDSYS_3RD_DAC_TML		25
+#define CLK_AUDSYS_3RD_DAC_HIRES	26
+#define CLK_AUDSYS_I2S5_BCLK		27
+#define CLK_AUDSYS_I2S6_BCLK		28
+#define CLK_AUDSYS_I2S7_BCLK		29
+#define CLK_AUDSYS_I2S8_BCLK		30
+#define CLK_AUDSYS_I2S9_BCLK		31
+#define CLK_AUDSYS_NR_CLK		32
+
+/* IMP_IIC_WRAP_E */
+
+#define CLK_IMPE_AP_CLOCK_RO_I2C3	0
+#define CLK_IMPE_NR_CLK			1
+
+/* IMP_IIC_WRAP_S */
+
+#define CLK_IMPS_AP_CLOCK_RO_I2C8	0
+#define CLK_IMPS_AP_CLOCK_RO_I2C9	1
+#define CLK_IMPS_NR_CLK			2
+
+/* IMP_IIC_WRAP_WS */
+
+#define CLK_IMPWS_AP_CLOCK_RO_I2C1	0
+#define CLK_IMPWS_AP_CLOCK_RO_I2C2	1
+#define CLK_IMPWS_AP_CLOCK_RO_I2C4	2
+#define CLK_IMPWS_NR_CLK		3
+
+/* IMP_IIC_WRAP_W */
+
+#define CLK_IMPW_AP_CLOCK_RO_I2C0	0
+#define CLK_IMPW_AP_CLOCK_RO_I2C5	1
+#define CLK_IMPW_AP_CLOCK_RO_I2C7	2
+#define CLK_IMPW_NR_CLK			3
+
+/* IMP_IIC_WRAP_N */
+
+#define CLK_IMPN_AP_CLOCK_RO_I2C6	0
+#define CLK_IMPN_NR_CLK			1
+
+/* MFGSYS */
+
+#define CLK_MFGCFG_BG3D			0
+#define CLK_MFGCFG_NR_CLK		1
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_DISP_MUTEX0		0
+#define CLK_MM_APB_BUS			1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_DISP_RDMA0		3
+#define CLK_MM_DISP_OVL0_2L		4
+#define CLK_MM_DISP_WDMA0		5
+#define CLK_MM_DISP_CCORR1		6
+#define CLK_MM_DISP_RSZ0		7
+#define CLK_MM_DISP_AAL0		8
+#define CLK_MM_DISP_CCORR0		9
+#define CLK_MM_DISP_COLOR0		10
+#define CLK_MM_SMI_INFRA		11
+#define CLK_MM_DISP_DSC_WRAP		12
+#define CLK_MM_DISP_GAMMA0		13
+#define CLK_MM_DISP_POSTMASK0		14
+#define CLK_MM_DISP_SPR0		15
+#define CLK_MM_DISP_DITHER0		16
+#define CLK_MM_SMI_COMMON		17
+#define CLK_MM_DISP_CM0			18
+#define CLK_MM_DSI0			19
+#define CLK_MM_DISP_FAKE_ENG0		20
+#define CLK_MM_DISP_FAKE_ENG1		21
+#define CLK_MM_SMI_GALS			22
+#define CLK_MM_SMI_IOMMU		23
+#define CLK_MM_DSI0_DSI_CK_DOMAIN	24
+#define CLK_MM_DISP_26M			25
+#define CLK_MM_NR_CLK			26
+
+/* IMGSYS1 */
+
+#define CLK_IMGSYS1_LARB9		0
+#define CLK_IMGSYS1_LARB10		1
+#define CLK_IMGSYS1_DIP			2
+#define CLK_IMGSYS1_GALS		3
+#define CLK_IMGSYS1_NR_CLK		4
+
+/* IMGSYS2 */
+
+#define CLK_IMGSYS2_LARB9		0
+#define CLK_IMGSYS2_LARB10		1
+#define CLK_IMGSYS2_MFB			2
+#define CLK_IMGSYS2_WPE			3
+#define CLK_IMGSYS2_MSS			4
+#define CLK_IMGSYS2_GALS		5
+#define CLK_IMGSYS2_NR_CLK		6
+
+/* VDEC_GCON */
+
+#define CLK_VDEC_LARB1_CKEN		0
+#define CLK_VDEC_CKEN			1
+#define CLK_VDEC_ACTIVE			2
+#define CLK_VDEC_NR_CLK			3
+
+/* VENC_GCON */
+
+#define CLK_VENC_SET0_LARB		0
+#define CLK_VENC_SET1_VENC		1
+#define CLK_VENC_SET2_JPGENC		2
+#define CLK_VENC_SET5_GALS		3
+#define CLK_VENC_NR_CLK			4
+
+/* APU_CONN */
+
+#define CLK_APUC_APU			0
+#define CLK_APUC_AHB			1
+#define CLK_APUC_AXI			2
+#define CLK_APUC_ISP			3
+#define CLK_APUC_CAM_ADL		4
+#define CLK_APUC_IMG_ADL		5
+#define CLK_APUC_EMI_26M		6
+#define CLK_APUC_VPU_UDI		7
+#define CLK_APUC_EDMA_0			8
+#define CLK_APUC_EDMA_1			9
+#define CLK_APUC_EDMAL_0		10
+#define CLK_APUC_EDMAL_1		11
+#define CLK_APUC_MNOC			12
+#define CLK_APUC_TCM			13
+#define CLK_APUC_MD32			14
+#define CLK_APUC_IOMMU_0		15
+#define CLK_APUC_MD32_32K		16
+#define CLK_APUC_NR_CLK			17
+
+/* APU_VCORE */
+
+#define CLK_APUV_AHB			0
+#define CLK_APUV_AXI			1
+#define CLK_APUV_ADL			2
+#define CLK_APUV_QOS			3
+#define CLK_APUV_NR_CLK			4
+
+/* APU0 */
+
+#define CLK_APU0_APU			0
+#define CLK_APU0_AXI_M			1
+#define CLK_APU0_JTAG			2
+#define CLK_APU0_PCLK			3
+#define CLK_APU0_NR_CLK			4
+
+/* APU1 */
+
+#define CLK_APU1_APU			0
+#define CLK_APU1_AXI_M			1
+#define CLK_APU1_JTAG			2
+#define CLK_APU1_PCLK			3
+#define CLK_APU1_NR_CLK			4
+
+/* CAMSYS_MAIN */
+
+#define CLK_CAM_M_LARB13		0
+#define CLK_CAM_M_LARB14		1
+#define CLK_CAM_M_RESERVED0		2
+#define CLK_CAM_M_CAM			3
+#define CLK_CAM_M_CAMTG			4
+#define CLK_CAM_M_SENINF		5
+#define CLK_CAM_M_CAMSV1		6
+#define CLK_CAM_M_CAMSV2		7
+#define CLK_CAM_M_CAMSV3		8
+#define CLK_CAM_M_CCU0			9
+#define CLK_CAM_M_CCU1			10
+#define CLK_CAM_M_MRAW0			11
+#define CLK_CAM_M_RESERVED2		12
+#define CLK_CAM_M_FAKE_ENG		13
+#define CLK_CAM_M_CCU_GALS		14
+#define CLK_CAM_M_CAM2MM_GALS		15
+#define CLK_CAM_M_NR_CLK		16
+
+/* CAMSYS_RAWA */
+
+#define CLK_CAM_RA_LARBX		0
+#define CLK_CAM_RA_CAM			1
+#define CLK_CAM_RA_CAMTG		2
+#define CLK_CAM_RA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+
+#define CLK_CAM_RB_LARBX		0
+#define CLK_CAM_RB_CAM			1
+#define CLK_CAM_RB_CAMTG		2
+#define CLK_CAM_RB_NR_CLK		3
+
+/* IPESYS */
+
+#define CLK_IPE_LARB19			0
+#define CLK_IPE_LARB20			1
+#define CLK_IPE_SMI_SUBCOM		2
+#define CLK_IPE_FD			3
+#define CLK_IPE_FE			4
+#define CLK_IPE_RSC			5
+#define CLK_IPE_DPE			6
+#define CLK_IPE_GALS			7
+#define CLK_IPE_NR_CLK			8
+
+/* MDPSYS_CONFIG */
+
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_TDSHP0			1
+#define CLK_MDP_IMG_DL_ASYNC0		2
+#define CLK_MDP_IMG_DL_ASYNC1		3
+#define CLK_MDP_RDMA1			4
+#define CLK_MDP_TDSHP1			5
+#define CLK_MDP_SMI0			6
+#define CLK_MDP_APB_BUS			7
+#define CLK_MDP_WROT0			8
+#define CLK_MDP_RSZ0			9
+#define CLK_MDP_HDR0			10
+#define CLK_MDP_MUTEX0			11
+#define CLK_MDP_WROT1			12
+#define CLK_MDP_RSZ1			13
+#define CLK_MDP_FAKE_ENG0		14
+#define CLK_MDP_AAL0			15
+#define CLK_MDP_AAL1			16
+#define CLK_MDP_COLOR0			17
+#define CLK_MDP_IMG_DL_RELAY0_ASYNC0	18
+#define CLK_MDP_IMG_DL_RELAY1_ASYNC1	19
+#define CLK_MDP_NR_CLK			20
+
+/* SCP_SYS */
+#define SCP_SYS_MD1	0
+#define SCP_SYS_CONN	1
+#define SCP_SYS_MFG0	2
+#define SCP_SYS_MFG1	3
+#define SCP_SYS_MFG2	4
+#define SCP_SYS_MFG3	5
+#define SCP_SYS_ISP	6
+#define SCP_SYS_ISP2	7
+#define SCP_SYS_IPE	8
+#define SCP_SYS_VDEC	9
+#define SCP_SYS_VENC	10
+#define SCP_SYS_DIS	11
+#define SCP_SYS_AUDIO	12
+#define SCP_SYS_CAM	13
+#define SCP_SYS_CAM_RAWA	14
+#define SCP_SYS_CAM_RAWB	15
+#define SCP_NR_SYSS	16
+
+#endif /* _DT_BINDINGS_CLK_MT6833_H */
+

include/dt-bindings/clock/mt6853-clk.h

@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MT6853_H
+#define _DT_BINDINGS_CLK_MT6853_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL_LL		0
+#define CLK_APMIXED_ARMPLL_BL0		1
+#define CLK_APMIXED_CCIPLL		2
+#define CLK_APMIXED_MPLL		3
+#define CLK_APMIXED_MAINPLL		4
+#define CLK_APMIXED_UNIVPLL		5
+#define CLK_APMIXED_MSDCPLL		6
+#define CLK_APMIXED_MMPLL		7
+#define CLK_APMIXED_ADSPPLL		8
+#define CLK_APMIXED_MFGPLL		9
+#define CLK_APMIXED_TVDPLL		10
+#define CLK_APMIXED_APLL1		11
+#define CLK_APMIXED_APLL2		12
+#define CLK_APMIXED_NPUPLL		13
+#define CLK_APMIXED_USBPLL		14
+#define CLK_APMIXED_PLL_MIPIC0_26M_EN	15
+#define CLK_APMIXED_PLL_MIPIC1_26M_EN	16
+#define CLK_APMIXED_PLL_MIPID0_26M_EN	17
+#define CLK_APMIXED_NR_CLK		18
+
+/* TOPCKGEN */
+
+#define CLK_TOP_MAINPLL			0
+#define CLK_TOP_MAINPLL_D3		1
+#define CLK_TOP_MAINPLL_D4		2
+#define CLK_TOP_MAINPLL_D4_D2		3
+#define CLK_TOP_MAINPLL_D4_D4		4
+#define CLK_TOP_MAINPLL_D4_D8		5
+#define CLK_TOP_MAINPLL_D4_D16		6
+#define CLK_TOP_MAINPLL_D5		7
+#define CLK_TOP_MAINPLL_D5_D2		8
+#define CLK_TOP_MAINPLL_D5_D4		9
+#define CLK_TOP_MAINPLL_D5_D8		10
+#define CLK_TOP_MAINPLL_D6		11
+#define CLK_TOP_MAINPLL_D6_D2		12
+#define CLK_TOP_MAINPLL_D6_D4		13
+#define CLK_TOP_MAINPLL_D6_D8		14
+#define CLK_TOP_MAINPLL_D7		15
+#define CLK_TOP_MAINPLL_D7_D2		16
+#define CLK_TOP_MAINPLL_D7_D4		17
+#define CLK_TOP_MAINPLL_D7_D8		18
+#define CLK_TOP_MAINPLL_D9		19
+#define CLK_TOP_UNIVPLL_192M		20
+#define CLK_TOP_UNIVPLL_192M_D2		21
+#define CLK_TOP_UNIVPLL_192M_D4		22
+#define CLK_TOP_UNIVPLL_192M_D8		23
+#define CLK_TOP_UNIVPLL_192M_D16	24
+#define CLK_TOP_UNIVPLL_192M_D32	25
+#define CLK_TOP_UNIVPLL			26
+#define CLK_TOP_UNIVPLL_D2		27
+#define CLK_TOP_UNIVPLL_D3		28
+#define CLK_TOP_UNIVPLL_D4		29
+#define CLK_TOP_UNIVPLL_D4_D2		30
+#define CLK_TOP_UNIVPLL_D4_D4		31
+#define CLK_TOP_UNIVPLL_D4_D8		32
+#define CLK_TOP_UNIVPLL_D5		33
+#define CLK_TOP_UNIVPLL_D5_D2		34
+#define CLK_TOP_UNIVPLL_D5_D4		35
+#define CLK_TOP_UNIVPLL_D5_D8		36
+#define CLK_TOP_UNIVPLL_D5_D16		37
+#define CLK_TOP_UNIVPLL_D6		38
+#define CLK_TOP_UNIVPLL_D6_D2		39
+#define CLK_TOP_UNIVPLL_D6_D4		40
+#define CLK_TOP_UNIVPLL_D6_D8		41
+#define CLK_TOP_UNIVPLL_D6_D16		42
+#define CLK_TOP_UNIVPLL_D7		43
+#define CLK_TOP_UNIVPLL_D7_D2		44
+#define CLK_TOP_MFGPLL			45
+#define CLK_TOP_APLL1			46
+#define CLK_TOP_APLL1_D2		47
+#define CLK_TOP_APLL1_D4		48
+#define CLK_TOP_APLL1_D8		49
+#define CLK_TOP_APLL2			50
+#define CLK_TOP_APLL2_D2		51
+#define CLK_TOP_APLL2_D4		52
+#define CLK_TOP_APLL2_D8		53
+#define CLK_TOP_ADSPPLL			54
+#define CLK_TOP_MMPLL_D3		55
+#define CLK_TOP_MMPLL_D4		56
+#define CLK_TOP_MMPLL_D4_D2		57
+#define CLK_TOP_MMPLL_D4_D4		58
+#define CLK_TOP_MMPLL_D5		59
+#define CLK_TOP_MMPLL_D5_D2		60
+#define CLK_TOP_MMPLL_D5_D4		61
+#define CLK_TOP_MMPLL_D6		62
+#define CLK_TOP_MMPLL_D6_D2		63
+#define CLK_TOP_MMPLL_D7		64
+#define CLK_TOP_MMPLL_D9		65
+#define CLK_TOP_NPUPLL			66
+#define CLK_TOP_TVDPLL			67
+#define CLK_TOP_TVDPLL_D2		68
+#define CLK_TOP_TVDPLL_D4		69
+#define CLK_TOP_TVDPLL_D8		70
+#define CLK_TOP_TVDPLL_D16		71
+#define CLK_TOP_MSDCPLL			72
+#define CLK_TOP_MSDCPLL_D2		73
+#define CLK_TOP_MSDCPLL_D4		74
+#define CLK_TOP_MSDCPLL_D8		75
+#define CLK_TOP_MSDCPLL_D16		76
+#define CLK_TOP_OSC			77
+#define CLK_TOP_OSC_D2			78
+#define CLK_TOP_OSC_D4			79
+#define CLK_TOP_OSC_D8			80
+#define CLK_TOP_OSC_D16			81
+#define CLK_TOP_OSC_D10			82
+#define CLK_TOP_OSC_D20			83
+#define CLK_TOP_OSC_CK_2		84
+#define CLK_TOP_OSC2_D2			85
+#define CLK_TOP_TCK_26M_MX9		86
+#define CLK_TOP_CSW_F26M_CK_D2		87
+#define CLK_TOP_F26M			88
+#define CLK_TOP_FRTC			89
+#define CLK_TOP_AXI			90
+#define CLK_TOP_SPM			91
+#define CLK_TOP_SCP			92
+#define CLK_TOP_BUS			93
+#define CLK_TOP_DISP			94
+#define CLK_TOP_MDP			95
+#define CLK_TOP_IMG1			96
+#define CLK_TOP_IMG2			97
+#define CLK_TOP_IPE			98
+#define CLK_TOP_DPE			99
+#define CLK_TOP_CAM			100
+#define CLK_TOP_CCU			101
+#define CLK_TOP_DSP			102
+#define CLK_TOP_DSP1			103
+#define CLK_TOP_DSP2			104
+#define CLK_TOP_IPU_IF			105
+#define CLK_TOP_MFG_REF			106
+#define CLK_TOP_FCAMTG			107
+#define CLK_TOP_FCAMTG2			108
+#define CLK_TOP_FCAMTG3			109
+#define CLK_TOP_FCAMTG4			110
+#define CLK_TOP_FCAMTG5			111
+#define CLK_TOP_FUART			112
+#define CLK_TOP_SPI			113
+#define CLK_TOP_MSDC50_0_HCLK		114
+#define CLK_TOP_MSDC50_0		115
+#define CLK_TOP_MSDC30_1		116
+#define CLK_TOP_AUDIO			117
+#define CLK_TOP_AUD_INTBUS		118
+#define CLK_TOP_FPWRAP_ULPOSC		119
+#define CLK_TOP_ATB			120
+#define CLK_TOP_SSPM			121
+#define CLK_TOP_SCAM			122
+#define CLK_TOP_FDISP_PWM		123
+#define CLK_TOP_FUSB_TOP		124
+#define CLK_TOP_FSSUSB_XHCI		125
+#define CLK_TOP_I2C			126
+#define CLK_TOP_FSENINF			127
+#define CLK_TOP_FSENINF1		128
+#define CLK_TOP_FSENINF2		129
+#define CLK_TOP_DXCC			130
+#define CLK_TOP_AUD_ENGEN1		131
+#define CLK_TOP_AUD_ENGEN2		132
+#define CLK_TOP_AES_UFSFDE		133
+#define CLK_TOP_UFS			134
+#define CLK_TOP_AUD_1			135
+#define CLK_TOP_AUD_2			136
+#define CLK_TOP_ADSP			137
+#define CLK_TOP_DPMAIF_MAIN		138
+#define CLK_TOP_VENC			139
+#define CLK_TOP_VDEC			140
+#define CLK_TOP_CAMTM			141
+#define CLK_TOP_PWM			142
+#define CLK_TOP_AUDIO_H			143
+#define CLK_TOP_SPMI_MST		144
+#define CLK_TOP_DVFSRC			145
+#define CLK_TOP_AES_MSDCFDE		146
+#define CLK_TOP_MCUPM			147
+#define CLK_TOP_SFLASH			148
+#define CLK_TOP_DSI_OCC			149
+#define CLK_TOP_UNIPLL_SES		150
+#define CLK_TOP_I2C_PSEUDO		151
+#define CLK_TOP_APDMA_PSEUDO		152
+#define CLK_TOP_AXI_SEL			153
+#define CLK_TOP_SPM_SEL			154
+#define CLK_TOP_SCP_SEL			155
+#define CLK_TOP_BUS_AXIMEM_SEL		156
+#define CLK_TOP_DISP_SEL		157
+#define CLK_TOP_MDP_SEL			158
+#define CLK_TOP_IMG1_SEL		159
+#define CLK_TOP_IMG2_SEL		160
+#define CLK_TOP_IPE_SEL			161
+#define CLK_TOP_DPE_SEL			162
+#define CLK_TOP_CAM_SEL			163
+#define CLK_TOP_CCU_SEL			164
+#define CLK_TOP_DSP_SEL			165
+#define CLK_TOP_DSP1_SEL		166
+#define CLK_TOP_DSP1_NPUPLL_SEL		167
+#define CLK_TOP_DSP2_SEL		168
+#define CLK_TOP_DSP2_NPUPLL_SEL		169
+#define CLK_TOP_IPU_IF_SEL		170
+#define CLK_TOP_MFG_REF_SEL		171
+#define CLK_TOP_MFG_PLL_SEL		172
+#define CLK_TOP_CAMTG_SEL		173
+#define CLK_TOP_CAMTG2_SEL		174
+#define CLK_TOP_CAMTG3_SEL		175
+#define CLK_TOP_CAMTG4_SEL		176
+#define CLK_TOP_CAMTG5_SEL		177
+#define CLK_TOP_UART_SEL		178
+#define CLK_TOP_SPI_SEL			179
+#define CLK_TOP_MSDC50_0_HCLK_SEL	180
+#define CLK_TOP_MSDC50_0_SEL		181
+#define CLK_TOP_MSDC30_1_SEL		182
+#define CLK_TOP_AUDIO_SEL		183
+#define CLK_TOP_AUD_INTBUS_SEL		184
+#define CLK_TOP_PWRAP_ULPOSC_SEL	185
+#define CLK_TOP_ATB_SEL			186
+#define CLK_TOP_SSPM_SEL		187
+#define CLK_TOP_SCAM_SEL		188
+#define CLK_TOP_DISP_PWM_SEL		189
+#define CLK_TOP_USB_TOP_SEL		190
+#define CLK_TOP_SSUSB_XHCI_SEL		191
+#define CLK_TOP_I2C_SEL			192
+#define CLK_TOP_SENINF_SEL		193
+#define CLK_TOP_SENINF1_SEL		194
+#define CLK_TOP_SENINF2_SEL		195
+#define CLK_TOP_DXCC_SEL		196
+#define CLK_TOP_AUD_ENGEN1_SEL		197
+#define CLK_TOP_AUD_ENGEN2_SEL		198
+#define CLK_TOP_AES_UFSFDE_SEL		199
+#define CLK_TOP_UFS_SEL			200
+#define CLK_TOP_AUD_1_SEL		201
+#define CLK_TOP_AUD_2_SEL		202
+#define CLK_TOP_ADSP_SEL		203
+#define CLK_TOP_DPMAIF_MAIN_SEL		204
+#define CLK_TOP_VENC_SEL		205
+#define CLK_TOP_VDEC_SEL		206
+#define CLK_TOP_CAMTM_SEL		207
+#define CLK_TOP_PWM_SEL			208
+#define CLK_TOP_AUDIO_H_SEL		209
+#define CLK_TOP_SPMI_MST_SEL		210
+#define CLK_TOP_DVFSRC_SEL		211
+#define CLK_TOP_AES_MSDCFDE_SEL		212
+#define CLK_TOP_MCUPM_SEL		213
+#define CLK_TOP_SFLASH_SEL		214
+#define CLK_TOP_APLL_I2S0_MCK_SEL	215
+#define CLK_TOP_APLL_I2S1_MCK_SEL	216
+#define CLK_TOP_APLL_I2S2_MCK_SEL	217
+#define CLK_TOP_APLL_I2S3_MCK_SEL	218
+#define CLK_TOP_APLL_I2S4_MCK_SEL	219
+#define CLK_TOP_APLL_I2S5_MCK_SEL	220
+#define CLK_TOP_APLL_I2S6_MCK_SEL	221
+#define CLK_TOP_APLL_I2S7_MCK_SEL	222
+#define CLK_TOP_APLL_I2S8_MCK_SEL	223
+#define CLK_TOP_APLL_I2S9_MCK_SEL	224
+#define CLK_TOP_APLL12_CK_DIV0		225
+#define CLK_TOP_APLL12_CK_DIV1		226
+#define CLK_TOP_APLL12_CK_DIV2		227
+#define CLK_TOP_APLL12_CK_DIV3		228
+#define CLK_TOP_APLL12_CK_DIV4		229
+#define CLK_TOP_APLL12_CK_DIVB		230
+#define CLK_TOP_APLL12_CK_DIV5		231
+#define CLK_TOP_APLL12_CK_DIV6		232
+#define CLK_TOP_APLL12_CK_DIV7		233
+#define CLK_TOP_APLL12_CK_DIV8		234
+#define CLK_TOP_APLL12_CK_DIV9		235
+#define CLK_TOP_NR_CLK			236
+
+/* INFRACFG_AO */
+
+#define CLK_IFRAO_INFRA_DCM_RG_FORCE		0
+#define CLK_IFRAO_PMIC_TMR			1
+#define CLK_IFRAO_PMIC_AP			2
+#define CLK_IFRAO_PMIC_MD			3
+#define CLK_IFRAO_PMIC_CONN			4
+#define CLK_IFRAO_SEJ				5
+#define CLK_IFRAO_APXGPT			6
+#define CLK_IFRAO_GCE				7
+#define CLK_IFRAO_GCE2				8
+#define CLK_IFRAO_THERM				9
+#define CLK_IFRAO_I2C0				10
+#define CLK_IFRAO_I2C1				11
+#define CLK_IFRAO_I2C2				12
+#define CLK_IFRAO_I2C3				13
+#define CLK_IFRAO_PWM_HCLK			14
+#define CLK_IFRAO_PWM1				15
+#define CLK_IFRAO_PWM2				16
+#define CLK_IFRAO_PWM3				17
+#define CLK_IFRAO_PWM4				18
+#define CLK_IFRAO_PWM				19
+#define CLK_IFRAO_UART0				20
+#define CLK_IFRAO_UART1				21
+#define CLK_IFRAO_UART2				22
+#define CLK_IFRAO_UART3				23
+#define CLK_IFRAO_GCE_26M			24
+#define CLK_IFRAO_CQ_DMA_FPC			25
+#define CLK_IFRAO_BTIF				26
+#define CLK_IFRAO_SPI0				27
+#define CLK_IFRAO_MSDC0				28
+#define CLK_IFRAO_MSDC1				29
+#define CLK_IFRAO_MSDC0_SRC			30
+#define CLK_IFRAO_DVFSRC			31
+#define CLK_IFRAO_TRNG				32
+#define CLK_IFRAO_AUXADC			33
+#define CLK_IFRAO_CPUM				34
+#define CLK_IFRAO_CCIF1_AP			35
+#define CLK_IFRAO_CCIF1_MD			36
+#define CLK_IFRAO_AUXADC_MD			37
+#define CLK_IFRAO_PCIE_TL_26M			38
+#define CLK_IFRAO_MSDC1_SRC			39
+#define CLK_IFRAO_MSDC0_AES			40
+#define CLK_IFRAO_PCIE_TL_96M			41
+#define CLK_IFRAO_PCIE_PL_PCLK_250M		42
+#define CLK_IFRAO_DEVICE_APC			43
+#define CLK_IFRAO_CCIF_AP			44
+#define CLK_IFRAO_DEBUGSYS			45
+#define CLK_IFRAO_AUDIO				46
+#define CLK_IFRAO_CCIF_MD			47
+#define CLK_IFRAO_DXCC_SEC_CORE			48
+#define CLK_IFRAO_DXCC_AO			49
+#define CLK_IFRAO_DBG_TRACE			50
+#define CLK_IFRAO_DRAMC_F26M			51
+#define CLK_IFRAO_SSUSB				52
+#define CLK_IFRAO_DISP_PWM			53
+#define CLK_IFRAO_CLDMA_BCLK			54
+#define CLK_IFRAO_AUDIO_26M_BCLK		55
+#define CLK_IFRAO_MODEM_TEMP_SHARE		56
+#define CLK_IFRAO_SPI1				57
+#define CLK_IFRAO_I2C4				58
+#define CLK_IFRAO_SPI2				59
+#define CLK_IFRAO_SPI3				60
+#define CLK_IFRAO_UNIPRO_SYSCLK			61
+#define CLK_IFRAO_UNIPRO_TICK			62
+#define CLK_IFRAO_UFS_MP_SAP_BCLK		63
+#define CLK_IFRAO_FSSPM				64
+#define CLK_IFRAO_SSPM_BUS_HCLK			65
+#define CLK_IFRAO_I2C5				66
+#define CLK_IFRAO_I2C5_ARBITER			67
+#define CLK_IFRAO_I2C5_IMM			68
+#define CLK_IFRAO_I2C1_ARBITER			69
+#define CLK_IFRAO_I2C1_IMM			70
+#define CLK_IFRAO_I2C2_ARBITER			71
+#define CLK_IFRAO_I2C2_IMM			72
+#define CLK_IFRAO_SPI4				73
+#define CLK_IFRAO_SPI5				74
+#define CLK_IFRAO_CQ_DMA			75
+#define CLK_IFRAO_UFS				76
+#define CLK_IFRAO_AES				77
+#define CLK_IFRAO_UFS_TICK			78
+#define CLK_IFRAO_SSUSB_XHCI			79
+#define CLK_IFRAO_MSDC0_SELF			80
+#define CLK_IFRAO_MSDC1_SELF			81
+#define CLK_IFRAO_MSDC2_SELF			82
+#define CLK_IFRAO_SSPM_26M_SELF			83
+#define CLK_IFRAO_SSPM_32K_SELF			84
+#define CLK_IFRAO_I2C6				85
+#define CLK_IFRAO_AP_MSDC0			86
+#define CLK_IFRAO_MD_MSDC0			87
+#define CLK_IFRAO_CCIF5_AP			88
+#define CLK_IFRAO_CCIF5_MD			89
+#define CLK_IFRAO_FLASHIF_TOP_HCLK_133M		90
+#define CLK_IFRAO_CCIF2_AP			91
+#define CLK_IFRAO_CCIF2_MD			92
+#define CLK_IFRAO_CCIF3_AP			93
+#define CLK_IFRAO_CCIF3_MD			94
+#define CLK_IFRAO_SEJ_F13M			95
+#define CLK_IFRAO_I2C7				96
+#define CLK_IFRAO_I2C8				97
+#define CLK_IFRAO_FBIST2FPC			98
+#define CLK_IFRAO_DEVICE_APC_SYNC		99
+#define CLK_IFRAO_DPMAIF_MAIN			100
+#define CLK_IFRAO_CCIF4_AP			101
+#define CLK_IFRAO_CCIF4_MD			102
+#define CLK_IFRAO_SPI6_CK			103
+#define CLK_IFRAO_SPI7_CK			104
+#define CLK_IFRAO_133M_MCLK_CK			105
+#define CLK_IFRAO_66M_MCLK_CK			106
+#define CLK_IFRAO_66M_PERI_BUS_MCLK_CK		107
+#define CLK_IFRAO_INFRA_FREE_DCM_133M		108
+#define CLK_IFRAO_INFRA_FREE_DCM_66M		109
+#define CLK_IFRAO_PERU_BUS_DCM_133M		110
+#define CLK_IFRAO_PERU_BUS_DCM_66M		111
+#define CLK_IFRAO_RG_FLASHIF_PERI_26M_CK	112
+#define CLK_IFRAO_RG_FLASHIF_SFLASH_CK		113
+#define CLK_IFRAO_AP_DMA			114
+#define CLK_IFRAO_PERI_DCM_RG_FORCE		115
+#define CLK_IFRAO_NR_CLK			116
+
+/* PERICFG */
+
+#define CLK_PERIAXI_DISABLE		0
+#define CLK_PERI_NR_CLK			1
+
+/* SCP */
+
+#define CLK_SCP_PAR_ADSP_PLL		0
+#define CLK_SCP_PAR_NR_CLK		1
+
+/* IMP_IIC_WRAP_C */
+
+#define CLK_IMPC_AP_CLOCK_RO_I2C10	0
+#define CLK_IMPC_AP_CLOCK_RO_I2C11	1
+#define CLK_IMPC_NR_CLK			2
+
+/* AUDIO */
+
+#define CLK_AUDSYS_AFE			0
+#define CLK_AUDSYS_22M			1
+#define CLK_AUDSYS_24M			2
+#define CLK_AUDSYS_APLL2_TUNER		3
+#define CLK_AUDSYS_APLL_TUNER		4
+#define CLK_AUDSYS_TDM			5
+#define CLK_AUDSYS_ADC			6
+#define CLK_AUDSYS_DAC			7
+#define CLK_AUDSYS_DAC_PREDIS		8
+#define CLK_AUDSYS_TML			9
+#define CLK_AUDSYS_NLE			10
+#define CLK_AUDSYS_I2S1_BCLK		11
+#define CLK_AUDSYS_I2S2_BCLK		12
+#define CLK_AUDSYS_I2S3_BCLK		13
+#define CLK_AUDSYS_I2S4_BCLK		14
+#define CLK_AUDSYS_CONNSYS_I2S_ASRC	15
+#define CLK_AUDSYS_GENERAL1_ASRC	16
+#define CLK_AUDSYS_GENERAL2_ASRC	17
+#define CLK_AUDSYS_DAC_HIRES		18
+#define CLK_AUDSYS_ADC_HIRES		19
+#define CLK_AUDSYS_ADC_HIRES_TML	20
+#define CLK_AUDSYS_ADDA6_ADC		21
+#define CLK_AUDSYS_ADDA6_ADC_HIRES	22
+#define CLK_AUDSYS_3RD_DAC		23
+#define CLK_AUDSYS_3RD_DAC_PREDIS	24
+#define CLK_AUDSYS_3RD_DAC_TML		25
+#define CLK_AUDSYS_3RD_DAC_HIRES	26
+#define CLK_AUDSYS_I2S5_BCLK		27
+#define CLK_AUDSYS_I2S6_BCLK		28
+#define CLK_AUDSYS_I2S7_BCLK		29
+#define CLK_AUDSYS_I2S8_BCLK		30
+#define CLK_AUDSYS_I2S9_BCLK		31
+#define CLK_AUDSYS_NR_CLK		32
+
+/* IMP_IIC_WRAP_E */
+
+#define CLK_IMPE_AP_CLOCK_RO_I2C3	0
+#define CLK_IMPE_NR_CLK			1
+
+/* IMP_IIC_WRAP_S */
+
+#define CLK_IMPS_AP_CLOCK_RO_I2C5	0
+#define CLK_IMPS_AP_CLOCK_RO_I2C7	1
+#define CLK_IMPS_AP_CLOCK_RO_I2C8	2
+#define CLK_IMPS_AP_CLOCK_RO_I2C9	3
+#define CLK_IMPS_NR_CLK			4
+
+/* IMP_IIC_WRAP_WS */
+
+#define CLK_IMPWS_AP_CLOCK_RO_I2C1	0
+#define CLK_IMPWS_AP_CLOCK_RO_I2C2	1
+#define CLK_IMPWS_AP_CLOCK_RO_I2C4	2
+#define CLK_IMPWS_NR_CLK		3
+
+/* IMP_IIC_WRAP_W */
+
+#define CLK_IMPW_AP_CLOCK_RO_I2C0	0
+#define CLK_IMPW_NR_CLK			1
+
+/* IMP_IIC_WRAP_N */
+
+#define CLK_IMPN_AP_CLOCK_RO_I2C6	0
+#define CLK_IMPN_NR_CLK			1
+
+/* MFGSYS */
+
+#define CLK_MFGCFG_BG3D			0
+#define CLK_MFGCFG_NR_CLK		1
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_DISP_MUTEX0		0
+#define CLK_MM_APB_BUS			1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_DISP_RDMA0		3
+#define CLK_MM_DISP_OVL0_2L		4
+#define CLK_MM_DISP_WDMA0		5
+#define CLK_MM_DISP_CCORR1		6
+#define CLK_MM_DISP_RSZ0		7
+#define CLK_MM_DISP_AAL0		8
+#define CLK_MM_DISP_CCORR0		9
+#define CLK_MM_DISP_COLOR0		10
+#define CLK_MM_SMI_INFRA		11
+#define CLK_MM_DISP_DSC_WRAP		12
+#define CLK_MM_DISP_GAMMA0		13
+#define CLK_MM_DISP_POSTMASK0		14
+#define CLK_MM_DISP_SPR0		15
+#define CLK_MM_DISP_DITHER0		16
+#define CLK_MM_SMI_COMMON		17
+#define CLK_MM_DISP_CM0			18
+#define CLK_MM_DSI0			19
+#define CLK_MM_DISP_FAKE_ENG0		20
+#define CLK_MM_DISP_FAKE_ENG1		21
+#define CLK_MM_SMI_GALS			22
+#define CLK_MM_SMI_IOMMU		23
+#define CLK_MM_DSI0_DSI_CK_DOMAIN	24
+#define CLK_MM_DISP_26M			25
+#define CLK_MM_NR_CLK			26
+
+/* IMGSYS1 */
+
+#define CLK_IMGSYS1_LARB9		0
+#define CLK_IMGSYS1_LARB10		1
+#define CLK_IMGSYS1_DIP			2
+#define CLK_IMGSYS1_GALS		3
+#define CLK_IMGSYS1_NR_CLK		4
+
+/* IMGSYS2 */
+
+#define CLK_IMGSYS2_LARB9		0
+#define CLK_IMGSYS2_LARB10		1
+#define CLK_IMGSYS2_MFB			2
+#define CLK_IMGSYS2_WPE			3
+#define CLK_IMGSYS2_MSS			4
+#define CLK_IMGSYS2_GALS		5
+#define CLK_IMGSYS2_NR_CLK		6
+
+/* VDEC_GCON */
+
+#define CLK_VDEC_LARB1_CKEN		0
+#define CLK_VDEC_CKEN			1
+#define CLK_VDEC_ACTIVE			2
+#define CLK_VDEC_NR_CLK			3
+
+/* VENC_GCON */
+
+#define CLK_VENC_SET0_LARB		0
+#define CLK_VENC_SET1_VENC		1
+#define CLK_VENC_SET2_JPGENC		2
+#define CLK_VENC_SET5_GALS		3
+#define CLK_VENC_NR_CLK			4
+
+/* APU_CONN */
+
+#define CLK_APUC_APU			0
+#define CLK_APUC_AHB			1
+#define CLK_APUC_AXI			2
+#define CLK_APUC_ISP			3
+#define CLK_APUC_CAM_ADL		4
+#define CLK_APUC_IMG_ADL		5
+#define CLK_APUC_EMI_26M		6
+#define CLK_APUC_VPU_UDI		7
+#define CLK_APUC_EDMA_0			8
+#define CLK_APUC_EDMA_1			9
+#define CLK_APUC_EDMAL_0		10
+#define CLK_APUC_EDMAL_1		11
+#define CLK_APUC_MNOC			12
+#define CLK_APUC_TCM			13
+#define CLK_APUC_MD32			14
+#define CLK_APUC_IOMMU_0		15
+#define CLK_APUC_MD32_32K		16
+#define CLK_APUC_NR_CLK			17
+
+/* APU_VCORE */
+
+#define CLK_APUV_AHB			0
+#define CLK_APUV_AXI			1
+#define CLK_APUV_ADL			2
+#define CLK_APUV_QOS			3
+#define CLK_APUV_NR_CLK			4
+
+/* APU0 */
+
+#define CLK_APU0_APU			0
+#define CLK_APU0_AXI_M			1
+#define CLK_APU0_JTAG			2
+#define CLK_APU0_PCLK			3
+#define CLK_APU0_NR_CLK			4
+
+/* APU1 */
+
+#define CLK_APU1_APU			0
+#define CLK_APU1_AXI_M			1
+#define CLK_APU1_JTAG			2
+#define CLK_APU1_PCLK			3
+#define CLK_APU1_NR_CLK			4
+
+/* CAMSYS_MAIN */
+
+#define CLK_CAM_M_LARB13		0
+#define CLK_CAM_M_LARB14		1
+#define CLK_CAM_M_RESERVED0		2
+#define CLK_CAM_M_CAM			3
+#define CLK_CAM_M_CAMTG			4
+#define CLK_CAM_M_SENINF		5
+#define CLK_CAM_M_CAMSV1		6
+#define CLK_CAM_M_CAMSV2		7
+#define CLK_CAM_M_CAMSV3		8
+#define CLK_CAM_M_CCU0			9
+#define CLK_CAM_M_CCU1			10
+#define CLK_CAM_M_MRAW0			11
+#define CLK_CAM_M_RESERVED2		12
+#define CLK_CAM_M_FAKE_ENG		13
+#define CLK_CAM_M_CCU_GALS		14
+#define CLK_CAM_M_CAM2MM_GALS		15
+#define CLK_CAM_M_NR_CLK		16
+
+/* CAMSYS_RAWA */
+
+#define CLK_CAM_RA_LARBX		0
+#define CLK_CAM_RA_CAM			1
+#define CLK_CAM_RA_CAMTG		2
+#define CLK_CAM_RA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+
+#define CLK_CAM_RB_LARBX		0
+#define CLK_CAM_RB_CAM			1
+#define CLK_CAM_RB_CAMTG		2
+#define CLK_CAM_RB_NR_CLK		3
+
+/* IPESYS */
+
+#define CLK_IPE_LARB19			0
+#define CLK_IPE_LARB20			1
+#define CLK_IPE_SMI_SUBCOM		2
+#define CLK_IPE_FD			3
+#define CLK_IPE_FE			4
+#define CLK_IPE_RSC			5
+#define CLK_IPE_DPE			6
+#define CLK_IPE_GALS			7
+#define CLK_IPE_NR_CLK			8
+
+/* MDPSYS_CONFIG */
+
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_TDSHP0			1
+#define CLK_MDP_IMG_DL_ASYNC0		2
+#define CLK_MDP_IMG_DL_ASYNC1		3
+#define CLK_MDP_RDMA1			4
+#define CLK_MDP_TDSHP1			5
+#define CLK_MDP_SMI0			6
+#define CLK_MDP_APB_BUS			7
+#define CLK_MDP_WROT0			8
+#define CLK_MDP_RSZ0			9
+#define CLK_MDP_HDR0			10
+#define CLK_MDP_MUTEX0			11
+#define CLK_MDP_WROT1			12
+#define CLK_MDP_RSZ1			13
+#define CLK_MDP_FAKE_ENG0		14
+#define CLK_MDP_AAL0			15
+#define CLK_MDP_AAL1			16
+#define CLK_MDP_COLOR0			17
+#define CLK_MDP_IMG_DL_RELAY0_ASYNC0	18
+#define CLK_MDP_IMG_DL_RELAY1_ASYNC1	19
+#define CLK_MDP_NR_CLK			20
+
+/* SCP_SYS */
+#define SCP_SYS_MD1	0
+#define SCP_SYS_CONN	1
+#define SCP_SYS_MFG0	2
+#define SCP_SYS_MFG1	3
+#define SCP_SYS_MFG2	4
+#define SCP_SYS_MFG3	5
+#define SCP_SYS_MFG5	6
+#define SCP_SYS_ISP	7
+#define SCP_SYS_ISP2	8
+#define SCP_SYS_IPE	9
+#define SCP_SYS_VDEC	10
+#define SCP_SYS_VENC	11
+#define SCP_SYS_DIS	12
+#define SCP_SYS_AUDIO	13
+#define SCP_SYS_ADSP	14
+#define SCP_SYS_CAM	15
+#define SCP_SYS_CAM_RAWA	16
+#define SCP_SYS_CAM_RAWB	17
+#define SCP_SYS_VPU	18
+#define SCP_NR_SYSS	19
+
+#endif /* _DT_BINDINGS_CLK_MT6853_H */
+

include/dt-bindings/clock/mt6873-clk.h

@@ -0,0 +1,723 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+/* TOPCKGEN */
+#define TOP_MUX_AXI 1
+#define TOP_MUX_SPM 2
+#define TOP_MUX_SCP 3
+#define TOP_MUX_BUS_AXIMEM 4
+#define TOP_MUX_DISP 5
+#define TOP_MUX_MDP 6
+#define TOP_MUX_IMG1 7
+#define TOP_MUX_IMG2 8
+#define TOP_MUX_IPE 9
+#define TOP_MUX_DPE 10
+#define TOP_MUX_CAM 11
+#define TOP_MUX_CCU 12
+#define TOP_MUX_DSP 13
+#define TOP_MUX_DSP1 14
+#define TOP_MUX_DSP2 15
+#define TOP_MUX_DSP2_NPUPLL 16
+#define TOP_MUX_DSP5 17
+#define TOP_MUX_DSP5_APUPLL 18
+#define TOP_MUX_DSP7 19
+#define TOP_MUX_IPU_IF 20
+#define TOP_MUX_MFG_PLL 21
+#define TOP_MUX_MFG_REF 22
+#define TOP_MUX_CAMTG 23
+#define TOP_MUX_CAMTG2 24
+#define TOP_MUX_CAMTG3 25
+#define TOP_MUX_CAMTG4 26
+#define TOP_MUX_CAMTG5 27
+#define TOP_MUX_CAMTG6 28
+#define TOP_MUX_UART 29
+#define TOP_MUX_SPI 30
+#define TOP_MUX_MSDC50_0_HCLK 31
+#define TOP_MUX_MSDC50_0 32
+#define TOP_MUX_MSDC30_1 33
+#define TOP_MUX_MSDC30_2 34
+#define TOP_MUX_AUDIO 35
+#define TOP_MUX_AUD_INTBUS 36
+#define TOP_MUX_PWRAP_ULPOSC 37
+#define TOP_MUX_ATB 38
+#define TOP_MUX_SSPM 39
+#define TOP_MUX_DPI 40
+#define TOP_MUX_SCAM 41
+#define TOP_MUX_DISP_PWM 42
+#define TOP_MUX_USB_TOP 43
+#define TOP_MUX_SSUSB_XHCI 44
+#define TOP_MUX_I2C 45
+#define TOP_MUX_SENINF 46
+#define TOP_MUX_SENINF1 47
+#define TOP_MUX_SENINF2 48
+#define TOP_MUX_SENINF3 49
+#define TOP_MUX_TL 50
+#define TOP_MUX_DXCC 51
+#define TOP_MUX_AUD_ENGEN1 52
+#define TOP_MUX_AUD_ENGEN2 53
+#define TOP_MUX_AES_UFSFDE 54
+#define TOP_MUX_UFS 55
+#define TOP_MUX_AUD_1 56
+#define TOP_MUX_AUD_2 57
+#define TOP_MUX_ADSP 58
+#define TOP_MUX_DPMAIF_MAIN 59
+#define TOP_MUX_VENC 60
+#define TOP_MUX_VDEC 61
+#define TOP_MUX_CAMTM 62
+#define TOP_MUX_PWM 63
+#define TOP_MUX_AUDIO_H 64
+#define TOP_MUX_MCUPM 65
+#define TOP_MUX_SPMI_MST 66
+#define TOP_MUX_DVFSRC 67
+#define TOP_MUX_AES_MSDCFDE 68
+#define TOP_MUX_SFLASH 69
+#define TOP_MAINPLL_CK 70
+#define TOP_MAINPLL_D3 71
+#define TOP_MAINPLL_D4 72
+#define TOP_MAINPLL_D4_D2 73
+#define TOP_MAINPLL_D4_D4 74
+#define TOP_MAINPLL_D4_D8 75
+#define TOP_MAINPLL_D4_D16 76
+#define TOP_MAINPLL_D5 77
+#define TOP_MAINPLL_D5_D2 78
+#define TOP_MAINPLL_D5_D4 79
+#define TOP_MAINPLL_D5_D8 80
+#define TOP_MAINPLL_D6 81
+#define TOP_MAINPLL_D6_D2 82
+#define TOP_MAINPLL_D6_D4 83
+#define TOP_MAINPLL_D7 84
+#define TOP_MAINPLL_D7_D2 85
+#define TOP_MAINPLL_D7_D4 86
+#define TOP_MAINPLL_D7_D8 87
+#define TOP_UNIVPLL_CK 88
+#define TOP_UNIVPLL_D3 89
+#define TOP_UNIVPLL_D4 90
+#define TOP_UNIVPLL_D4_D2 91
+#define TOP_UNIVPLL_D4_D4 92
+#define TOP_UNIVPLL_D4_D8 93
+#define TOP_UNIVPLL_D5 94
+#define TOP_UNIVPLL_D5_D2 95
+#define TOP_UNIVPLL_D5_D4 96
+#define TOP_UNIVPLL_D5_D8 97
+#define TOP_UNIVPLL_D6 98
+#define TOP_UNIVPLL_D6_D2 99
+#define TOP_UNIVPLL_D6_D4 100
+#define TOP_UNIVPLL_D6_D8 101
+#define TOP_UNIVPLL_D6_D16 102
+#define TOP_UNIVPLL_D7 103
+#define TOP_APLL1_CK 104
+#define TOP_APLL1_D2			105	/* add manually */
+#define TOP_APLL1_D4			106	/* add manually */
+#define TOP_APLL1_D8			107	/* add manually */
+#define TOP_APLL2_CK 108
+#define TOP_APLL2_D2			109	/* add manually */
+#define TOP_APLL2_D4			110	/* add manually */
+#define TOP_APLL2_D8			111	/* add manually */
+#define TOP_MMPLL_D4 112
+#define TOP_MMPLL_D4_D2 113
+#define TOP_MMPLL_D5 114
+#define TOP_MMPLL_D5_D2 115
+#define TOP_MMPLL_D6 116
+#define TOP_MMPLL_D6_D2 117
+#define TOP_MMPLL_D7 118
+#define TOP_MMPLL_D9 119
+#define TOP_APUPLL_CK 120
+#define TOP_NPUPLL_CK 121
+#define TOP_USBPLL_CK 122
+#define TOP_TVDPLL_CK 123
+#define TOP_TVDPLL_D2 124
+#define TOP_TVDPLL_D4 125
+#define TOP_TVDPLL_D8 126
+#define TOP_TVDPLL_D16 127
+#define TOP_MSDCPLL_CK 128
+#define TOP_MSDCPLL_D2 129
+#define TOP_MSDCPLL_D4 130
+#define TOP_AD_OSC_CK 131
+#define TOP_OSC_D2 132
+#define TOP_OSC_D4 133
+#define TOP_OSC_D8 134
+#define TOP_OSC_D10 135
+#define TOP_OSC_D16 136
+#define TOP_OSC_D20 137
+#define TOP_CLK26M			138	/* add manually */
+#define TOP_CLK13M			139	/* add manually */
+#define TOP_F26M_CK_D2			140//used	/* add manually */
+#define TOP_UNIVP_192M_CK		141	/* add manually */
+#define TOP_UNIVP_192M_D2		142	/* add manually */
+#define TOP_UNIVP_192M_D4		143	/* add manually */
+#define TOP_UNIVP_192M_D8		144	/* add manually */
+#define TOP_UNIVP_192M_D16		145	/* add manually */
+#define TOP_UNIVP_192M_D32		146	/* add manually */
+#define TOP_MFGPLL_CK			147	/* add manually */
+#define TOP_ADSPPLL_CK			148	/* add manually */
+#define TOP_I2S0_M_SEL			149	/* add manually */
+#define TOP_I2S1_M_SEL			150	/* add manually */
+#define TOP_I2S2_M_SEL			151	/* add manually */
+#define TOP_I2S3_M_SEL			152	/* add manually */
+#define TOP_I2S4_M_SEL			153	/* add manually */
+#define TOP_I2S5_M_SEL			154	/* add manually */
+#define TOP_I2S6_M_SEL			155	/* add manually */
+#define TOP_I2S7_M_SEL			156	/* add manually */
+#define TOP_I2S8_M_SEL			157	/* add manually */
+#define TOP_I2S9_M_SEL			158	/* add manually */
+#define TOP_APLL12_DIV0			159	/* add manually */
+#define TOP_APLL12_DIV1			160	/* add manually */
+#define TOP_APLL12_DIV2			161	/* add manually */
+#define TOP_APLL12_DIV3			162	/* add manually */
+#define TOP_APLL12_DIV4			163	/* add manually */
+#define TOP_APLL12_DIVB			164	/* add manually */
+#define TOP_APLL12_DIV5			165	/* add manually */
+#define TOP_APLL12_DIV6			166	/* add manually */
+#define TOP_APLL12_DIV7			167	/* add manually */
+#define TOP_APLL12_DIV8			168	/* add manually */
+#define TOP_APLL12_DIV9			169	/* add manually */
+#define TOP_MUX_DSP1_NPUPLL 170
+#define TOP_NR_CLK	171
+
+/* APMIXED */
+#define APMIXED_MAINPLL 1
+#define APMIXED_UNIVPLL 2
+#define APMIXED_MSDCPLL 3
+#define APMIXED_MMPLL 4
+#define APMIXED_ADSPPLL 5
+#define APMIXED_MFGPLL 6
+#define APMIXED_TVDPLL 7
+#define APMIXED_APLL1 8
+#define APMIXED_APLL2 9
+#define APMIXED_APUPLL 10
+#define APMIXED_NPUPLL 11
+#define APMIXED_USBPLL 12
+#define APMIXED_MIPID0_26M 13
+#define APMIXED_NR_CLK 14
+
+/* APU0 */
+#define APU0_APU_CG 1
+#define APU0_AXI_M_CG 2
+#define APU0_JTAG_CG 3
+#define APU0_NR_CLK 4
+/* APU1 */
+#define APU1_APU_CG 1
+#define APU1_AXI_M_CG 2
+#define APU1_JTAG_CG 3
+#define APU1_NR_CLK 4
+/* APUSYS_VCORE */
+#define APUSYS_VCORE_AHB_CG 1
+#define APUSYS_VCORE_AXI_CG 2
+#define APUSYS_VCORE_ADL_CG 3
+#define APUSYS_VCORE_QOS_CG 4
+#define APUSYS_VCORE_NR_CLK 5
+/* APU_CONN */
+#define APU_CONN_APU_CG 1
+#define APU_CONN_AHB_CG 2
+#define APU_CONN_AXI_CG 3
+#define APU_CONN_ISP_CG 4
+#define APU_CONN_CAM_ADL_CG 5
+#define APU_CONN_IMG_ADL_CG 6
+#define APU_CONN_EMI_26M_CG 7
+#define APU_CONN_VPU_UDI_CG 8
+#define APU_CONN_EDMA_0_CG 9
+#define APU_CONN_EDMA_1_CG 10
+#define APU_CONN_EDMAL_0_CG 11
+#define APU_CONN_EDMAL_1_CG 12
+#define APU_CONN_MNOC_CG 13
+#define APU_CONN_TCM_CG 14
+#define APU_CONN_MD32_CG 15
+#define APU_CONN_IOMMU_0_CG 16
+#define APU_CONN_IOMMU_1_CG 17
+#define APU_CONN_MD32_32K_CG 18
+#define APU_CONN_NR_CLK 19
+
+/* APU_MDLA0 */
+#define APU_MDLA0_MDLA_CG0 1
+#define APU_MDLA0_MDLA_CG1 2
+#define APU_MDLA0_MDLA_CG2 3
+#define APU_MDLA0_MDLA_CG3 4
+#define APU_MDLA0_MDLA_CG4 5
+#define APU_MDLA0_MDLA_CG5 6
+#define APU_MDLA0_MDLA_CG6 7
+#define APU_MDLA0_MDLA_CG7 8
+#define APU_MDLA0_MDLA_CG8 9
+#define APU_MDLA0_MDLA_CG9 10
+#define APU_MDLA0_MDLA_CG10 11
+#define APU_MDLA0_MDLA_CG11 12
+#define APU_MDLA0_MDLA_CG12 13
+#define APU_MDLA0_APB_CG 14
+#define APU_MDLA0_AXI_M_CG 15
+#define APU_MDLA0_NR_CLK 16
+
+/* AUDIO */
+#define AUDIO_PDN_AFE 1
+#define AUDIO_PDN_22M 2
+#define AUDIO_PDN_24M 3
+#define AUDIO_PDN_APLL2_TUNER 4
+#define AUDIO_PDN_APLL_TUNER 5
+#define AUDIO_PDN_TDM_CK 6
+#define AUDIO_PDN_ADC 7
+#define AUDIO_PDN_DAC 8
+#define AUDIO_PDN_DAC_PREDIS 9
+#define AUDIO_PDN_TML 10
+#define AUDIO_PDN_NLE 11
+#define AUDIO_I2S1_BCLK_SW_CG 12
+#define AUDIO_I2S2_BCLK_SW_CG 13
+#define AUDIO_I2S3_BCLK_SW_CG 14
+#define AUDIO_I2S4_BCLK_SW_CG 15
+#define AUDIO_PDN_CONNSYS_I2S_ASRC 16
+#define AUDIO_PDN_GENERAL1_ASRC 17
+#define AUDIO_PDN_GENERAL2_ASRC 18
+#define AUDIO_PDN_DAC_HIRES 19
+#define AUDIO_PDN_ADC_HIRES 20
+#define AUDIO_PDN_ADC_HIRES_TML 21
+#define AUDIO_PDN_ADDA6_ADC 22
+#define AUDIO_PDN_ADDA6_ADC_HIRES 23
+#define AUDIO_PDN_3RD_DAC 24
+#define AUDIO_PDN_3RD_DAC_PREDIS 25
+#define AUDIO_PDN_3RD_DAC_TML 26
+#define AUDIO_PDN_3RD_DAC_HIRES 27
+#define AUDIO_I2S5_BCLK_SW_CG 28
+#define AUDIO_I2S6_BCLK_SW_CG 29
+#define AUDIO_I2S7_BCLK_SW_CG 30
+#define AUDIO_I2S8_BCLK_SW_CG 31
+#define AUDIO_I2S9_BCLK_SW_CG 32
+#define AUDIO_NR_CLK 33
+
+/* CAMSYS_MAIN */
+#define CAMSYS_MAIN_LARB13_CGPDN 1
+#define CAMSYS_MAIN_DFP_VAD_CGPDN 2
+#define CAMSYS_MAIN_CAM_CGPDN 3
+#define CAMSYS_MAIN_CAMTG_CGPDN 4
+#define CAMSYS_MAIN_LARB14_CGPDN 5
+#define CAMSYS_MAIN_SENINF_CGPDN 6
+#define CAMSYS_MAIN_CAMSV0_CGPDN 7
+#define CAMSYS_MAIN_CAMSV1_CGPDN 8
+#define CAMSYS_MAIN_CAMSV2_CGPDN 9
+#define CAMSYS_MAIN_CAMSV3_CGPDN 10
+#define CAMSYS_MAIN_CCU0_CGPDN 11
+#define CAMSYS_MAIN_CCU1_CGPDN 12
+#define CAMSYS_MAIN_MRAW0_CGPDN 13
+#define CAMSYS_MAIN_FAKE_ENG_CGPDN 14
+#define CAMSYS_MAIN_CCU_GALS_CGPDN 15
+#define CAMSYS_MAIN_CAM2MM_GALS_CGPDN 16
+#define CAMSYS_MAIN_NR_CLK 17
+/* CAMSYS_RAWA */
+#define CAMSYS_RAWA_LARBX_CGPDN 1
+#define CAMSYS_RAWA_CAM_CGPDN 2
+#define CAMSYS_RAWA_CAMTG_CGPDN 3
+#define CAMSYS_RAWA_NR_CLK 4
+/* CAMSYS_RAWB */
+#define CAMSYS_RAWB_LARBX_CGPDN 1
+#define CAMSYS_RAWB_CAM_CGPDN 2
+#define CAMSYS_RAWB_CAMTG_CGPDN 3
+#define CAMSYS_RAWB_NR_CLK 4
+/* CAMSYS_RAWC */
+#define CAMSYS_RAWC_LARBX_CGPDN 1
+#define CAMSYS_RAWC_CAM_CGPDN 2
+#define CAMSYS_RAWC_CAMTG_CGPDN 3
+#define CAMSYS_RAWC_NR_CLK 4
+
+/* GCE */
+#define GCE_SW_CG_0 1
+#define GCE_NR_CLK 2
+
+/* IMGSYS1 */
+#define IMGSYS1_LARB9_CGPDN 1
+#define IMGSYS1_LARB10_CGPDN 2
+#define IMGSYS1_DIP_CGPDN 3
+#define IMGSYS1_GALS_CGPDN 4
+#define IMGSYS1_NR_CLK 5
+/* IMGSYS2 */
+#define IMGSYS2_LARB11_CGPDN 1
+#define IMGSYS2_LARB12_CGPDN 2
+#define IMGSYS2_MFB_CGPDN 3
+#define IMGSYS2_WPE_CGPDN 4
+#define IMGSYS2_MSS_CGPDN 5
+#define IMGSYS2_GALS_CGPDN 6
+#define IMGSYS2_NR_CLK 7
+
+/* IMP_IIC_WRAP_C */
+#define IMP_IIC_WRAP_C_AP_I2C10_CG_RO 1
+#define IMP_IIC_WRAP_C_AP_I2C11_CG_RO 2
+#define IMP_IIC_WRAP_C_AP_I2C12_CG_RO 3
+#define IMP_IIC_WRAP_C_AP_I2C13_CG_RO 4
+#define IMP_IIC_WRAP_C_NR_CLK 5
+/* IMP_IIC_WRAP_E */
+#define IMP_IIC_WRAP_E_AP_I2C3_CG_RO 1
+#define IMP_IIC_WRAP_E_NR_CLK 2
+/* IMP_IIC_WRAP_N */
+#define IMP_IIC_WRAP_N_AP_I2C0_CG_RO 1
+#define IMP_IIC_WRAP_N_AP_I2C6_CG_RO 2
+#define IMP_IIC_WRAP_N_NR_CLK 3
+/* IMP_IIC_WRAP_S */
+//#define IMP_IIC_WRAP_S_AP_I2C5_CG_RO 1
+#define IMP_IIC_WRAP_S_AP_I2C7_CG_RO 1
+#define IMP_IIC_WRAP_S_AP_I2C8_CG_RO 2
+#define IMP_IIC_WRAP_S_AP_I2C9_CG_RO 3
+#define IMP_IIC_WRAP_S_NR_CLK 4
+/* IMP_IIC_WRAP_W */
+//#define IMP_IIC_WRAP_W_AP_I2C0_CG_RO 1
+#define IMP_IIC_WRAP_W_AP_I2C5_CG_RO 1
+#define IMP_IIC_WRAP_W_NR_CLK 2
+/* IMP_IIC_WRAP_WS */
+//#define IMP_IIC_WRAP_WS_AP_I2C0_CG_RO 1
+#define IMP_IIC_WRAP_WS_AP_I2C1_CG_RO 1
+#define IMP_IIC_WRAP_WS_AP_I2C2_CG_RO 2
+#define IMP_IIC_WRAP_WS_AP_I2C4_CG_RO 3
+#define IMP_IIC_WRAP_WS_NR_CLK 4
+
+/* INFRACFG_AO */
+#define INFRACFG_AO_PMIC_CG_TMR 1
+#define INFRACFG_AO_PMIC_CG_AP 2
+#define INFRACFG_AO_PMIC_CG_MD 3
+#define INFRACFG_AO_PMIC_CG_CONN 4
+#define INFRACFG_AO_SCPSYS_CG 5
+#define INFRACFG_AO_SEJ_CG 6
+#define INFRACFG_AO_APXGPT_CG 7
+#define INFRACFG_AO_MCUPM_CG 8
+#define INFRACFG_AO_GCE_CG 9
+#define INFRACFG_AO_GCE2_CG 10
+#define INFRACFG_AO_THERM_CG 11
+#define INFRACFG_AO_I2C0_CG 12
+#define INFRACFG_AO_I2C1_CG 13
+#define INFRACFG_AO_I2C2_CG 14
+#define INFRACFG_AO_I2C3_CG 15
+#define INFRACFG_AO_PWM_HCLK_CG 16
+#define INFRACFG_AO_PWM1_CG 17
+#define INFRACFG_AO_PWM2_CG 18
+#define INFRACFG_AO_PWM3_CG 19
+#define INFRACFG_AO_PWM4_CG 20
+#define INFRACFG_AO_PWM_CG 21
+#define INFRACFG_AO_UART0_CG 22
+#define INFRACFG_AO_UART1_CG 23
+#define INFRACFG_AO_UART2_CG 24
+#define INFRACFG_AO_UART3_CG 25
+#define INFRACFG_AO_GCE_26M 26
+#define INFRACFG_AO_CQ_DMA_FPC 27
+#define INFRACFG_AO_BTIF_CG 28
+#define INFRACFG_AO_MD2MD_CCIF3_CG 29
+#define INFRACFG_AO_SPI0_CG 30
+#define INFRACFG_AO_MSDC0_CG 31
+#define INFRACFG_AO_MSDC1_CG 32
+#define INFRACFG_AO_MSDC0_SRC_CLK_CG 33
+#define INFRACFG_AO_DVFSRC_CG 34
+#define INFRACFG_AO_GCPU_CG 35
+#define INFRACFG_AO_TRNG_CG 36
+#define INFRACFG_AO_AUXADC_CG 37
+#define INFRACFG_AO_CPUM_CG 38
+#define INFRACFG_AO_CCIF1_AP_CG 39
+#define INFRACFG_AO_CCIF1_MD_CG 40
+#define INFRACFG_AO_AUXADC_MD_CG 41
+#define INFRACFG_AO_PCIE_TL_CLK26M_CG 42
+#define INFRACFG_AO_MSDC1_SRC_CLK_CG 43
+#define INFRACFG_AO_PCIE_TL_CLK96M_CG 44
+#define INFRACFG_AO_PCIE_PL_PCLK250M_CG 45
+#define INFRACFG_AO_DEVICE_APC_CG 46
+#define INFRACFG_AO_CCIF_AP_CG 47
+#define INFRACFG_AO_DEBUGSYS_CG 48
+#define INFRACFG_AO_AUDIO_CG 49
+#define INFRACFG_AO_CCIF_MD_CG 50
+#define INFRACFG_AO_DXCC_SEC_CORE_CG 51
+#define INFRACFG_AO_DXCC_AO_CG 52
+#define INFRACFG_AO_DBG_TRACE_CG 53
+#define INFRACFG_AO_DEVMPU_BCLK_CG 54
+#define INFRACFG_AO_DRAMC_F26M_CG 55
+#define INFRACFG_AO_IRTX_CG 56
+#define INFRACFG_AO_SSUSB_CG 57
+#define INFRACFG_AO_DISP_PWM_CG 58
+#define INFRACFG_AO_CLDMA_BCLK_CK 59
+#define INFRACFG_AO_AUDIO_26M_BCLK_CK 60
+#define INFRACFG_AO_MODEM_TEMP_SHARE_CG 61
+#define INFRACFG_AO_SPI1_CG 62
+#define INFRACFG_AO_I2C4_CG 63
+#define INFRACFG_AO_SPI2_CG 64
+#define INFRACFG_AO_SPI3_CG 65
+#define INFRACFG_AO_UNIPRO_SYSCLK_CG 66
+#define INFRACFG_AO_UNIPRO_TICK_CG 67
+#define INFRACFG_AO_UFS_MP_SAP_BCLK_CG 68
+#define INFRACFG_AO_MD32_BCLK_CG 69
+#define INFRACFG_AO_SSPM_CG 70
+#define INFRACFG_AO_UNIPRO_MBIST_CG 71
+#define INFRACFG_AO_SSPM_BUS_HCLK_CG 72
+#define INFRACFG_AO_I2C5_CG 73
+#define INFRACFG_AO_I2C5_ARBITER_CG 74
+#define INFRACFG_AO_I2C5_IMM_CG 75
+#define INFRACFG_AO_I2C1_ARBITER_CG 76
+#define INFRACFG_AO_I2C1_IMM_CG 77
+#define INFRACFG_AO_I2C2_ARBITER_CG 78
+#define INFRACFG_AO_I2C2_IMM_CG 79
+#define INFRACFG_AO_SPI4_CG 80
+#define INFRACFG_AO_SPI5_CG 81
+#define INFRACFG_AO_CQ_DMA_CG 82
+#define INFRACFG_AO_UFS_CG 83
+#define INFRACFG_AO_AES_UFSFDE_CG 84
+#define INFRACFG_AO_UFS_TICK_CG 85
+#define INFRACFG_AO_SSUSB_XHCI_CG 86
+#define INFRACFG_AO_MSDC0_SELF_CG 87
+#define INFRACFG_AO_MSDC1_SELF_CG 88
+#define INFRACFG_AO_MSDC2_SELF_CG 89
+#define INFRACFG_AO_SSPM_26M_SELF_CG 90
+#define INFRACFG_AO_SSPM_32K_SELF_CG 91
+#define INFRACFG_AO_UFS_AXI_CG 92
+#define INFRACFG_AO_I2C6_CG 93
+#define INFRACFG_AO_AP_MSDC0_CG 94
+#define INFRACFG_AO_MD_MSDC0_CG 95
+#define INFRACFG_AO_CCIF5_AP_CG 96
+#define INFRACFG_AO_CCIF5_MD_CG 97
+#define INFRACFG_AO_PCIE_TOP_HCLK133M_CG 98
+#define INFRACFG_AO_FLASHIF_TOP_HCLK133M_CG 99
+#define INFRACFG_AO_PCIE_PERI_CLK26M_CG 100
+#define INFRACFG_AO_CCIF2_AP_CG 101
+#define INFRACFG_AO_CCIF2_MD_CG 102
+#define INFRACFG_AO_CCIF3_AP_CG 103
+#define INFRACFG_AO_CCIF3_MD_CG 104
+#define INFRACFG_AO_SEJ_F13M_CG 105
+#define INFRACFG_AO_AES_CG 106
+#define INFRACFG_AO_I2C7_CG 107
+#define INFRACFG_AO_I2C8_CG 108
+#define INFRACFG_AO_FBIST2FPC_CG 109
+#define INFRACFG_AO_DEVICE_APC_SYNC_CG 110
+#define INFRACFG_AO_DPMAIF_MAIN_CG 111
+#define INFRACFG_AO_PCIE_TL_CLK32K_CG 112
+#define INFRACFG_AO_CCIF4_AP_CG 113
+#define INFRACFG_AO_CCIF4_MD_CG 114
+#define INFRACFG_AO_SPI6_CK_CG 115
+#define INFRACFG_AO_SPI7_CK_CG 116
+#define INFRACFG_AO_HF133M_MCLK_PERI_CG 117
+#define INFRACFG_AO_HF66M_MCLK_PERI_CG 118
+#define INFRACFG_AO_HD66M_PERIBUS_MCLK_PERI_CG 119
+#define INFRACFG_AO_FREE_DCM_133M_CG 120
+#define INFRACFG_AO_FREE_DCM_66M_CG 121
+#define INFRACFG_AO_PERIBUS_DCM_133M_CG 122
+#define INFRACFG_AO_PERIBUS_DCM_66M_CG 123
+#define INFRACFG_AO_PERITOP_PAR_WARP_CG 124
+#define INFRACFG_AO_PERITOP_PAR_WARP_CKCTL_CG 125
+#define INFRACFG_AO_FLASHIF_PERI_CLK26M_CG 126
+#define INFRACFG_AO_FLASHIF_SFLASH_CG 127
+#define INFRACFG_AO_AP_DMA_PSEUDO_CG	128/* add manually */
+#define INFRACFG_AO_AP_DMA_CG		129/* add manually */
+#define INFRACFG_AO_MSDC2_CG 130
+#define INFRACFG_AO_MSDC2_SRC_CLK_CG 131
+#define INFRACFG_AO_NR_CLK 132
+
+/* IPESYS */
+#define IPESYS_LARB19_CGPDN 1
+#define IPESYS_LARB20_CGPDN 2
+#define IPESYS_IPE_SMI_SUBCOM_CGPDN 3
+#define IPESYS_FD_CGPDN 4
+#define IPESYS_FE_CGPDN 5
+#define IPESYS_RSC_CGPDN 6
+#define IPESYS_DPE_CGPDN 7
+#define IPESYS_GALS_CGPDN 8
+#define IPESYS_NR_CLK 9
+
+/* MFGCFG */
+#define MFGCFG_BG3D 1
+#define MFGCFG_NR_CLK 2
+
+/* MMSYS_CONFIG */
+#define MM_DISP_MUTEX0	1
+#define MM_DISP_CONFIG	2
+#define MM_DISP_OVL0	3
+#define MM_DISP_RDMA0	4
+#define MM_DISP_OVL0_2L	5
+#define MM_DISP_WDMA0	6
+#define MM_DISP_UFBC_WDMA0	7
+#define MM_DISP_RSZ0	8
+#define MM_DISP_AAL0	9
+#define MM_DISP_CCORR0	10
+#define MM_DISP_DITHER0	11
+#define MM_SMI_INFRA	12
+#define MM_DISP_GAMMA0	13
+#define MM_DISP_POSTMASK0	14
+#define MM_DISP_DSC_WRAP0	15
+#define MM_DSI0	16
+#define MM_DISP_COLOR0	17
+#define MM_SMI_COMMON	18
+#define MM_DISP_FAKE_ENG0	19
+#define MM_DISP_FAKE_ENG1	20
+#define MM_MDP_TDSHP4	21
+#define MM_MDP_RSZ4	22
+#define MM_MDP_AAL4	23
+#define MM_MDP_HDR4	24
+#define MM_MDP_RDMA4	25
+#define MM_MDP_COLOR4	26
+#define MM_DISP_Y2R0	27
+#define MM_SMI_GALS	28
+#define MM_DISP_OVL2_2L	29
+#define MM_DISP_RDMA4	30
+#define MM_DISP_DPI0	31
+#define MM_SMI_IOMMU	32
+#define MM_DSI_DSI0	33
+#define MM_DPI_DPI0	34
+#define MM_DP_INTF	35
+#define MM_26MHZ	36
+#define MM_32KHZ	37
+#define MM_NR_CLK	38
+
+/* MSDC0 */
+#define MSDC0_AXI_WRAP_CKEN 1
+#define MSDC0_NR_CLK 2
+/* PERICFG */
+#define PERICFG_PERIAXI_CG_DISABLE 1
+#define PERICFG_NR_CLK 2
+
+/* VDEC_CORE_GCON */
+#define VDEC_GCON_LARB1_CKEN 1
+#define VDEC_GCON_LAT_CKEN 2
+#define VDEC_GCON_LAT_ACTIVE 3
+#define VDEC_GCON_LAT_CKEN_ENG 4
+#define VDEC_GCON_VDEC_CKEN 5
+#define VDEC_GCON_VDEC_ACTIVE 6
+#define VDEC_GCON_VDEC_CKEN_ENG 7
+#define VDEC_GCON_NR_CLK 8
+/* VDEC_SOC_GCON */
+#define VDEC_SOC_GCON_LARB1_CKEN 1
+#define VDEC_SOC_GCON_LAT_CKEN 2
+#define VDEC_SOC_GCON_LAT_ACTIVE 3
+#define VDEC_SOC_GCON_LAT_CKEN_ENG 4
+#define VDEC_SOC_GCON_VDEC_CKEN 5
+#define VDEC_SOC_GCON_VDEC_ACTIVE 6
+#define VDEC_SOC_GCON_VDEC_CKEN_ENG 7
+#define VDEC_SOC_GCON_NR_CLK 8
+
+/* VENC_GCON */
+#define VENC_GCON_SET0_LARB 1
+#define VENC_GCON_SET1_VENC 2
+#define VENC_GCON_SET2_JPGENC 3
+#define VENC_GCON_SET5_GALS 4
+#define VENC_GCON_NR_CLK 5
+
+/* MSDCSYS */
+#define MSDC_AES_CK_0P_CKEN 1
+#define MSDC_SRC_CK_0P_CKEN 2
+#define MSDC_SRC_CK_1P_CKEN 3
+#define MSDC_SRC_CK_2P_CKEN 4
+#define MSDC_PCLK_CK_MSDC0_CKEN 5
+#define MSDC_PCLK_CK_MSDC1_CKEN 6
+#define MSDC_PCLK_CK_MSDC2_CKEN 7
+#define MSDC_PCLK_CK_CFG_CKEN 8
+#define MSDC_AXI_CK_CKEN 9
+#define MSDC_HCLK_MST_CK_0P_CKEN 10
+#define MSDC_HCLK_MST_CK_1P_CKEN 11
+#define MSDC_HCLK_MST_CK_2P_CKEN 12
+#define MSDC_MEM_OFF_DLY_26M_CK_CKEN 13
+#define MSDC_32K_CK_CKEN 14
+#define MSDC_AHB2AXI_BRG_AXI_CKEN 15
+#define MSDC_NR_CLK 16
+/* Note: TOPCK register offset definition is generated from parsing
+ * TOPCKGEN's register (project.h) with keyword "CLK_CFG_"
+ */
+/* #define TOPCKGEN_BASE 0x10000000 */
+
+#define CLK_CFG_UPDATE 0x004
+#define CLK_CFG_UPDATE1 0x008
+#define CLK_CFG_UPDATE2 0x00c
+#define CLK_CFG_0 0x010
+#define CLK_CFG_0_SET 0x014
+#define CLK_CFG_0_CLR 0x018
+#define CLK_CFG_1 0x020
+#define CLK_CFG_1_SET 0x024
+#define CLK_CFG_1_CLR 0x028
+#define CLK_CFG_2 0x030
+#define CLK_CFG_2_SET 0x034
+#define CLK_CFG_2_CLR 0x038
+#define CLK_CFG_3 0x040
+#define CLK_CFG_3_SET 0x044
+#define CLK_CFG_3_CLR 0x048
+#define CLK_CFG_4 0x050
+#define CLK_CFG_4_SET 0x054
+#define CLK_CFG_4_CLR 0x058
+#define CLK_CFG_5 0x060
+#define CLK_CFG_5_SET 0x064
+#define CLK_CFG_5_CLR 0x068
+#define CLK_CFG_6 0x070
+#define CLK_CFG_6_SET 0x074
+#define CLK_CFG_6_CLR 0x078
+#define CLK_CFG_7 0x080
+#define CLK_CFG_7_SET 0x084
+#define CLK_CFG_7_CLR 0x088
+#define CLK_CFG_8 0x090
+#define CLK_CFG_8_SET 0x094
+#define CLK_CFG_8_CLR 0x098
+#define CLK_CFG_9 0x0a0
+#define CLK_CFG_9_SET 0x0a4
+#define CLK_CFG_9_CLR 0x0a8
+#define CLK_CFG_10 0x0b0
+#define CLK_CFG_10_SET 0x0b4
+#define CLK_CFG_10_CLR 0x0b8
+#define CLK_CFG_11 0x0c0
+#define CLK_CFG_11_SET 0x0c4
+#define CLK_CFG_11_CLR 0x0c8
+#define CLK_CFG_12 0x0d0
+#define CLK_CFG_12_SET 0x0d4
+#define CLK_CFG_12_CLR 0x0d8
+#define CLK_CFG_13 0x0e0
+#define CLK_CFG_13_SET 0x0e4
+#define CLK_CFG_13_CLR 0x0e8
+#define CLK_CFG_14 0x0f0
+#define CLK_CFG_14_SET 0x0f4
+#define CLK_CFG_14_CLR 0x0f8
+#define CLK_CFG_15 0x100
+#define CLK_CFG_15_SET 0x104
+#define CLK_CFG_15_CLR 0x108
+#define CLK_CFG_16 0x110
+#define CLK_CFG_16_SET 0x114
+#define CLK_CFG_16_CLR 0x118
+
+/* SCP_ADSP */
+#define SCP_ADSP_CK_CG	1
+#define SCP_ADSP_NR_CLK	2
+
+/* SCP_SYS */
+#define SCP_SYS_MD1	1
+#define SCP_SYS_CONN	2
+#define SCP_SYS_MFG0	3
+#define SCP_SYS_MFG1	4
+#define SCP_SYS_MFG2	5
+#define SCP_SYS_MFG3	6
+#define SCP_SYS_MFG4	7
+#define SCP_SYS_MFG5	8
+#define SCP_SYS_MFG6	9
+#define SCP_SYS_ISP	10
+#define SCP_SYS_ISP2	11
+#define SCP_SYS_IPE	12
+#define SCP_SYS_VDEC	13
+#define SCP_SYS_VDEC2	14
+#define SCP_SYS_VENC	15
+#define SCP_SYS_MDP	16
+#define SCP_SYS_DIS	17
+#define SCP_SYS_AUDIO	18
+#define SCP_SYS_ADSP	19
+#define SCP_SYS_CAM	20
+#define SCP_SYS_CAM_RAWA	21
+#define SCP_SYS_CAM_RAWB	22
+#define SCP_SYS_CAM_RAWC	23
+#define SCP_SYS_DP_TX	24
+#define SCP_SYS_MSDC	25
+#define SCP_SYS_VPU	26
+#define SCP_NR_SYSS	27
+
+/* MDPSYS_CONFIG */
+#define MDP_MDP_RDMA0	1
+#define MDP_MDP_TDSHP0	2
+#define MDP_IMG_DL_ASYNC0	3
+#define MDP_IMG_DL_ASYNC1	4
+#define MDP_MDP_RDMA1	5
+#define MDP_MDP_TDSHP1	6
+#define MDP_SMI0	7
+#define MDP_APB_BUS	8
+#define MDP_MDP_WROT0	9
+#define MDP_MDP_RSZ0	10
+#define MDP_MDP_HDR0	11
+#define MDP_MDP_MUTEX0	12
+#define MDP_MDP_WROT1	13
+#define MDP_MDP_RSZ1	14
+#define MDP_MDP_HDR1	15
+#define MDP_MDP_FAKE_ENG0	16
+#define MDP_MDP_AAL0	17
+#define MDP_MDP_AAL1	18
+#define MDP_MDP_COLOR0	19
+#define MDP_MDP_COLOR1	20
+#define MDP_IMG_DL_RELAY0_ASYNC0	21
+#define MDP_IMG_DL_RELAY1_ASYNC1	22
+#define MDP_NR_CLK 23

include/dt-bindings/clock/mt6877-clk.h

@@ -0,0 +1,589 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+#ifndef _DT_BINDINGS_CLK_MT6877_H
+#define _DT_BINDINGS_CLK_MT6877_H
+
+/* TOPCKGEN */
+#define CLK_TOP_MFGPLL1					0
+#define CLK_TOP_MFGPLL4					1
+#define CLK_TOP_MAINPLL_D4				2
+#define CLK_TOP_MAINPLL_D4_D2				3
+#define CLK_TOP_MAINPLL_D4_D4				4
+#define CLK_TOP_MAINPLL_D4_D8				5
+#define CLK_TOP_MAINPLL_D4_D16				6
+#define CLK_TOP_MAINPLL_D5				7
+#define CLK_TOP_MAINPLL_D5_D2				8
+#define CLK_TOP_MAINPLL_D5_D4				9
+#define CLK_TOP_MAINPLL_D5_D8				10
+#define CLK_TOP_MAINPLL_D6				11
+#define CLK_TOP_MAINPLL_D6_D2				12
+#define CLK_TOP_MAINPLL_D6_D4				13
+#define CLK_TOP_MAINPLL_D6_D8				14
+#define CLK_TOP_MAINPLL_D7				15
+#define CLK_TOP_MAINPLL_D7_D2				16
+#define CLK_TOP_MAINPLL_D7_D4				17
+#define CLK_TOP_MAINPLL_D7_D8				18
+#define CLK_TOP_MAINPLL_D9				19
+#define CLK_TOP_UNIVPLL					20
+#define CLK_TOP_UNIVPLL_D4				21
+#define CLK_TOP_UNIVPLL_D4_D2				22
+#define CLK_TOP_UNIVPLL_D4_D4				23
+#define CLK_TOP_UNIVPLL_D4_D8				24
+#define CLK_TOP_UNIVPLL_D5				25
+#define CLK_TOP_UNIVPLL_D5_D2				26
+#define CLK_TOP_UNIVPLL_D5_D4				27
+#define CLK_TOP_UNIVPLL_D6				28
+#define CLK_TOP_UNIVPLL_D6_D2				29
+#define CLK_TOP_UNIVPLL_D6_D4				30
+#define CLK_TOP_UNIVPLL_D6_D8				31
+#define CLK_TOP_UNIVPLL_D6_D16				32
+#define CLK_TOP_UNIVPLL_D7				33
+#define CLK_TOP_UNIVPLL_D7_D2				34
+#define CLK_TOP_UNIVPLL_192M_D2				35
+#define CLK_TOP_UNIVPLL_192M_D4				36
+#define CLK_TOP_UNIVPLL_192M_D8				37
+#define CLK_TOP_UNIVPLL_192M_D16			38
+#define CLK_TOP_UNIVPLL_192M_D32			39
+#define CLK_TOP_APLL1					40
+#define CLK_TOP_APLL1_D2				41
+#define CLK_TOP_APLL1_D4				42
+#define CLK_TOP_APLL1_D8				43
+#define CLK_TOP_APLL2					44
+#define CLK_TOP_APLL2_D2				45
+#define CLK_TOP_APLL2_D4				46
+#define CLK_TOP_APLL2_D8				47
+#define CLK_TOP_ADSPPLL					48
+#define CLK_TOP_MMPLL_D4				49
+#define CLK_TOP_MMPLL_D4_D2				50
+#define CLK_TOP_MMPLL_D5				51
+#define CLK_TOP_MMPLL_D5_D2				52
+#define CLK_TOP_MMPLL_D6				53
+#define CLK_TOP_MMPLL_D6_D2				54
+#define CLK_TOP_MMPLL_D7				55
+#define CLK_TOP_MMPLL_D9				56
+#define CLK_TOP_APUPLL					57
+#define CLK_TOP_NPUPLL					58
+#define CLK_TOP_APUPLL1					59
+#define CLK_TOP_APUPLL2					60
+#define CLK_TOP_TVDPLL					61
+#define CLK_TOP_TVDPLL_D2				62
+#define CLK_TOP_MSDCPLL					63
+#define CLK_TOP_MSDCPLL_D2				64
+#define CLK_TOP_MSDCPLL_D4				65
+#define CLK_TOP_CLKRTC					66
+#define CLK_TOP_TCK_26M_MX9				67
+#define CLK_TOP_F26M_CK_D2				68
+#define CLK_TOP_OSC					69
+#define CLK_TOP_OSC_D2					70
+#define CLK_TOP_OSC_D4					71
+#define CLK_TOP_OSC_D7					72
+#define CLK_TOP_OSC_D8					73
+#define CLK_TOP_OSC_D16					74
+#define CLK_TOP_OSC_D10					75
+#define CLK_TOP_ULPOSC					76
+#define CLK_TOP_F26M					77
+#define CLK_TOP_AXI					78
+#define CLK_TOP_DISP0					79
+#define CLK_TOP_MDP0					80
+#define CLK_TOP_IMG1					81
+#define CLK_TOP_IPE					82
+#define CLK_TOP_DPE					83
+#define CLK_TOP_CAM					84
+#define CLK_TOP_DSP					85
+#define CLK_TOP_DSP1					86
+#define CLK_TOP_DSP2					87
+#define CLK_TOP_DSP4					88
+#define CLK_TOP_DSP7					89
+#define CLK_TOP_FUART					90
+#define CLK_TOP_SPI					91
+#define CLK_TOP_MSDC50_0_HCLK				92
+#define CLK_TOP_MSDC50_0				93
+#define CLK_TOP_MSDC30_1				94
+#define CLK_TOP_AUDIO					95
+#define CLK_TOP_AUD_INTBUS				96
+#define CLK_TOP_FPWRAP_ULPOSC				97
+#define CLK_TOP_FDISP_PWM				98
+#define CLK_TOP_FUSB_TOP				99
+#define CLK_TOP_FSSUSB_XHCI				100
+#define CLK_TOP_I2C					101
+#define CLK_TOP_DXCC					102
+#define CLK_TOP_AUD_ENGEN1				103
+#define CLK_TOP_AUD_ENGEN2				104
+#define CLK_TOP_AES_UFSFDE				105
+#define CLK_TOP_UFS					106
+#define CLK_TOP_AUD_1					107
+#define CLK_TOP_AUD_2					108
+#define CLK_TOP_ADSP					109
+#define CLK_TOP_DPMAIF_MAIN				110
+#define CLK_TOP_VENC					111
+#define CLK_TOP_VDEC					112
+#define CLK_TOP_PWM					113
+#define CLK_TOP_AUDIO_H					114
+#define CLK_TOP_MEM_SUB					115
+#define CLK_TOP_AES_MSDCFDE				116
+#define CLK_TOP_UFS_MBIST				117
+#define CLK_TOP_MSDC_NEW_RX				118
+#define CLK_TOP_MFG_INTERNAL1				119
+#define CLK_TOP_MFG_INTERNAL2				120
+#define CLK_TOP_FI2C_PSEUDO				121
+#define CLK_TOP_AXI_SEL					122
+#define CLK_TOP_SPM_SEL					123
+#define CLK_TOP_SCP_SEL					124
+#define CLK_TOP_BUS_AXIMEM_SEL				125
+#define CLK_TOP_DISP0_SEL				126
+#define CLK_TOP_MDP0_SEL				127
+#define CLK_TOP_IMG1_SEL				128
+#define CLK_TOP_IPE_SEL					129
+#define CLK_TOP_DPE_SEL					130
+#define CLK_TOP_CAM_SEL					131
+#define CLK_TOP_CCU_SEL					132
+#define CLK_TOP_DSP_SEL					133
+#define CLK_TOP_DSP1_SEL				134
+#define CLK_TOP_DSP2_SEL				135
+#define CLK_TOP_DSP4_SEL				136
+#define CLK_TOP_DSP7_SEL				137
+#define CLK_TOP_CAMTG_SEL				138
+#define CLK_TOP_CAMTG2_SEL				139
+#define CLK_TOP_CAMTG3_SEL				140
+#define CLK_TOP_CAMTG4_SEL				141
+#define CLK_TOP_CAMTG5_SEL				142
+#define CLK_TOP_UART_SEL				143
+#define CLK_TOP_SPI_SEL					144
+#define CLK_TOP_MSDC50_0_HCLK_SEL			145
+#define CLK_TOP_MSDC50_0_SEL				146
+#define CLK_TOP_MSDC30_1_SEL				147
+#define CLK_TOP_AUDIO_SEL				148
+#define CLK_TOP_AUD_INTBUS_SEL				149
+#define CLK_TOP_PWRAP_ULPOSC_SEL			150
+#define CLK_TOP_ATB_SEL					151
+#define CLK_TOP_SSPM_SEL				152
+#define CLK_TOP_DISP_PWM_SEL				153
+#define CLK_TOP_USB_TOP_SEL				154
+#define CLK_TOP_SSUSB_XHCI_SEL				155
+#define CLK_TOP_I2C_SEL					156
+#define CLK_TOP_SENINF_SEL				157
+#define CLK_TOP_SENINF1_SEL				158
+#define CLK_TOP_SENINF2_SEL				159
+#define CLK_TOP_SENINF3_SEL				160
+#define CLK_TOP_DXCC_SEL				161
+#define CLK_TOP_AUD_ENGEN1_SEL				162
+#define CLK_TOP_AUD_ENGEN2_SEL				163
+#define CLK_TOP_AES_UFSFDE_SEL				164
+#define CLK_TOP_UFS_SEL					165
+#define CLK_TOP_AUD_1_SEL				166
+#define CLK_TOP_AUD_2_SEL				167
+#define CLK_TOP_ADSP_SEL				168
+#define CLK_TOP_DPMAIF_MAIN_SEL				169
+#define CLK_TOP_VENC_SEL				170
+#define CLK_TOP_VDEC_SEL				171
+#define CLK_TOP_CAMTM_SEL				172
+#define CLK_TOP_PWM_SEL					173
+#define CLK_TOP_AUDIO_H_SEL				174
+#define CLK_TOP_MCUPM_SEL				175
+#define CLK_TOP_SPMI_M_MST_SEL				176
+#define CLK_TOP_DVFSRC_SEL				177
+#define CLK_TOP_MEM_SUB_SEL				178
+#define CLK_TOP_AES_MSDCFDE_SEL				179
+#define CLK_TOP_UFS_MBIST_SEL				180
+#define CLK_TOP_MFG_INTERNAL2_SEL			181
+#define CLK_TOP_MFG_INTERNAL1_SEL			182
+#define CLK_TOP_AP2CONN_HOST_SEL			183
+#define CLK_TOP_MSDC_NEW_RX_SEL				184
+#define CLK_TOP_APLL_I2S0_MCK_SEL			185
+#define CLK_TOP_APLL_I2S1_MCK_SEL			186
+#define CLK_TOP_APLL_I2S2_MCK_SEL			187
+#define CLK_TOP_APLL_I2S3_MCK_SEL			188
+#define CLK_TOP_APLL_I2S4_MCK_SEL			189
+#define CLK_TOP_APLL_I2S5_MCK_SEL			190
+#define CLK_TOP_APLL_I2S6_MCK_SEL			191
+#define CLK_TOP_APLL_I2S7_MCK_SEL			192
+#define CLK_TOP_APLL_I2S8_MCK_SEL			193
+#define CLK_TOP_APLL_I2S9_MCK_SEL			194
+#define CLK_TOP_APLL12_CK_DIV0				195
+#define CLK_TOP_APLL12_CK_DIV1				196
+#define CLK_TOP_APLL12_CK_DIV2				197
+#define CLK_TOP_APLL12_CK_DIV3				198
+#define CLK_TOP_APLL12_CK_DIV4				199
+#define CLK_TOP_APLL12_CK_DIVB				200
+#define CLK_TOP_APLL12_CK_DIV5				201
+#define CLK_TOP_APLL12_CK_DIV6				202
+#define CLK_TOP_APLL12_CK_DIV7				203
+#define CLK_TOP_APLL12_CK_DIV8				204
+#define CLK_TOP_APLL12_CK_DIV9				205
+#define CLK_TOP_NR_CLK					206
+
+/* INFRACFG_AO */
+#define CLK_IFRAO_PMIC_TMR				0
+#define CLK_IFRAO_PMIC_AP				1
+#define CLK_IFRAO_PMIC_MD				2
+#define CLK_IFRAO_PMIC_CONN				3
+#define CLK_IFRAO_APXGPT				4
+#define CLK_IFRAO_GCE					5
+#define CLK_IFRAO_GCE2					6
+#define CLK_IFRAO_THERM					7
+#define CLK_IFRAO_I2C_PSEUDO				8
+#define CLK_IFRAO_PWM_HCLK				9
+#define CLK_IFRAO_PWM1					10
+#define CLK_IFRAO_PWM2					11
+#define CLK_IFRAO_PWM3					12
+#define CLK_IFRAO_PWM4					13
+#define CLK_IFRAO_PWM					14
+#define CLK_IFRAO_UART0					15
+#define CLK_IFRAO_UART1					16
+#define CLK_IFRAO_UART2					17
+#define CLK_IFRAO_UART3					18
+#define CLK_IFRAO_GCE_26M				19
+#define CLK_IFRAO_BTIF					20
+#define CLK_IFRAO_SPI0					21
+#define CLK_IFRAO_MSDC0					22
+#define CLK_IFRAO_MSDC1					23
+#define CLK_IFRAO_MSDC0_SRC				24
+#define CLK_IFRAO_AUXADC				25
+#define CLK_IFRAO_CPUM					26
+#define CLK_IFRAO_CCIF1_AP				27
+#define CLK_IFRAO_CCIF1_MD				28
+#define CLK_IFRAO_AUXADC_MD				29
+#define CLK_IFRAO_MSDC1_SRC				30
+#define CLK_IFRAO_MSDC0_AES				31
+#define CLK_IFRAO_DEVICE_APC				32
+#define CLK_IFRAO_CCIF_AP				33
+#define CLK_IFRAO_AUDIO					34
+#define CLK_IFRAO_CCIF_MD				35
+#define CLK_IFRAO_SSUSB					36
+#define CLK_IFRAO_DISP_PWM				37
+#define CLK_IFRAO_CLDMA_BCLK				38
+#define CLK_IFRAO_AUDIO_26M_BCLK			39
+#define CLK_IFRAO_SPI1					40
+#define CLK_IFRAO_SPI2					41
+#define CLK_IFRAO_SPI3					42
+#define CLK_IFRAO_UNIPRO_SYSCLK				43
+#define CLK_IFRAO_UFS_MP_SAP_BCLK			44
+#define CLK_IFRAO_APDMA					45
+#define CLK_IFRAO_SPI4					46
+#define CLK_IFRAO_SPI5					47
+#define CLK_IFRAO_CQ_DMA				48
+#define CLK_IFRAO_UFS					49
+#define CLK_IFRAO_AES_UFSFDE				50
+#define CLK_IFRAO_SSUSB_XHCI				51
+#define CLK_IFRAO_AP_MSDC0				52
+#define CLK_IFRAO_MD_MSDC0				53
+#define CLK_IFRAO_CCIF5_MD				54
+#define CLK_IFRAO_CCIF2_AP				55
+#define CLK_IFRAO_CCIF2_MD				56
+#define CLK_IFRAO_FBIST2FPC				57
+#define CLK_IFRAO_DPMAIF_MAIN				58
+#define CLK_IFRAO_CCIF4_MD				59
+#define CLK_IFRAO_SPI6_CK				60
+#define CLK_IFRAO_SPI7_CK				61
+#define CLK_IFRAO_RG_AES_CK_0P_CK			62
+#define CLK_IFRAO_NR_CLK				63
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL				0
+#define CLK_APMIXED_ARMPLL_BL				1
+#define CLK_APMIXED_CCIPLL				2
+#define CLK_APMIXED_MAINPLL				3
+#define CLK_APMIXED_UNIVPLL				4
+#define CLK_APMIXED_MSDCPLL				5
+#define CLK_APMIXED_MMPLL				6
+#define CLK_APMIXED_ADSPPLL				7
+#define CLK_APMIXED_TVDPLL				8
+#define CLK_APMIXED_APLL1				9
+#define CLK_APMIXED_APLL2				10
+#define CLK_APMIXED_MPLL				11
+#define CLK_APMIXED_USBPLL				12
+#define CLK_APMIXED_NR_CLK				13
+
+/* SCP_ADSP */
+#define CLK_SCP_PAR_RG_AUDIODSP				0
+#define CLK_SCP_PAR_NR_CLK				1
+
+/* AUDIOSYS */
+#define CLK_AUDSYS_AFE					0
+#define CLK_AUDSYS_22M					1
+#define CLK_AUDSYS_24M					2
+#define CLK_AUDSYS_APLL2_TUNER				3
+#define CLK_AUDSYS_APLL_TUNER				4
+#define CLK_AUDSYS_TDM					5
+#define CLK_AUDSYS_ADC					6
+#define CLK_AUDSYS_DAC					7
+#define CLK_AUDSYS_DAC_PREDIS				8
+#define CLK_AUDSYS_TML					9
+#define CLK_AUDSYS_NLE					10
+#define CLK_AUDSYS_CONNSYS_I2S_ASRC			11
+#define CLK_AUDSYS_GENERAL1_ASRC			12
+#define CLK_AUDSYS_GENERAL2_ASRC			13
+#define CLK_AUDSYS_DAC_HIRES				14
+#define CLK_AUDSYS_ADC_HIRES				15
+#define CLK_AUDSYS_ADC_HIRES_TML			16
+#define CLK_AUDSYS_ADDA6_ADC				17
+#define CLK_AUDSYS_ADDA6_ADC_HIRES			18
+#define CLK_AUDSYS_3RD_DAC				19
+#define CLK_AUDSYS_3RD_DAC_PREDIS			20
+#define CLK_AUDSYS_3RD_DAC_TML				21
+#define CLK_AUDSYS_3RD_DAC_HIRES			22
+#define CLK_AUDSYS_NR_CLK				23
+
+/* MSDC0SYS */
+#define CLK_MSDC0_MSDC_NEW_RX_PATH_SEL			0
+#define CLK_MSDC0_NR_CLK				1
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMPC_AP_CLOCK_I2C10				0
+#define CLK_IMPC_AP_CLOCK_I2C11				1
+#define CLK_IMPC_NR_CLK					2
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_AP_CLOCK_I2C3				0
+#define CLK_IMPE_NR_CLK					1
+
+/* IMP_IIC_WRAP_S */
+#define CLK_IMPS_AP_CLOCK_I2C5				0
+#define CLK_IMPS_AP_CLOCK_I2C7				1
+#define CLK_IMPS_AP_CLOCK_I2C8				2
+#define CLK_IMPS_AP_CLOCK_I2C9				3
+#define CLK_IMPS_NR_CLK					4
+
+/* IMP_IIC_WRAP_WS */
+#define CLK_IMPWS_AP_CLOCK_I2C1				0
+#define CLK_IMPWS_AP_CLOCK_I2C2				1
+#define CLK_IMPWS_AP_CLOCK_I2C4				2
+#define CLK_IMPWS_NR_CLK				3
+
+/* IMP_IIC_WRAP_W */
+#define CLK_IMPW_AP_CLOCK_I2C0				0
+#define CLK_IMPW_NR_CLK					1
+
+/* IMP_IIC_WRAP_N */
+#define CLK_IMPN_AP_CLOCK_I2C6				0
+#define CLK_IMPN_NR_CLK					1
+
+/* GPU_PLL_CTRL */
+#define CLK_MFG_AO_MFGPLL1				0
+#define CLK_MFG_AO_MFGPLL4				1
+#define CLK_MFG_AO_NR_CLK				2
+
+/* MFGCFG */
+#define CLK_MFGCFG_BG3D					0
+#define CLK_MFGCFG_NR_CLK				1
+
+/* MMSYS_CONFIG */
+#define CLK_MM_DISP_MUTEX0				0
+#define CLK_MM_APB_BUS					1
+#define CLK_MM_DISP_OVL0				2
+#define CLK_MM_DISP_RDMA0				3
+#define CLK_MM_DISP_OVL0_2L				4
+#define CLK_MM_DISP_WDMA0				5
+#define CLK_MM_DISP_CCORR1				6
+#define CLK_MM_DISP_RSZ0				7
+#define CLK_MM_DISP_AAL0				8
+#define CLK_MM_DISP_CCORR0				9
+#define CLK_MM_DISP_COLOR0				10
+#define CLK_MM_SMI_INFRA				11
+#define CLK_MM_DISP_GAMMA0				12
+#define CLK_MM_DISP_POSTMASK0				13
+#define CLK_MM_DISP_SPR0				14
+#define CLK_MM_DISP_DITHER0				15
+#define CLK_MM_SMI_COMMON				16
+#define CLK_MM_DISP_CM0					17
+#define CLK_MM_DSI0					18
+#define CLK_MM_SMI_GALS					19
+#define CLK_MM_DISP_DSC_WRAP				20
+#define CLK_MM_SMI_IOMMU				21
+#define CLK_MM_DISP_OVL1_2L				22
+#define CLK_MM_DISP_UFBC_WDMA0				23
+#define CLK_MM_DSI0_DSI_CK_DOMAIN			24
+#define CLK_MM_DISP_26M					25
+#define CLK_MM_NR_CLK					26
+
+/* IMGSYS1 */
+#define CLK_IMGSYS1_LARB9				0
+#define CLK_IMGSYS1_DIP					1
+#define CLK_IMGSYS1_GALS				2
+#define CLK_IMGSYS1_NR_CLK				3
+
+/* IMGSYS2 */
+#define CLK_IMGSYS2_LARB9				0
+#define CLK_IMGSYS2_LARB10				1
+#define CLK_IMGSYS2_MFB					2
+#define CLK_IMGSYS2_WPE					3
+#define CLK_IMGSYS2_MSS					4
+#define CLK_IMGSYS2_GALS				5
+#define CLK_IMGSYS2_NR_CLK				6
+
+/* VDEC_GCON */
+#define CLK_VDE2_VDEC_CKEN				0
+#define CLK_VDE2_NR_CLK					1
+
+/* VENC_GCON */
+#define CLK_VEN1_CKE0_LARB				0
+#define CLK_VEN1_CKE1_VENC				1
+#define CLK_VEN1_CKE2_JPGENC				2
+#define CLK_VEN1_CKE5_GALS				3
+#define CLK_VEN1_NR_CLK					4
+
+/* APU_CONN2 */
+#define CLK_APU_CONN2_AHB				0
+#define CLK_APU_CONN2_AXI				1
+#define CLK_APU_CONN2_ISP				2
+#define CLK_APU_CONN2_CAM_ADL				3
+#define CLK_APU_CONN2_IMG_ADL				4
+#define CLK_APU_CONN2_EMI_26M				5
+#define CLK_APU_CONN2_VPU_UDI				6
+#define CLK_APU_CONN2_EDMA_0				7
+#define CLK_APU_CONN2_EDMA_1				8
+#define CLK_APU_CONN2_EDMAL_0				9
+#define CLK_APU_CONN2_EDMAL_1				10
+#define CLK_APU_CONN2_MNOC				11
+#define CLK_APU_CONN2_TCM				12
+#define CLK_APU_CONN2_MD32				13
+#define CLK_APU_CONN2_IOMMU_0				14
+#define CLK_APU_CONN2_IOMMU_1				15
+#define CLK_APU_CONN2_MD32_32K				16
+#define CLK_APU_CONN2_CPE				17
+#define CLK_APU_CONN2_NR_CLK				18
+
+/* APU_CONN1 */
+#define CLK_APU_CONN1_AXI				0
+#define CLK_APU_CONN1_EDMA_0				1
+#define CLK_APU_CONN1_EDMA_1				2
+#define CLK_APU_CONN1_IOMMU_0				3
+#define CLK_APU_CONN1_IOMMU_1				4
+#define CLK_APU_CONN1_NR_CLK				5
+
+/* APU_VCORE */
+#define CLK_APUV_AHB					0
+#define CLK_APUV_AXI					1
+#define CLK_APUV_ADL					2
+#define CLK_APUV_QOS					3
+#define CLK_APUV_NR_CLK					4
+
+/* APU0 */
+#define CLK_APU0_APU					0
+#define CLK_APU0_AXI_M					1
+#define CLK_APU0_JTAG					2
+#define CLK_APU0_NR_CLK					3
+
+/* APU1 */
+#define CLK_APU1_APU					0
+#define CLK_APU1_AXI_M					1
+#define CLK_APU1_JTAG					2
+#define CLK_APU1_NR_CLK					3
+
+/* APU_MDLA0 */
+#define CLK_APUM0_MDLA_CG0				0
+#define CLK_APUM0_MDLA_CG1				1
+#define CLK_APUM0_MDLA_CG2				2
+#define CLK_APUM0_MDLA_CG3				3
+#define CLK_APUM0_MDLA_CG4				4
+#define CLK_APUM0_MDLA_CG5				5
+#define CLK_APUM0_MDLA_CG6				6
+#define CLK_APUM0_MDLA_CG7				7
+#define CLK_APUM0_MDLA_CG8				8
+#define CLK_APUM0_MDLA_CG9				9
+#define CLK_APUM0_MDLA_CG10				10
+#define CLK_APUM0_MDLA_CG11				11
+#define CLK_APUM0_MDLA_CG12				12
+#define CLK_APUM0_APB					13
+#define CLK_APUM0_AXI_M					14
+#define CLK_APUM0_NR_CLK				15
+
+/* APU_PLL_CTRL */
+#define CLK_APU_AO_APUPLL				0
+#define CLK_APU_AO_NPUPLL				1
+#define CLK_APU_AO_APUPLL1				2
+#define CLK_APU_AO_APUPLL2				3
+#define CLK_APU_AO_NR_CLK				4
+
+/* CAMSYS_MAIN */
+#define CLK_CAM_M_LARB13				0
+#define CLK_CAM_M_LARB14				1
+#define CLK_CAM_M_CAM					2
+#define CLK_CAM_M_CAMTG					3
+#define CLK_CAM_M_SENINF				4
+#define CLK_CAM_M_CAMSV0				5
+#define CLK_CAM_M_CAMSV1				6
+#define CLK_CAM_M_CAMSV2				7
+#define CLK_CAM_M_CAMSV3				8
+#define CLK_CAM_M_CCU0					9
+#define CLK_CAM_M_CCU1					10
+#define CLK_CAM_M_MRAW0					11
+#define CLK_CAM_M_CCU_GALS				12
+#define CLK_CAM_M_CAM2MM_GALS				13
+#define CLK_CAM_M_CAMSV4				14
+#define CLK_CAM_M_PDA					15
+#define CLK_CAM_M_NR_CLK				16
+
+/* CAMSYS_RAWA */
+#define CLK_CAM_RA_LARBX				0
+#define CLK_CAM_RA_CAM					1
+#define CLK_CAM_RA_CAMTG				2
+#define CLK_CAM_RA_NR_CLK				3
+
+/* CAMSYS_RAWB */
+#define CLK_CAM_RB_LARBX				0
+#define CLK_CAM_RB_CAM					1
+#define CLK_CAM_RB_CAMTG				2
+#define CLK_CAM_RB_NR_CLK				3
+
+/* IPESYS */
+#define CLK_IPE_LARB19					0
+#define CLK_IPE_LARB20					1
+#define CLK_IPE_SMI_SUBCOM				2
+#define CLK_IPE_FD					3
+#define CLK_IPE_FE					4
+#define CLK_IPE_RSC					5
+#define CLK_IPE_DPE					6
+#define CLK_IPE_GALS					7
+#define CLK_IPE_NR_CLK					8
+
+/* MDPSYS_CONFIG */
+#define CLK_MDP_RDMA0					0
+#define CLK_MDP_TDSHP0					1
+#define CLK_MDP_IMG_DL_ASYNC0				2
+#define CLK_MDP_IMG_DL_ASYNC1				3
+#define CLK_MDP_RDMA1					4
+#define CLK_MDP_TDSHP1					5
+#define CLK_MDP_SMI0					6
+#define CLK_MDP_APB_BUS					7
+#define CLK_MDP_WROT0					8
+#define CLK_MDP_RSZ0					9
+#define CLK_MDP_HDR0					10
+#define CLK_MDP_MUTEX0					11
+#define CLK_MDP_WROT1					12
+#define CLK_MDP_COLOR0					13
+#define CLK_MDP_AAL0					14
+#define CLK_MDP_AAL1					15
+#define CLK_MDP_RSZ1					16
+#define CLK_MDP_IMG_DL_RELAY0_ASYNC0			17
+#define CLK_MDP_IMG_DL_RELAY1_ASYNC1			18
+#define CLK_MDP_NR_CLK					19
+
+/* SCPSYS */
+#define SCP_SYS_MFG0					0
+#define SCP_SYS_MFG1					1
+#define SCP_SYS_MFG2					2
+#define SCP_SYS_MFG3					3
+#define SCP_SYS_MFG4					4
+#define SCP_SYS_MFG5					5
+#define SCP_SYS_MD					6
+#define SCP_SYS_CONN					7
+#define SCP_SYS_ISP0					8
+#define SCP_SYS_ISP1					9
+#define SCP_SYS_IPE					10
+#define SCP_SYS_VDEC					11
+#define SCP_SYS_VENC					12
+#define SCP_SYS_DISP					13
+#define SCP_SYS_AUDIO					14
+#define SCP_SYS_ADSP_DORMANT				15
+#define SCP_SYS_CAM					16
+#define SCP_SYS_CAM_RAWA				17
+#define SCP_SYS_CAM_RAWB				18
+#define SCP_SYS_CSI					19
+#define SCP_SYS_APU					20
+#define SCP_NR_SYSS					21
+
+#endif /* _DT_BINDINGS_CLK_MT6877_H */

include/dt-bindings/clock/mt6885-clk.h

@@ -0,0 +1,794 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6893_H
+#define _DT_BINDINGS_CLK_MT6893_H
+
+/* TOPCKGEN */
+#define CLK_TOP_ARMPLL_BL0_CK_VRPOC	0
+#define CLK_TOP_ARMPLL_BL1_CK_VRPOC	1
+#define CLK_TOP_ARMPLL_BL2_CK_VRPOC	2
+#define CLK_TOP_ARMPLL_BL3_CK_VRPOC	3
+#define CLK_TOP_ARMPLL_LL_CK_VRPOC	4
+#define CLK_TOP_CCIPLL_CK_VRPOC_CCI	5
+#define CLK_TOP_MFGPLL			6
+#define CLK_TOP_MAINPLL			7
+#define CLK_TOP_MAINPLL_D3		8
+#define CLK_TOP_MAINPLL_D4		9
+#define CLK_TOP_MAINPLL_D4_D2		10
+#define CLK_TOP_MAINPLL_D4_D4		11
+#define CLK_TOP_MAINPLL_D4_D8		12
+#define CLK_TOP_MAINPLL_D4_D16		13
+#define CLK_TOP_MAINPLL_D5		14
+#define CLK_TOP_MAINPLL_D5_D2		15
+#define CLK_TOP_MAINPLL_D5_D4		16
+#define CLK_TOP_MAINPLL_D5_D8		17
+#define CLK_TOP_MAINPLL_D6		18
+#define CLK_TOP_MAINPLL_D6_D2		19
+#define CLK_TOP_MAINPLL_D6_D4		20
+#define CLK_TOP_MAINPLL_D6_D8		21
+#define CLK_TOP_MAINPLL_D7		22
+#define CLK_TOP_MAINPLL_D7_D2		23
+#define CLK_TOP_MAINPLL_D7_D4		24
+#define CLK_TOP_MAINPLL_D7_D8		25
+#define CLK_TOP_MAINPLL_D9		26
+#define CLK_TOP_UNIVPLL			27
+#define CLK_TOP_UNIVPLL_D2		28
+#define CLK_TOP_UNIVPLL_D3		29
+#define CLK_TOP_UNIVPLL_D4		30
+#define CLK_TOP_UNIVPLL_D4_D2		31
+#define CLK_TOP_UNIVPLL_D4_D4		32
+#define CLK_TOP_UNIVPLL_D4_D8		33
+#define CLK_TOP_UNIVPLL_D5		34
+#define CLK_TOP_UNIVPLL_D5_D2		35
+#define CLK_TOP_UNIVPLL_D5_D4		36
+#define CLK_TOP_UNIVPLL_D5_D8		37
+#define CLK_TOP_UNIVPLL_D5_D16		38
+#define CLK_TOP_UNIVPLL_D6		39
+#define CLK_TOP_UNIVPLL_D6_D2		40
+#define CLK_TOP_UNIVPLL_D6_D4		41
+#define CLK_TOP_UNIVPLL_D6_D8		42
+#define CLK_TOP_UNIVPLL_D6_D16		43
+#define CLK_TOP_UNIVPLL_D7		44
+#define CLK_TOP_UNIVPLL_D7_D2		45
+#define CLK_TOP_UNIVPLL_192M_D2		46
+#define CLK_TOP_UNIVPLL_192M_D4		47
+#define CLK_TOP_UNIVPLL_192M_D8		48
+#define CLK_TOP_UNIVPLL_192M_D16	49
+#define CLK_TOP_UNIVPLL_192M_D32	50
+#define CLK_TOP_USB20_192M		51
+#define CLK_TOP_USB20_PLL_D2		52
+#define CLK_TOP_USB20_PLL_D4		53
+#define CLK_TOP_MPLL_208M		54
+#define CLK_TOP_MPLL_D2			55
+#define CLK_TOP_MPLL_D4			56
+#define CLK_TOP_APLL1			57
+#define CLK_TOP_APLL1_D2		58
+#define CLK_TOP_APLL1_D4		59
+#define CLK_TOP_APLL1_D8		60
+#define CLK_TOP_APLL2			61
+#define CLK_TOP_APLL2_D2		62
+#define CLK_TOP_APLL2_D4		63
+#define CLK_TOP_APLL2_D8		64
+#define CLK_TOP_CLK26M_BYP		65
+#define CLK_TOP_ADSPPLL			66
+#define CLK_TOP_ADSPPLL_D4		67
+#define CLK_TOP_ADSPPLL_D5		68
+#define CLK_TOP_ADSPPLL_D6		69
+#define CLK_TOP_MMPLL			70
+#define CLK_TOP_MMPLL_D3		71
+#define CLK_TOP_MMPLL_D4		72
+#define CLK_TOP_MMPLL_D4_D2		73
+#define CLK_TOP_MMPLL_D4_D4		74
+#define CLK_TOP_MMPLL_D5		75
+#define CLK_TOP_MMPLL_D5_D2		76
+#define CLK_TOP_MMPLL_D5_D4		77
+#define CLK_TOP_MMPLL_D6		78
+#define CLK_TOP_MMPLL_D6_D2		79
+#define CLK_TOP_MMPLL_D7		80
+#define CLK_TOP_MMPLL_D9		81
+#define CLK_TOP_APUPLL			82
+#define CLK_TOP_TVDPLL			83
+#define CLK_TOP_TVDPLL_D2		84
+#define CLK_TOP_TVDPLL_D4		85
+#define CLK_TOP_TVDPLL_D8		86
+#define CLK_TOP_TVDPLL_D16		87
+#define CLK_TOP_MSDCPLL			88
+#define CLK_TOP_MSDCPLL_D2		89
+#define CLK_TOP_MSDCPLL_D4		90
+#define CLK_TOP_MSDCPLL_D8		91
+#define CLK_TOP_MSDCPLL_D16		92
+#define CLK_TOP_MIPI_26M		93
+#define CLK_TOP_MEM_26M			94
+#define CLK_TOP_ARMPLL_26M		95
+#define CLK_TOP_SSUBS_26M		96
+#define CLK_TOP_PLLGP_TST		97
+#define CLK_TOP_CLKRTC			98
+#define CLK_TOP_TCK_26M_MX8		99
+#define CLK_TOP_TCK_26M_MX9		100
+#define CLK_TOP_TCK_26M_MX10		101
+#define CLK_TOP_TCK_26M_MX11		102
+#define CLK_TOP_TCK_26M_MX12		103
+#define CLK_TOP_CSW_FAXI		104
+#define CLK_TOP_F26M_CK_D52		105
+#define CLK_TOP_F26M_CK_D2		106
+#define CLK_TOP_OSC			107
+#define CLK_TOP_OSC_D2			108
+#define CLK_TOP_OSC_D4			109
+#define CLK_TOP_OSC_D8			110
+#define CLK_TOP_OSC_D16			111
+#define CLK_TOP_OSC_D10			112
+#define CLK_TOP_OSC_D20			113
+#define CLK_TOP_TVDPLL_MAINPLL_D2	114
+#define CLK_TOP_F26M			115
+#define CLK_TOP_FRTC			116
+#define CLK_TOP_AXI			117
+#define CLK_TOP_SPM			118
+#define CLK_TOP_SCP			119
+#define CLK_TOP_BUS			120
+#define CLK_TOP_DISP			121
+#define CLK_TOP_MDP			122
+#define CLK_TOP_IMG1			123
+#define CLK_TOP_IMG2			124
+#define CLK_TOP_IPE			125
+#define CLK_TOP_DPE			126
+#define CLK_TOP_CAM			127
+#define CLK_TOP_CCU			128
+#define CLK_TOP_DSP			129
+#define CLK_TOP_DSP1			130
+#define CLK_TOP_DSP2			131
+#define CLK_TOP_DSP3			132
+#define CLK_TOP_DSP4			133
+#define CLK_TOP_DSP5			134
+#define CLK_TOP_DSP6			135
+#define CLK_TOP_DSP7			136
+#define CLK_TOP_IPU_IF			137
+#define CLK_TOP_MFG_REF			138
+#define CLK_TOP_FCAMTG			139
+#define CLK_TOP_FCAMTG2			140
+#define CLK_TOP_FCAMTG3			141
+#define CLK_TOP_FCAMTG4			142
+#define CLK_TOP_FUART			143
+#define CLK_TOP_SPI			144
+#define CLK_TOP_MSDC50_0_HCLK		145
+#define CLK_TOP_MSDC50_0		146
+#define CLK_TOP_MSDC30_1		147
+#define CLK_TOP_AUDIO			148
+#define CLK_TOP_AUD_INTBUS		149
+#define CLK_TOP_FPWRAP_ULPOSC		150
+#define CLK_TOP_ATB			151
+#define CLK_TOP_SSPM			152
+#define CLK_TOP_DP			153
+#define CLK_TOP_SCAM			154
+#define CLK_TOP_FDISP_PWM		155
+#define CLK_TOP_FUSB_TOP		156
+#define CLK_TOP_FSSUSB_XHCI		157
+#define CLK_TOP_I2C			158
+#define CLK_TOP_FSENINF			159
+#define CLK_TOP_FSENINF1		160
+#define CLK_TOP_FSENINF2		161
+#define CLK_TOP_FSENINF3		162
+#define CLK_TOP_DXCC			163
+#define CLK_TOP_AUD_ENGEN1		164
+#define CLK_TOP_AUD_ENGEN2		165
+#define CLK_TOP_AES_UFSFDE		166
+#define CLK_TOP_UFS			167
+#define CLK_TOP_AUD_1			168
+#define CLK_TOP_AUD_2			169
+#define CLK_TOP_ADSP			170
+#define CLK_TOP_DPMAIF_MAIN		171
+#define CLK_TOP_VENC			172
+#define CLK_TOP_VDEC			173
+#define CLK_TOP_VDEC_LAT		174
+#define CLK_TOP_CAMTM			175
+#define CLK_TOP_PWM			176
+#define CLK_TOP_AUDIO_H			177
+#define CLK_TOP_FCAMTG5			178
+#define CLK_TOP_FCAMTG6			179
+#define CLK_TOP_MCUPM			180
+#define CLK_TOP_SPMI_MST		181
+#define CLK_TOP_DVFSRC			182
+#define CLK_TOP_SRCK			183
+#define CLK_TOP_SYS_26M			184
+#define CLK_TOP_F_UFS_MP_SAP_CFG	185
+#define CLK_TOP_F_UFS_TICK1US		186
+#define CLK_TOP_I2C_PSEUDO		187
+#define CLK_TOP_APDMA_PSEUDO		188
+#define CLK_TOP_AXI_SEL			189
+#define CLK_TOP_SPM_SEL			190
+#define CLK_TOP_SCP_SEL			191
+#define CLK_TOP_BUS_AXIMEM_SEL		192
+#define CLK_TOP_DISP_SEL		193
+#define CLK_TOP_MDP_SEL			194
+#define CLK_TOP_IMG1_SEL		195
+#define CLK_TOP_IMG2_SEL		196
+#define CLK_TOP_IPE_SEL			197
+#define CLK_TOP_DPE_SEL			198
+#define CLK_TOP_CAM_SEL			199
+#define CLK_TOP_CCU_SEL			200
+#define CLK_TOP_DSP_SEL			201
+#define CLK_TOP_DSP1_SEL		202
+#define CLK_TOP_DSP2_SEL		203
+#define CLK_TOP_DSP3_SEL		204
+#define CLK_TOP_DSP4_SEL		205
+#define CLK_TOP_DSP5_SEL		206
+#define CLK_TOP_DSP6_SEL		207
+#define CLK_TOP_DSP7_SEL		208
+#define CLK_TOP_IPU_IF_SEL		209
+#define CLK_TOP_MFG_SEL			210
+#define CLK_TOP_CAMTG_SEL		211
+#define CLK_TOP_CAMTG2_SEL		212
+#define CLK_TOP_CAMTG3_SEL		213
+#define CLK_TOP_CAMTG4_SEL		214
+#define CLK_TOP_UART_SEL		215
+#define CLK_TOP_SPI_SEL			216
+#define CLK_TOP_MSDC50_0_HCLK_SEL	217
+#define CLK_TOP_MSDC50_0_SEL		218
+#define CLK_TOP_MSDC30_1_SEL		219
+#define CLK_TOP_AUDIO_SEL		220
+#define CLK_TOP_AUD_INTBUS_SEL		221
+#define CLK_TOP_PWRAP_ULPOSC_SEL	222
+#define CLK_TOP_ATB_SEL			223
+#define CLK_TOP_SSPM_SEL		224
+#define CLK_TOP_DP_SEL			225
+#define CLK_TOP_SCAM_SEL		226
+#define CLK_TOP_DISP_PWM_SEL		227
+#define CLK_TOP_USB_TOP_SEL		228
+#define CLK_TOP_SSUSB_XHCI_SEL		229
+#define CLK_TOP_I2C_SEL			230
+#define CLK_TOP_SENINF_SEL		231
+#define CLK_TOP_SENINF1_SEL		232
+#define CLK_TOP_SENINF2_SEL		233
+#define CLK_TOP_SENINF3_SEL		234
+#define CLK_TOP_DXCC_SEL		235
+#define CLK_TOP_AUD_ENGEN1_SEL		236
+#define CLK_TOP_AUD_ENGEN2_SEL		237
+#define CLK_TOP_AES_UFSFDE_SEL		238
+#define CLK_TOP_UFS_SEL			239
+#define CLK_TOP_AUD_1_SEL		240
+#define CLK_TOP_AUD_2_SEL		241
+#define CLK_TOP_ADSP_SEL		242
+#define CLK_TOP_DPMAIF_MAIN_SEL		243
+#define CLK_TOP_VENC_SEL		244
+#define CLK_TOP_VDEC_SEL		245
+#define CLK_TOP_VDEC_LAT_SEL		246
+#define CLK_TOP_CAMTM_SEL		247
+#define CLK_TOP_PWM_SEL			248
+#define CLK_TOP_AUDIO_H_SEL		249
+#define CLK_TOP_CAMTG5_SEL		250
+#define CLK_TOP_CAMTG6_SEL		251
+#define CLK_TOP_MCUPM_SEL		252
+#define CLK_TOP_SPMI_MST_SEL		253
+#define CLK_TOP_DVFSRC_SEL		254
+#define CLK_TOP_APLL_I2S0_MCK_SEL	255
+#define CLK_TOP_APLL_I2S1_MCK_SEL	256
+#define CLK_TOP_APLL_I2S2_MCK_SEL	257
+#define CLK_TOP_APLL_I2S3_MCK_SEL	258
+#define CLK_TOP_APLL_I2S4_MCK_SEL	259
+#define CLK_TOP_APLL_I2S5_MCK_SEL	260
+#define CLK_TOP_APLL_I2S6_MCK_SEL	261
+#define CLK_TOP_APLL_I2S7_MCK_SEL	262
+#define CLK_TOP_APLL_I2S8_MCK_SEL	263
+#define CLK_TOP_APLL_I2S9_MCK_SEL	264
+#define CLK_TOP_APLL1_CK_DIV0		265
+#define CLK_TOP_APLL2_CK_DIV0		266
+#define CLK_TOP_APLL12_CK_DIV0		267
+#define CLK_TOP_APLL12_CK_DIV1		268
+#define CLK_TOP_APLL12_CK_DIV2		269
+#define CLK_TOP_APLL12_CK_DIV3		270
+#define CLK_TOP_APLL12_CK_DIV4		271
+#define CLK_TOP_APLL12_CK_DIVB		272
+#define CLK_TOP_APLL12_CK_DIV5_LSB	273
+#define CLK_TOP_APLL12_CK_DIV5_MSB	274
+#define CLK_TOP_APLL12_CK_DIV6		275
+#define CLK_TOP_APLL12_CK_DIV7		276
+#define CLK_TOP_APLL12_CK_DIV8		277
+#define CLK_TOP_APLL12_CK_DIV9		278
+#define CLK_TOP_NR_CLK			279
+
+/* INFRACFG_AO */
+#define CLK_IFRAO_PMIC_TMR		0
+#define CLK_IFRAO_PMIC_AP		1
+#define CLK_IFRAO_GCE			2
+#define CLK_IFRAO_GCE2			3
+#define CLK_IFRAO_THERM			4
+#define CLK_IFRAO_I2C0			5
+#define CLK_IFRAO_I2C1			6
+#define CLK_IFRAO_I2C2			7
+#define CLK_IFRAO_I2C3			8
+#define CLK_IFRAO_PWM_HCLK		9
+#define CLK_IFRAO_PWM1			10
+#define CLK_IFRAO_PWM2			11
+#define CLK_IFRAO_PWM3			12
+#define CLK_IFRAO_PWM4			13
+#define CLK_IFRAO_PWM			14
+#define CLK_IFRAO_UART0			15
+#define CLK_IFRAO_UART1			16
+#define CLK_IFRAO_UART2			17
+#define CLK_IFRAO_UART3			18
+#define CLK_IFRAO_GCE_26M		19
+#define CLK_IFRAO_CQ_DMA_FPC		20
+#define CLK_IFRAO_BTIF			21
+#define CLK_IFRAO_SPI0			22
+#define CLK_IFRAO_MSDC0			23
+#define CLK_IFRAO_MSDC1			24
+#define CLK_IFRAO_MSDC0_SRC		25
+#define CLK_IFRAO_AUXADC		26
+#define CLK_IFRAO_CPUM			27
+#define CLK_IFRAO_CCIF1_AP		28
+#define CLK_IFRAO_CCIF1_MD		29
+#define CLK_IFRAO_MSDC1_SRC		30
+#define CLK_IFRAO_AP_DMA_PS		31
+#define CLK_IFRAO_DEVICE_APC		32
+#define CLK_IFRAO_CCIF_AP		33
+#define CLK_IFRAO_AUDIO			34
+#define CLK_IFRAO_CCIF_MD		35
+#define CLK_IFRAO_DXCC_SEC_CORE		36
+#define CLK_IFRAO_SSUSB			37
+#define CLK_IFRAO_DISP_PWM		38
+#define CLK_IFRAO_DPMAIF		39
+#define CLK_IFRAO_AUDIO_26M_BCLK	40
+#define CLK_IFRAO_SPI1			41
+#define CLK_IFRAO_I2C4			42
+#define CLK_IFRAO_SPI2			43
+#define CLK_IFRAO_SPI3			44
+#define CLK_IFRAO_UNIPRO_SYSCLK		45
+#define CLK_IFRAO_UFS_MP_SAP_BCLK	46
+#define CLK_IFRAO_I2C5			47
+#define CLK_IFRAO_I2C5_ARBITER		48
+#define CLK_IFRAO_I2C5_IMM		49
+#define CLK_IFRAO_I2C1_ARBITER		50
+#define CLK_IFRAO_I2C1_IMM		51
+#define CLK_IFRAO_I2C2_ARBITER		52
+#define CLK_IFRAO_I2C2_IMM		53
+#define CLK_IFRAO_SPI4			54
+#define CLK_IFRAO_SPI5			55
+#define CLK_IFRAO_CQ_DMA		56
+#define CLK_IFRAO_UFS			57
+#define CLK_IFRAO_AES			58
+#define CLK_IFRAO_SSUSB_XHCI		59
+#define CLK_IFRAO_MSDC0_SELF		60
+#define CLK_IFRAO_MSDC1_SELF		61
+#define CLK_IFRAO_MSDC2_SELF		62
+#define CLK_IFRAO_I2C6			63
+#define CLK_IFRAO_AP_MSDC0		64
+#define CLK_IFRAO_MD_MSDC0		65
+#define CLK_IFRAO_CCIF5_AP		66
+#define CLK_IFRAO_CCIF5_MD		67
+#define CLK_IFRAO_CCIF2_AP		68
+#define CLK_IFRAO_CCIF2_MD		69
+#define CLK_IFRAO_I2C7			70
+#define CLK_IFRAO_I2C8			71
+#define CLK_IFRAO_FBIST2FPC		72
+#define CLK_IFRAO_DEVICE_APC_SYNC	73
+#define CLK_IFRAO_DPMAIF_MAIN		74
+#define CLK_IFRAO_CCIF4_AP		75
+#define CLK_IFRAO_CCIF4_MD		76
+#define CLK_IFRAO_SPI6_CK		77
+#define CLK_IFRAO_SPI7_CK		78
+#define CLK_IFRAO_APDMA			79
+#define CLK_IFRAO_NR_CLK		80
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL		0
+#define CLK_APMIXED_ARMPLL_BL0		1
+#define CLK_APMIXED_ARMPLL_BL1		2
+#define CLK_APMIXED_ARMPLL_BL2		3
+#define CLK_APMIXED_ARMPLL_BL3		4
+#define CLK_APMIXED_CCIPLL		5
+#define CLK_APMIXED_MAINPLL		6
+#define CLK_APMIXED_UNIVPLL		7
+#define CLK_APMIXED_MSDCPLL		8
+#define CLK_APMIXED_MMPLL		9
+#define CLK_APMIXED_ADSPPLL		10
+#define CLK_APMIXED_MFGPLL		11
+#define CLK_APMIXED_TVDPLL		12
+#define CLK_APMIXED_APLL1		13
+#define CLK_APMIXED_APLL2		14
+#define CLK_APMIXED_MPLL		15
+#define CLK_APMIXED_APUPLL		16
+#define CLK_APMIXED_NR_CLK		17
+
+/* SCP_ADSP */
+#define CLK_SCP_ADSP_RG_AUDIODSP	0
+#define CLK_SCP_ADSP_NR_CLK		1
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMPC_AP_I2C0_RO		0
+#define CLK_IMPC_AP_I2C10_RO		1
+#define CLK_IMPC_AP_I2C11_RO		2
+#define CLK_IMPC_AP_I2C12_RO		3
+#define CLK_IMPC_AP_I2C13_RO		4
+#define CLK_IMPC_NR_CLK			5
+
+/* AUDIOSYS */
+#define CLK_AUDSYS_AFE			0
+#define CLK_AUDSYS_22M			1
+#define CLK_AUDSYS_24M			2
+#define CLK_AUDSYS_APLL2_TUNER		3
+#define CLK_AUDSYS_APLL_TUNER		4
+#define CLK_AUDSYS_TDM			5
+#define CLK_AUDSYS_ADC			6
+#define CLK_AUDSYS_DAC			7
+#define CLK_AUDSYS_DAC_PREDIS		8
+#define CLK_AUDSYS_TML			9
+#define CLK_AUDSYS_NLE			10
+#define CLK_AUDSYS_I2S1_BCLK		11
+#define CLK_AUDSYS_I2S2_BCLK		12
+#define CLK_AUDSYS_I2S3_BCLK		13
+#define CLK_AUDSYS_I2S4_BCLK		14
+#define CLK_AUDSYS_CONNSYS_I2S_ASRC	15
+#define CLK_AUDSYS_GENERAL1_ASRC	16
+#define CLK_AUDSYS_GENERAL2_ASRC	17
+#define CLK_AUDSYS_DAC_HIRES		18
+#define CLK_AUDSYS_ADC_HIRES		19
+#define CLK_AUDSYS_ADC_HIRES_TML	20
+#define CLK_AUDSYS_ADDA6_ADC		21
+#define CLK_AUDSYS_ADDA6_ADC_HIRES	22
+#define CLK_AUDSYS_3RD_DAC		23
+#define CLK_AUDSYS_3RD_DAC_PREDIS	24
+#define CLK_AUDSYS_3RD_DAC_TML		25
+#define CLK_AUDSYS_3RD_DAC_HIRES	26
+#define CLK_AUDSYS_I2S5_BCLK		27
+#define CLK_AUDSYS_I2S6_BCLK		28
+#define CLK_AUDSYS_I2S7_BCLK		29
+#define CLK_AUDSYS_I2S8_BCLK		30
+#define CLK_AUDSYS_I2S9_BCLK		31
+#define CLK_AUDSYS_NR_CLK		32
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_AP_I2C3_RO		0
+#define CLK_IMPE_AP_I2C9_RO		1
+#define CLK_IMPE_NR_CLK			2
+
+/* IMP_IIC_WRAP_S */
+#define CLK_IMPS_AP_I2C1_RO		0
+#define CLK_IMPS_AP_I2C2_RO		1
+#define CLK_IMPS_AP_I2C4_RO		2
+#define CLK_IMPS_AP_I2C7_RO		3
+#define CLK_IMPS_AP_I2C8_RO		4
+#define CLK_IMPS_NR_CLK			5
+
+/* IMP_IIC_WRAP_N */
+#define CLK_IMPN_AP_I2C5_RO		0
+#define CLK_IMPN_AP_I2C6_RO		1
+#define CLK_IMPN_NR_CLK			2
+
+/* MFGCFG */
+#define CLK_MFGCFG_BG3D			0
+#define CLK_MFGCFG_NR_CLK		1
+
+/* MMSYS_CONFIG */
+#define CLK_MM_DISP_RSZ0		0
+#define CLK_MM_DISP_RSZ1		1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_INLINE			3
+#define CLK_MM_MDP_TDSHP4		4
+#define CLK_MM_MDP_TDSHP5		5
+#define CLK_MM_MDP_AAL4			6
+#define CLK_MM_MDP_AAL5			7
+#define CLK_MM_MDP_HDR4			8
+#define CLK_MM_MDP_HDR5			9
+#define CLK_MM_MDP_RSZ4			10
+#define CLK_MM_MDP_RSZ5			11
+#define CLK_MM_MDP_RDMA4		12
+#define CLK_MM_MDP_RDMA5		13
+#define CLK_MM_DISP_FAKE_ENG0		14
+#define CLK_MM_DISP_FAKE_ENG1		15
+#define CLK_MM_DISP_OVL0_2L		16
+#define CLK_MM_DISP_OVL1_2L		17
+#define CLK_MM_DISP_OVL2_2L		18
+#define CLK_MM_DISP_MUTEX		19
+#define CLK_MM_DISP_OVL1		20
+#define CLK_MM_DISP_OVL3_2L		21
+#define CLK_MM_DISP_CCORR0		22
+#define CLK_MM_DISP_CCORR1		23
+#define CLK_MM_DISP_COLOR0		24
+#define CLK_MM_DISP_COLOR1		25
+#define CLK_MM_DISP_POSTMASK0		26
+#define CLK_MM_DISP_POSTMASK1		27
+#define CLK_MM_DISP_DITHER0		28
+#define CLK_MM_DISP_DITHER1		29
+#define CLK_MM_DSI0_MM_CLK		30
+#define CLK_MM_DSI1_MM_CLK		31
+#define CLK_MM_DISP_GAMMA0		32
+#define CLK_MM_DISP_GAMMA1		33
+#define CLK_MM_DISP_AAL0		34
+#define CLK_MM_DISP_AAL1		35
+#define CLK_MM_DISP_WDMA0		36
+#define CLK_MM_DISP_WDMA1		37
+#define CLK_MM_DISP_UFBC_WDMA0		38
+#define CLK_MM_DISP_UFBC_WDMA1		39
+#define CLK_MM_DISP_RDMA0		40
+#define CLK_MM_DISP_RDMA1		41
+#define CLK_MM_DISP_RDMA4		42
+#define CLK_MM_DISP_RDMA5		43
+#define CLK_MM_DISP_DSC_WRAP		44
+#define CLK_MM_DP_INTF_MM_CLK		45
+#define CLK_MM_DISP_MERGE0		46
+#define CLK_MM_DISP_MERGE1		47
+#define CLK_MM_SMI_COMMON		48
+#define CLK_MM_SMI_GALS			49
+#define CLK_MM_SMI_INFRA		50
+#define CLK_MM_SMI_IOMMU		51
+#define CLK_MM_DSI0_INTF_CLK		52
+#define CLK_MM_DSI1_INTF_CLK		53
+#define CLK_MM_DP_INTF_INTF_CLK		54
+#define CLK_MM_CK_26_MHZ		55
+#define CLK_MM_CK_32_KHZ		56
+#define CLK_MM_NR_CLK			57
+
+/* IMGSYS1 */
+#define CLK_IMGSYS1_LARB9		0
+#define CLK_IMGSYS1_LARB10		1
+#define CLK_IMGSYS1_DIP			2
+#define CLK_IMGSYS1_MFB			3
+#define CLK_IMGSYS1_WPE			4
+#define CLK_IMGSYS1_MSS			5
+#define CLK_IMGSYS1_NR_CLK		6
+
+/* IMGSYS2 */
+#define CLK_IMGSYS2_LARB11		0
+#define CLK_IMGSYS2_LARB12		1
+#define CLK_IMGSYS2_DIP			2
+#define CLK_IMGSYS2_WPE			3
+#define CLK_IMGSYS2_NR_CLK		4
+
+/* VDEC_SOC_GCON */
+#define CLK_VDE1_LARB1_CKEN		0
+#define CLK_VDE1_LAT_CKEN		1
+#define CLK_VDE1_LAT_ACTIVE		2
+#define CLK_VDE1_LAT_CKEN_ENG		3
+#define CLK_VDE1_VDEC_CKEN		4
+#define CLK_VDE1_VDEC_ACTIVE		5
+#define CLK_VDE1_VDEC_CKEN_ENG		6
+#define CLK_VDE1_NR_CLK			7
+
+/* VDEC_GCON */
+#define CLK_VDE2_LARB1_CKEN		0
+#define CLK_VDE2_LAT_CKEN		1
+#define CLK_VDE2_LAT_ACTIVE		2
+#define CLK_VDE2_LAT_CKEN_ENG		3
+#define CLK_VDE2_VDEC_CKEN		4
+#define CLK_VDE2_VDEC_ACTIVE		5
+#define CLK_VDE2_VDEC_CKEN_ENG		6
+#define CLK_VDE2_NR_CLK			7
+
+/* VENC_GCON */
+#define CLK_VEN1_CKE0_LARB		0
+#define CLK_VEN1_CKE1_VENC		1
+#define CLK_VEN1_CKE2_JPGENC		2
+#define CLK_VEN1_CKE3_JPGDEC		3
+#define CLK_VEN1_CKE4_JPGDEC_C1		4
+#define CLK_VEN1_CKE5_GALS		5
+#define CLK_VEN1_NR_CLK			6
+
+/* VENC_C1_GCON */
+#define CLK_VEN2_CKE0_LARB		0
+#define CLK_VEN2_CKE1_VENC		1
+#define CLK_VEN2_CKE2_JPGENC		2
+#define CLK_VEN2_CKE3_JPGDEC		3
+#define CLK_VEN2_CKE4_JPGDEC_C1		4
+#define CLK_VEN2_CKE5_GALS		5
+#define CLK_VEN2_NR_CLK			6
+
+/* APU_CONN */
+#define CLK_APUC_AHB			0
+#define CLK_APUC_AXI			1
+#define CLK_APUC_ISP			2
+#define CLK_APUC_CAM_ADL		3
+#define CLK_APUC_IMG_ADL		4
+#define CLK_APUC_EMI_26M		5
+#define CLK_APUC_VPU_UDI		6
+#define CLK_APUC_EDMA_0			7
+#define CLK_APUC_EDMA_1			8
+#define CLK_APUC_EDMAL_0		9
+#define CLK_APUC_EDMAL_1		10
+#define CLK_APUC_MNOC			11
+#define CLK_APUC_TCM			12
+#define CLK_APUC_MD32			13
+#define CLK_APUC_IOMMU_0		14
+#define CLK_APUC_IOMMU_1		15
+#define CLK_APUC_MD32_32K		16
+#define CLK_APUC_NR_CLK			17
+
+/* APU_VCORE */
+#define CLK_APUV_AHB			0
+#define CLK_APUV_AXI			1
+#define CLK_APUV_ADL			2
+#define CLK_APUV_QOS			3
+#define CLK_APUV_NR_CLK			4
+
+/* APU0 */
+#define CLK_APU0_APU			0
+#define CLK_APU0_AXI_M			1
+#define CLK_APU0_JTAG			2
+#define CLK_APU0_NR_CLK			3
+
+/* APU1 */
+#define CLK_APU1_APU			0
+#define CLK_APU1_AXI_M			1
+#define CLK_APU1_JTAG			2
+#define CLK_APU1_NR_CLK			3
+
+/* APU2 */
+#define CLK_APU2_APU			0
+#define CLK_APU2_AXI_M			1
+#define CLK_APU2_JTAG			2
+#define CLK_APU2_NR_CLK			3
+
+/* APU_MDLA0 */
+#define CLK_APUM0_MDLA_CG0		0
+#define CLK_APUM0_MDLA_CG1		1
+#define CLK_APUM0_MDLA_CG2		2
+#define CLK_APUM0_MDLA_CG3		3
+#define CLK_APUM0_MDLA_CG4		4
+#define CLK_APUM0_MDLA_CG5		5
+#define CLK_APUM0_MDLA_CG6		6
+#define CLK_APUM0_MDLA_CG7		7
+#define CLK_APUM0_MDLA_CG8		8
+#define CLK_APUM0_MDLA_CG9		9
+#define CLK_APUM0_MDLA_CG10		10
+#define CLK_APUM0_MDLA_CG11		11
+#define CLK_APUM0_MDLA_CG12		12
+#define CLK_APUM0_APB			13
+#define CLK_APUM0_AXI_M			14
+#define CLK_APUM0_NR_CLK		15
+
+/* APU_MDLA1 */
+#define CLK_APUM1_MDLA_CG0		0
+#define CLK_APUM1_MDLA_CG1		1
+#define CLK_APUM1_MDLA_CG2		2
+#define CLK_APUM1_MDLA_CG3		3
+#define CLK_APUM1_MDLA_CG4		4
+#define CLK_APUM1_MDLA_CG5		5
+#define CLK_APUM1_MDLA_CG6		6
+#define CLK_APUM1_MDLA_CG7		7
+#define CLK_APUM1_MDLA_CG8		8
+#define CLK_APUM1_MDLA_CG9		9
+#define CLK_APUM1_MDLA_CG10		10
+#define CLK_APUM1_MDLA_CG11		11
+#define CLK_APUM1_MDLA_CG12		12
+#define CLK_APUM1_APB			13
+#define CLK_APUM1_AXI_M			14
+#define CLK_APUM1_NR_CLK		15
+
+/* CAMSYS_MAIN */
+#define CLK_CAM_M_LARB13		0
+#define CLK_CAM_M_DFP_VAD		1
+#define CLK_CAM_M_LARB14		2
+#define CLK_CAM_M_LARB15		3
+#define CLK_CAM_M_CAM			4
+#define CLK_CAM_M_CAMTG			5
+#define CLK_CAM_M_SENINF		6
+#define CLK_CAM_M_CAMSV0		7
+#define CLK_CAM_M_CAMSV1		8
+#define CLK_CAM_M_CAMSV2		9
+#define CLK_CAM_M_CAMSV3		10
+#define CLK_CAM_M_CCU0			11
+#define CLK_CAM_M_CCU1			12
+#define CLK_CAM_M_MRAW0			13
+#define CLK_CAM_M_MRAW1			14
+#define CLK_CAM_M_FAKE_ENG		15
+#define CLK_CAM_M_NR_CLK		16
+
+/* CAMSYS_RAWA */
+#define CLK_CAM_RA_LARBX		0
+#define CLK_CAM_RA_CAM			1
+#define CLK_CAM_RA_CAMTG		2
+#define CLK_CAM_RA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+#define CLK_CAM_RB_LARBX		0
+#define CLK_CAM_RB_CAM			1
+#define CLK_CAM_RB_CAMTG		2
+#define CLK_CAM_RB_NR_CLK		3
+
+/* CAMSYS_RAWC */
+#define CLK_CAM_RC_LARBX		0
+#define CLK_CAM_RC_CAM			1
+#define CLK_CAM_RC_CAMTG		2
+#define CLK_CAM_RC_NR_CLK		3
+
+/* IPESYS */
+#define CLK_IPE_LARB19			0
+#define CLK_IPE_LARB20			1
+#define CLK_IPE_SMI_SUBCOM		2
+#define CLK_IPE_FD			3
+#define CLK_IPE_FE			4
+#define CLK_IPE_RSC			5
+#define CLK_IPE_DPE			6
+#define CLK_IPE_NR_CLK			7
+
+/* MDPSYS_CONFIG */
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_FG0			1
+#define CLK_MDP_HDR0			2
+#define CLK_MDP_AAL0			3
+#define CLK_MDP_RSZ0			4
+#define CLK_MDP_TDSHP0			5
+#define CLK_MDP_TCC0			6
+#define CLK_MDP_WROT0			7
+#define CLK_MDP_RDMA2			8
+#define CLK_MDP_AAL2			9
+#define CLK_MDP_RSZ2			10
+#define CLK_MDP_COLOR0			11
+#define CLK_MDP_TDSHP2			12
+#define CLK_MDP_TCC2			13
+#define CLK_MDP_WROT2			14
+#define CLK_MDP_MUTEX0			15
+#define CLK_MDP_RDMA1			16
+#define CLK_MDP_FG1			17
+#define CLK_MDP_HDR1			18
+#define CLK_MDP_AAL1			19
+#define CLK_MDP_RSZ1			20
+#define CLK_MDP_TDSHP1			21
+#define CLK_MDP_TCC1			22
+#define CLK_MDP_WROT1			23
+#define CLK_MDP_RDMA3			24
+#define CLK_MDP_AAL3			25
+#define CLK_MDP_RSZ3			26
+#define CLK_MDP_COLOR1			27
+#define CLK_MDP_TDSHP3			28
+#define CLK_MDP_TCC3			29
+#define CLK_MDP_WROT3			30
+#define CLK_MDP_APB_BUS			31
+#define CLK_MDP_MMSYSRAM		32
+#define CLK_MDP_APMCU_GALS		33
+#define CLK_MDP_FAKE_ENG0		34
+#define CLK_MDP_FAKE_ENG1		35
+#define CLK_MDP_SMI0			36
+#define CLK_MDP_IMG_DL_ASYNC0		37
+#define CLK_MDP_IMG_DL_ASYNC1		38
+#define CLK_MDP_IMG_DL_ASYNC2		39
+#define CLK_MDP_SMI1			40
+#define CLK_MDP_IMG_DL_ASYNC3		41
+#define CLK_MDP_RESERVED42		42
+#define CLK_MDP_RESERVED43		43
+#define CLK_MDP_SMI2			44
+#define CLK_MDP_RESERVED45		45
+#define CLK_MDP_RESERVED46		46
+#define CLK_MDP_RESERVED47		47
+#define CLK_MDP_IMG0_IMG_DL_ASYNC0	48
+#define CLK_MDP_IMG0_IMG_DL_ASYNC1	49
+#define CLK_MDP_IMG1_IMG_DL_ASYNC2	50
+#define CLK_MDP_IMG1_IMG_DL_ASYNC3	51
+#define CLK_MDP_NR_CLK			52
+
+/* SCP_SYS */
+#define SCP_SYS_MD1	0
+#define SCP_SYS_CONN	1
+#define SCP_SYS_MFG0	2
+#define SCP_SYS_MFG1	3
+#define SCP_SYS_MFG2	4
+#define SCP_SYS_MFG3	5
+#define SCP_SYS_MFG4	6
+#define SCP_SYS_MFG5	7
+#define SCP_SYS_MFG6	8
+#define SCP_SYS_IFR	9
+#define SCP_SYS_IFR_SUB	10
+#define SCP_SYS_DPY	11
+#define SCP_SYS_ISP	12
+#define SCP_SYS_ISP2	13
+#define SCP_SYS_IPE	14
+#define SCP_SYS_VDEC	15
+#define SCP_SYS_VDEC2	16
+#define SCP_SYS_VENC	17
+#define SCP_SYS_VENC_CORE1	18
+#define SCP_SYS_MDP	19
+#define SCP_SYS_DIS	20
+#define SCP_SYS_AUDIO	21
+#define SCP_SYS_ADSP	22
+#define SCP_SYS_CAM	23
+#define SCP_SYS_CAM_RAWA	24
+#define SCP_SYS_CAM_RAWB	25
+#define SCP_SYS_CAM_RAWC	26
+#define SCP_SYS_DP_TX	27
+#define SCP_SYS_DPY2	28
+#define SCP_SYS_VPU		29
+#define SCP_NR_SYSS	30
+
+#endif /* _DT_BINDINGS_CLK_MT6893_H */

include/dt-bindings/clock/mt6893-clk.h

@@ -0,0 +1,794 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6893_H
+#define _DT_BINDINGS_CLK_MT6893_H
+
+/* TOPCKGEN */
+#define CLK_TOP_ARMPLL_BL0_CK_VRPOC	0
+#define CLK_TOP_ARMPLL_BL1_CK_VRPOC	1
+#define CLK_TOP_ARMPLL_BL2_CK_VRPOC	2
+#define CLK_TOP_ARMPLL_BL3_CK_VRPOC	3
+#define CLK_TOP_ARMPLL_LL_CK_VRPOC	4
+#define CLK_TOP_CCIPLL_CK_VRPOC_CCI	5
+#define CLK_TOP_MFGPLL			6
+#define CLK_TOP_MAINPLL			7
+#define CLK_TOP_MAINPLL_D3		8
+#define CLK_TOP_MAINPLL_D4		9
+#define CLK_TOP_MAINPLL_D4_D2		10
+#define CLK_TOP_MAINPLL_D4_D4		11
+#define CLK_TOP_MAINPLL_D4_D8		12
+#define CLK_TOP_MAINPLL_D4_D16		13
+#define CLK_TOP_MAINPLL_D5		14
+#define CLK_TOP_MAINPLL_D5_D2		15
+#define CLK_TOP_MAINPLL_D5_D4		16
+#define CLK_TOP_MAINPLL_D5_D8		17
+#define CLK_TOP_MAINPLL_D6		18
+#define CLK_TOP_MAINPLL_D6_D2		19
+#define CLK_TOP_MAINPLL_D6_D4		20
+#define CLK_TOP_MAINPLL_D6_D8		21
+#define CLK_TOP_MAINPLL_D7		22
+#define CLK_TOP_MAINPLL_D7_D2		23
+#define CLK_TOP_MAINPLL_D7_D4		24
+#define CLK_TOP_MAINPLL_D7_D8		25
+#define CLK_TOP_MAINPLL_D9		26
+#define CLK_TOP_UNIVPLL			27
+#define CLK_TOP_UNIVPLL_D2		28
+#define CLK_TOP_UNIVPLL_D3		29
+#define CLK_TOP_UNIVPLL_D4		30
+#define CLK_TOP_UNIVPLL_D4_D2		31
+#define CLK_TOP_UNIVPLL_D4_D4		32
+#define CLK_TOP_UNIVPLL_D4_D8		33
+#define CLK_TOP_UNIVPLL_D5		34
+#define CLK_TOP_UNIVPLL_D5_D2		35
+#define CLK_TOP_UNIVPLL_D5_D4		36
+#define CLK_TOP_UNIVPLL_D5_D8		37
+#define CLK_TOP_UNIVPLL_D5_D16		38
+#define CLK_TOP_UNIVPLL_D6		39
+#define CLK_TOP_UNIVPLL_D6_D2		40
+#define CLK_TOP_UNIVPLL_D6_D4		41
+#define CLK_TOP_UNIVPLL_D6_D8		42
+#define CLK_TOP_UNIVPLL_D6_D16		43
+#define CLK_TOP_UNIVPLL_D7		44
+#define CLK_TOP_UNIVPLL_D7_D2		45
+#define CLK_TOP_UNIVPLL_192M_D2		46
+#define CLK_TOP_UNIVPLL_192M_D4		47
+#define CLK_TOP_UNIVPLL_192M_D8		48
+#define CLK_TOP_UNIVPLL_192M_D16	49
+#define CLK_TOP_UNIVPLL_192M_D32	50
+#define CLK_TOP_USB20_192M		51
+#define CLK_TOP_USB20_PLL_D2		52
+#define CLK_TOP_USB20_PLL_D4		53
+#define CLK_TOP_MPLL_208M		54
+#define CLK_TOP_MPLL_D2			55
+#define CLK_TOP_MPLL_D4			56
+#define CLK_TOP_APLL1			57
+#define CLK_TOP_APLL1_D2		58
+#define CLK_TOP_APLL1_D4		59
+#define CLK_TOP_APLL1_D8		60
+#define CLK_TOP_APLL2			61
+#define CLK_TOP_APLL2_D2		62
+#define CLK_TOP_APLL2_D4		63
+#define CLK_TOP_APLL2_D8		64
+#define CLK_TOP_CLK26M_BYP		65
+#define CLK_TOP_ADSPPLL			66
+#define CLK_TOP_ADSPPLL_D4		67
+#define CLK_TOP_ADSPPLL_D5		68
+#define CLK_TOP_ADSPPLL_D6		69
+#define CLK_TOP_MMPLL			70
+#define CLK_TOP_MMPLL_D3		71
+#define CLK_TOP_MMPLL_D4		72
+#define CLK_TOP_MMPLL_D4_D2		73
+#define CLK_TOP_MMPLL_D4_D4		74
+#define CLK_TOP_MMPLL_D5		75
+#define CLK_TOP_MMPLL_D5_D2		76
+#define CLK_TOP_MMPLL_D5_D4		77
+#define CLK_TOP_MMPLL_D6		78
+#define CLK_TOP_MMPLL_D6_D2		79
+#define CLK_TOP_MMPLL_D7		80
+#define CLK_TOP_MMPLL_D9		81
+#define CLK_TOP_APUPLL			82
+#define CLK_TOP_TVDPLL			83
+#define CLK_TOP_TVDPLL_D2		84
+#define CLK_TOP_TVDPLL_D4		85
+#define CLK_TOP_TVDPLL_D8		86
+#define CLK_TOP_TVDPLL_D16		87
+#define CLK_TOP_MSDCPLL			88
+#define CLK_TOP_MSDCPLL_D2		89
+#define CLK_TOP_MSDCPLL_D4		90
+#define CLK_TOP_MSDCPLL_D8		91
+#define CLK_TOP_MSDCPLL_D16		92
+#define CLK_TOP_MIPI_26M		93
+#define CLK_TOP_MEM_26M			94
+#define CLK_TOP_ARMPLL_26M		95
+#define CLK_TOP_SSUBS_26M		96
+#define CLK_TOP_PLLGP_TST		97
+#define CLK_TOP_CLKRTC			98
+#define CLK_TOP_TCK_26M_MX8		99
+#define CLK_TOP_TCK_26M_MX9		100
+#define CLK_TOP_TCK_26M_MX10		101
+#define CLK_TOP_TCK_26M_MX11		102
+#define CLK_TOP_TCK_26M_MX12		103
+#define CLK_TOP_CSW_FAXI		104
+#define CLK_TOP_F26M_CK_D52		105
+#define CLK_TOP_F26M_CK_D2		106
+#define CLK_TOP_OSC			107
+#define CLK_TOP_OSC_D2			108
+#define CLK_TOP_OSC_D4			109
+#define CLK_TOP_OSC_D8			110
+#define CLK_TOP_OSC_D16			111
+#define CLK_TOP_OSC_D10			112
+#define CLK_TOP_OSC_D20			113
+#define CLK_TOP_TVDPLL_MAINPLL_D2	114
+#define CLK_TOP_F26M			115
+#define CLK_TOP_FRTC			116
+#define CLK_TOP_AXI			117
+#define CLK_TOP_SPM			118
+#define CLK_TOP_SCP			119
+#define CLK_TOP_BUS			120
+#define CLK_TOP_DISP			121
+#define CLK_TOP_MDP			122
+#define CLK_TOP_IMG1			123
+#define CLK_TOP_IMG2			124
+#define CLK_TOP_IPE			125
+#define CLK_TOP_DPE			126
+#define CLK_TOP_CAM			127
+#define CLK_TOP_CCU			128
+#define CLK_TOP_DSP			129
+#define CLK_TOP_DSP1			130
+#define CLK_TOP_DSP2			131
+#define CLK_TOP_DSP3			132
+#define CLK_TOP_DSP4			133
+#define CLK_TOP_DSP5			134
+#define CLK_TOP_DSP6			135
+#define CLK_TOP_DSP7			136
+#define CLK_TOP_IPU_IF			137
+#define CLK_TOP_MFG_REF			138
+#define CLK_TOP_FCAMTG			139
+#define CLK_TOP_FCAMTG2			140
+#define CLK_TOP_FCAMTG3			141
+#define CLK_TOP_FCAMTG4			142
+#define CLK_TOP_FUART			143
+#define CLK_TOP_SPI			144
+#define CLK_TOP_MSDC50_0_HCLK		145
+#define CLK_TOP_MSDC50_0		146
+#define CLK_TOP_MSDC30_1		147
+#define CLK_TOP_AUDIO			148
+#define CLK_TOP_AUD_INTBUS		149
+#define CLK_TOP_FPWRAP_ULPOSC		150
+#define CLK_TOP_ATB			151
+#define CLK_TOP_SSPM			152
+#define CLK_TOP_DP			153
+#define CLK_TOP_SCAM			154
+#define CLK_TOP_FDISP_PWM		155
+#define CLK_TOP_FUSB_TOP		156
+#define CLK_TOP_FSSUSB_XHCI		157
+#define CLK_TOP_I2C			158
+#define CLK_TOP_FSENINF			159
+#define CLK_TOP_FSENINF1		160
+#define CLK_TOP_FSENINF2		161
+#define CLK_TOP_FSENINF3		162
+#define CLK_TOP_DXCC			163
+#define CLK_TOP_AUD_ENGEN1		164
+#define CLK_TOP_AUD_ENGEN2		165
+#define CLK_TOP_AES_UFSFDE		166
+#define CLK_TOP_UFS			167
+#define CLK_TOP_AUD_1			168
+#define CLK_TOP_AUD_2			169
+#define CLK_TOP_ADSP			170
+#define CLK_TOP_DPMAIF_MAIN		171
+#define CLK_TOP_VENC			172
+#define CLK_TOP_VDEC			173
+#define CLK_TOP_VDEC_LAT		174
+#define CLK_TOP_CAMTM			175
+#define CLK_TOP_PWM			176
+#define CLK_TOP_AUDIO_H			177
+#define CLK_TOP_FCAMTG5			178
+#define CLK_TOP_FCAMTG6			179
+#define CLK_TOP_MCUPM			180
+#define CLK_TOP_SPMI_MST		181
+#define CLK_TOP_DVFSRC			182
+#define CLK_TOP_SRCK			183
+#define CLK_TOP_SYS_26M			184
+#define CLK_TOP_F_UFS_MP_SAP_CFG	185
+#define CLK_TOP_F_UFS_TICK1US		186
+#define CLK_TOP_I2C_PSEUDO		187
+#define CLK_TOP_APDMA_PSEUDO		188
+#define CLK_TOP_AXI_SEL			189
+#define CLK_TOP_SPM_SEL			190
+#define CLK_TOP_SCP_SEL			191
+#define CLK_TOP_BUS_AXIMEM_SEL		192
+#define CLK_TOP_DISP_SEL		193
+#define CLK_TOP_MDP_SEL			194
+#define CLK_TOP_IMG1_SEL		195
+#define CLK_TOP_IMG2_SEL		196
+#define CLK_TOP_IPE_SEL			197
+#define CLK_TOP_DPE_SEL			198
+#define CLK_TOP_CAM_SEL			199
+#define CLK_TOP_CCU_SEL			200
+#define CLK_TOP_DSP_SEL			201
+#define CLK_TOP_DSP1_SEL		202
+#define CLK_TOP_DSP2_SEL		203
+#define CLK_TOP_DSP3_SEL		204
+#define CLK_TOP_DSP4_SEL		205
+#define CLK_TOP_DSP5_SEL		206
+#define CLK_TOP_DSP6_SEL		207
+#define CLK_TOP_DSP7_SEL		208
+#define CLK_TOP_IPU_IF_SEL		209
+#define CLK_TOP_MFG_SEL			210
+#define CLK_TOP_CAMTG_SEL		211
+#define CLK_TOP_CAMTG2_SEL		212
+#define CLK_TOP_CAMTG3_SEL		213
+#define CLK_TOP_CAMTG4_SEL		214
+#define CLK_TOP_UART_SEL		215
+#define CLK_TOP_SPI_SEL			216
+#define CLK_TOP_MSDC50_0_HCLK_SEL	217
+#define CLK_TOP_MSDC50_0_SEL		218
+#define CLK_TOP_MSDC30_1_SEL		219
+#define CLK_TOP_AUDIO_SEL		220
+#define CLK_TOP_AUD_INTBUS_SEL		221
+#define CLK_TOP_PWRAP_ULPOSC_SEL	222
+#define CLK_TOP_ATB_SEL			223
+#define CLK_TOP_SSPM_SEL		224
+#define CLK_TOP_DP_SEL			225
+#define CLK_TOP_SCAM_SEL		226
+#define CLK_TOP_DISP_PWM_SEL		227
+#define CLK_TOP_USB_TOP_SEL		228
+#define CLK_TOP_SSUSB_XHCI_SEL		229
+#define CLK_TOP_I2C_SEL			230
+#define CLK_TOP_SENINF_SEL		231
+#define CLK_TOP_SENINF1_SEL		232
+#define CLK_TOP_SENINF2_SEL		233
+#define CLK_TOP_SENINF3_SEL		234
+#define CLK_TOP_DXCC_SEL		235
+#define CLK_TOP_AUD_ENGEN1_SEL		236
+#define CLK_TOP_AUD_ENGEN2_SEL		237
+#define CLK_TOP_AES_UFSFDE_SEL		238
+#define CLK_TOP_UFS_SEL			239
+#define CLK_TOP_AUD_1_SEL		240
+#define CLK_TOP_AUD_2_SEL		241
+#define CLK_TOP_ADSP_SEL		242
+#define CLK_TOP_DPMAIF_MAIN_SEL		243
+#define CLK_TOP_VENC_SEL		244
+#define CLK_TOP_VDEC_SEL		245
+#define CLK_TOP_VDEC_LAT_SEL		246
+#define CLK_TOP_CAMTM_SEL		247
+#define CLK_TOP_PWM_SEL			248
+#define CLK_TOP_AUDIO_H_SEL		249
+#define CLK_TOP_CAMTG5_SEL		250
+#define CLK_TOP_CAMTG6_SEL		251
+#define CLK_TOP_MCUPM_SEL		252
+#define CLK_TOP_SPMI_MST_SEL		253
+#define CLK_TOP_DVFSRC_SEL		254
+#define CLK_TOP_APLL_I2S0_MCK_SEL	255
+#define CLK_TOP_APLL_I2S1_MCK_SEL	256
+#define CLK_TOP_APLL_I2S2_MCK_SEL	257
+#define CLK_TOP_APLL_I2S3_MCK_SEL	258
+#define CLK_TOP_APLL_I2S4_MCK_SEL	259
+#define CLK_TOP_APLL_I2S5_MCK_SEL	260
+#define CLK_TOP_APLL_I2S6_MCK_SEL	261
+#define CLK_TOP_APLL_I2S7_MCK_SEL	262
+#define CLK_TOP_APLL_I2S8_MCK_SEL	263
+#define CLK_TOP_APLL_I2S9_MCK_SEL	264
+#define CLK_TOP_APLL1_CK_DIV0		265
+#define CLK_TOP_APLL2_CK_DIV0		266
+#define CLK_TOP_APLL12_CK_DIV0		267
+#define CLK_TOP_APLL12_CK_DIV1		268
+#define CLK_TOP_APLL12_CK_DIV2		269
+#define CLK_TOP_APLL12_CK_DIV3		270
+#define CLK_TOP_APLL12_CK_DIV4		271
+#define CLK_TOP_APLL12_CK_DIVB		272
+#define CLK_TOP_APLL12_CK_DIV5_LSB	273
+#define CLK_TOP_APLL12_CK_DIV5_MSB	274
+#define CLK_TOP_APLL12_CK_DIV6		275
+#define CLK_TOP_APLL12_CK_DIV7		276
+#define CLK_TOP_APLL12_CK_DIV8		277
+#define CLK_TOP_APLL12_CK_DIV9		278
+#define CLK_TOP_NR_CLK			279
+
+/* INFRACFG_AO */
+#define CLK_IFRAO_PMIC_TMR		0
+#define CLK_IFRAO_PMIC_AP		1
+#define CLK_IFRAO_GCE			2
+#define CLK_IFRAO_GCE2			3
+#define CLK_IFRAO_THERM			4
+#define CLK_IFRAO_I2C0			5
+#define CLK_IFRAO_I2C1			6
+#define CLK_IFRAO_I2C2			7
+#define CLK_IFRAO_I2C3			8
+#define CLK_IFRAO_PWM_HCLK		9
+#define CLK_IFRAO_PWM1			10
+#define CLK_IFRAO_PWM2			11
+#define CLK_IFRAO_PWM3			12
+#define CLK_IFRAO_PWM4			13
+#define CLK_IFRAO_PWM			14
+#define CLK_IFRAO_UART0			15
+#define CLK_IFRAO_UART1			16
+#define CLK_IFRAO_UART2			17
+#define CLK_IFRAO_UART3			18
+#define CLK_IFRAO_GCE_26M		19
+#define CLK_IFRAO_CQ_DMA_FPC		20
+#define CLK_IFRAO_BTIF			21
+#define CLK_IFRAO_SPI0			22
+#define CLK_IFRAO_MSDC0			23
+#define CLK_IFRAO_MSDC1			24
+#define CLK_IFRAO_MSDC0_SRC		25
+#define CLK_IFRAO_AUXADC		26
+#define CLK_IFRAO_CPUM			27
+#define CLK_IFRAO_CCIF1_AP		28
+#define CLK_IFRAO_CCIF1_MD		29
+#define CLK_IFRAO_MSDC1_SRC		30
+#define CLK_IFRAO_AP_DMA_PS		31
+#define CLK_IFRAO_DEVICE_APC		32
+#define CLK_IFRAO_CCIF_AP		33
+#define CLK_IFRAO_AUDIO			34
+#define CLK_IFRAO_CCIF_MD		35
+#define CLK_IFRAO_DXCC_SEC_CORE		36
+#define CLK_IFRAO_SSUSB			37
+#define CLK_IFRAO_DISP_PWM		38
+#define CLK_IFRAO_DPMAIF		39
+#define CLK_IFRAO_AUDIO_26M_BCLK	40
+#define CLK_IFRAO_SPI1			41
+#define CLK_IFRAO_I2C4			42
+#define CLK_IFRAO_SPI2			43
+#define CLK_IFRAO_SPI3			44
+#define CLK_IFRAO_UNIPRO_SYSCLK		45
+#define CLK_IFRAO_UFS_MP_SAP_BCLK	46
+#define CLK_IFRAO_I2C5			47
+#define CLK_IFRAO_I2C5_ARBITER		48
+#define CLK_IFRAO_I2C5_IMM		49
+#define CLK_IFRAO_I2C1_ARBITER		50
+#define CLK_IFRAO_I2C1_IMM		51
+#define CLK_IFRAO_I2C2_ARBITER		52
+#define CLK_IFRAO_I2C2_IMM		53
+#define CLK_IFRAO_SPI4			54
+#define CLK_IFRAO_SPI5			55
+#define CLK_IFRAO_CQ_DMA		56
+#define CLK_IFRAO_UFS			57
+#define CLK_IFRAO_AES			58
+#define CLK_IFRAO_SSUSB_XHCI		59
+#define CLK_IFRAO_MSDC0_SELF		60
+#define CLK_IFRAO_MSDC1_SELF		61
+#define CLK_IFRAO_MSDC2_SELF		62
+#define CLK_IFRAO_I2C6			63
+#define CLK_IFRAO_AP_MSDC0		64
+#define CLK_IFRAO_MD_MSDC0		65
+#define CLK_IFRAO_CCIF5_AP		66
+#define CLK_IFRAO_CCIF5_MD		67
+#define CLK_IFRAO_CCIF2_AP		68
+#define CLK_IFRAO_CCIF2_MD		69
+#define CLK_IFRAO_I2C7			70
+#define CLK_IFRAO_I2C8			71
+#define CLK_IFRAO_FBIST2FPC		72
+#define CLK_IFRAO_DEVICE_APC_SYNC	73
+#define CLK_IFRAO_DPMAIF_MAIN		74
+#define CLK_IFRAO_CCIF4_AP		75
+#define CLK_IFRAO_CCIF4_MD		76
+#define CLK_IFRAO_SPI6_CK		77
+#define CLK_IFRAO_SPI7_CK		78
+#define CLK_IFRAO_APDMA			79
+#define CLK_IFRAO_NR_CLK		80
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL		0
+#define CLK_APMIXED_ARMPLL_BL0		1
+#define CLK_APMIXED_ARMPLL_BL1		2
+#define CLK_APMIXED_ARMPLL_BL2		3
+#define CLK_APMIXED_ARMPLL_BL3		4
+#define CLK_APMIXED_CCIPLL		5
+#define CLK_APMIXED_MAINPLL		6
+#define CLK_APMIXED_UNIVPLL		7
+#define CLK_APMIXED_MSDCPLL		8
+#define CLK_APMIXED_MMPLL		9
+#define CLK_APMIXED_ADSPPLL		10
+#define CLK_APMIXED_MFGPLL		11
+#define CLK_APMIXED_TVDPLL		12
+#define CLK_APMIXED_APLL1		13
+#define CLK_APMIXED_APLL2		14
+#define CLK_APMIXED_MPLL		15
+#define CLK_APMIXED_APUPLL		16
+#define CLK_APMIXED_NR_CLK		17
+
+/* SCP_ADSP */
+#define CLK_SCP_ADSP_RG_AUDIODSP	0
+#define CLK_SCP_ADSP_NR_CLK		1
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMPC_AP_I2C0_RO		0
+#define CLK_IMPC_AP_I2C10_RO		1
+#define CLK_IMPC_AP_I2C11_RO		2
+#define CLK_IMPC_AP_I2C12_RO		3
+#define CLK_IMPC_AP_I2C13_RO		4
+#define CLK_IMPC_NR_CLK			5
+
+/* AUDIOSYS */
+#define CLK_AUDSYS_AFE			0
+#define CLK_AUDSYS_22M			1
+#define CLK_AUDSYS_24M			2
+#define CLK_AUDSYS_APLL2_TUNER		3
+#define CLK_AUDSYS_APLL_TUNER		4
+#define CLK_AUDSYS_TDM			5
+#define CLK_AUDSYS_ADC			6
+#define CLK_AUDSYS_DAC			7
+#define CLK_AUDSYS_DAC_PREDIS		8
+#define CLK_AUDSYS_TML			9
+#define CLK_AUDSYS_NLE			10
+#define CLK_AUDSYS_I2S1_BCLK		11
+#define CLK_AUDSYS_I2S2_BCLK		12
+#define CLK_AUDSYS_I2S3_BCLK		13
+#define CLK_AUDSYS_I2S4_BCLK		14
+#define CLK_AUDSYS_CONNSYS_I2S_ASRC	15
+#define CLK_AUDSYS_GENERAL1_ASRC	16
+#define CLK_AUDSYS_GENERAL2_ASRC	17
+#define CLK_AUDSYS_DAC_HIRES		18
+#define CLK_AUDSYS_ADC_HIRES		19
+#define CLK_AUDSYS_ADC_HIRES_TML	20
+#define CLK_AUDSYS_ADDA6_ADC		21
+#define CLK_AUDSYS_ADDA6_ADC_HIRES	22
+#define CLK_AUDSYS_3RD_DAC		23
+#define CLK_AUDSYS_3RD_DAC_PREDIS	24
+#define CLK_AUDSYS_3RD_DAC_TML		25
+#define CLK_AUDSYS_3RD_DAC_HIRES	26
+#define CLK_AUDSYS_I2S5_BCLK		27
+#define CLK_AUDSYS_I2S6_BCLK		28
+#define CLK_AUDSYS_I2S7_BCLK		29
+#define CLK_AUDSYS_I2S8_BCLK		30
+#define CLK_AUDSYS_I2S9_BCLK		31
+#define CLK_AUDSYS_NR_CLK		32
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_AP_I2C3_RO		0
+#define CLK_IMPE_AP_I2C9_RO		1
+#define CLK_IMPE_NR_CLK			2
+
+/* IMP_IIC_WRAP_S */
+#define CLK_IMPS_AP_I2C1_RO		0
+#define CLK_IMPS_AP_I2C2_RO		1
+#define CLK_IMPS_AP_I2C4_RO		2
+#define CLK_IMPS_AP_I2C7_RO		3
+#define CLK_IMPS_AP_I2C8_RO		4
+#define CLK_IMPS_NR_CLK			5
+
+/* IMP_IIC_WRAP_N */
+#define CLK_IMPN_AP_I2C5_RO		0
+#define CLK_IMPN_AP_I2C6_RO		1
+#define CLK_IMPN_NR_CLK			2
+
+/* MFGCFG */
+#define CLK_MFGCFG_BG3D			0
+#define CLK_MFGCFG_NR_CLK		1
+
+/* MMSYS_CONFIG */
+#define CLK_MM_DISP_RSZ0		0
+#define CLK_MM_DISP_RSZ1		1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_INLINE			3
+#define CLK_MM_MDP_TDSHP4		4
+#define CLK_MM_MDP_TDSHP5		5
+#define CLK_MM_MDP_AAL4			6
+#define CLK_MM_MDP_AAL5			7
+#define CLK_MM_MDP_HDR4			8
+#define CLK_MM_MDP_HDR5			9
+#define CLK_MM_MDP_RSZ4			10
+#define CLK_MM_MDP_RSZ5			11
+#define CLK_MM_MDP_RDMA4		12
+#define CLK_MM_MDP_RDMA5		13
+#define CLK_MM_DISP_FAKE_ENG0		14
+#define CLK_MM_DISP_FAKE_ENG1		15
+#define CLK_MM_DISP_OVL0_2L		16
+#define CLK_MM_DISP_OVL1_2L		17
+#define CLK_MM_DISP_OVL2_2L		18
+#define CLK_MM_DISP_MUTEX		19
+#define CLK_MM_DISP_OVL1		20
+#define CLK_MM_DISP_OVL3_2L		21
+#define CLK_MM_DISP_CCORR0		22
+#define CLK_MM_DISP_CCORR1		23
+#define CLK_MM_DISP_COLOR0		24
+#define CLK_MM_DISP_COLOR1		25
+#define CLK_MM_DISP_POSTMASK0		26
+#define CLK_MM_DISP_POSTMASK1		27
+#define CLK_MM_DISP_DITHER0		28
+#define CLK_MM_DISP_DITHER1		29
+#define CLK_MM_DSI0_MM_CLK		30
+#define CLK_MM_DSI1_MM_CLK		31
+#define CLK_MM_DISP_GAMMA0		32
+#define CLK_MM_DISP_GAMMA1		33
+#define CLK_MM_DISP_AAL0		34
+#define CLK_MM_DISP_AAL1		35
+#define CLK_MM_DISP_WDMA0		36
+#define CLK_MM_DISP_WDMA1		37
+#define CLK_MM_DISP_UFBC_WDMA0		38
+#define CLK_MM_DISP_UFBC_WDMA1		39
+#define CLK_MM_DISP_RDMA0		40
+#define CLK_MM_DISP_RDMA1		41
+#define CLK_MM_DISP_RDMA4		42
+#define CLK_MM_DISP_RDMA5		43
+#define CLK_MM_DISP_DSC_WRAP		44
+#define CLK_MM_DP_INTF_MM_CLK		45
+#define CLK_MM_DISP_MERGE0		46
+#define CLK_MM_DISP_MERGE1		47
+#define CLK_MM_SMI_COMMON		48
+#define CLK_MM_SMI_GALS			49
+#define CLK_MM_SMI_INFRA		50
+#define CLK_MM_SMI_IOMMU		51
+#define CLK_MM_DSI0_INTF_CLK		52
+#define CLK_MM_DSI1_INTF_CLK		53
+#define CLK_MM_DP_INTF_INTF_CLK		54
+#define CLK_MM_CK_26_MHZ		55
+#define CLK_MM_CK_32_KHZ		56
+#define CLK_MM_NR_CLK			57
+
+/* IMGSYS1 */
+#define CLK_IMGSYS1_LARB9		0
+#define CLK_IMGSYS1_LARB10		1
+#define CLK_IMGSYS1_DIP			2
+#define CLK_IMGSYS1_MFB			3
+#define CLK_IMGSYS1_WPE			4
+#define CLK_IMGSYS1_MSS			5
+#define CLK_IMGSYS1_NR_CLK		6
+
+/* IMGSYS2 */
+#define CLK_IMGSYS2_LARB11		0
+#define CLK_IMGSYS2_LARB12		1
+#define CLK_IMGSYS2_DIP			2
+#define CLK_IMGSYS2_WPE			3
+#define CLK_IMGSYS2_NR_CLK		4
+
+/* VDEC_SOC_GCON */
+#define CLK_VDE1_LARB1_CKEN		0
+#define CLK_VDE1_LAT_CKEN		1
+#define CLK_VDE1_LAT_ACTIVE		2
+#define CLK_VDE1_LAT_CKEN_ENG		3
+#define CLK_VDE1_VDEC_CKEN		4
+#define CLK_VDE1_VDEC_ACTIVE		5
+#define CLK_VDE1_VDEC_CKEN_ENG		6
+#define CLK_VDE1_NR_CLK			7
+
+/* VDEC_GCON */
+#define CLK_VDE2_LARB1_CKEN		0
+#define CLK_VDE2_LAT_CKEN		1
+#define CLK_VDE2_LAT_ACTIVE		2
+#define CLK_VDE2_LAT_CKEN_ENG		3
+#define CLK_VDE2_VDEC_CKEN		4
+#define CLK_VDE2_VDEC_ACTIVE		5
+#define CLK_VDE2_VDEC_CKEN_ENG		6
+#define CLK_VDE2_NR_CLK			7
+
+/* VENC_GCON */
+#define CLK_VEN1_CKE0_LARB		0
+#define CLK_VEN1_CKE1_VENC		1
+#define CLK_VEN1_CKE2_JPGENC		2
+#define CLK_VEN1_CKE3_JPGDEC		3
+#define CLK_VEN1_CKE4_JPGDEC_C1		4
+#define CLK_VEN1_CKE5_GALS		5
+#define CLK_VEN1_NR_CLK			6
+
+/* VENC_C1_GCON */
+#define CLK_VEN2_CKE0_LARB		0
+#define CLK_VEN2_CKE1_VENC		1
+#define CLK_VEN2_CKE2_JPGENC		2
+#define CLK_VEN2_CKE3_JPGDEC		3
+#define CLK_VEN2_CKE4_JPGDEC_C1		4
+#define CLK_VEN2_CKE5_GALS		5
+#define CLK_VEN2_NR_CLK			6
+
+/* APU_CONN */
+#define CLK_APUC_AHB			0
+#define CLK_APUC_AXI			1
+#define CLK_APUC_ISP			2
+#define CLK_APUC_CAM_ADL		3
+#define CLK_APUC_IMG_ADL		4
+#define CLK_APUC_EMI_26M		5
+#define CLK_APUC_VPU_UDI		6
+#define CLK_APUC_EDMA_0			7
+#define CLK_APUC_EDMA_1			8
+#define CLK_APUC_EDMAL_0		9
+#define CLK_APUC_EDMAL_1		10
+#define CLK_APUC_MNOC			11
+#define CLK_APUC_TCM			12
+#define CLK_APUC_MD32			13
+#define CLK_APUC_IOMMU_0		14
+#define CLK_APUC_IOMMU_1		15
+#define CLK_APUC_MD32_32K		16
+#define CLK_APUC_NR_CLK			17
+
+/* APU_VCORE */
+#define CLK_APUV_AHB			0
+#define CLK_APUV_AXI			1
+#define CLK_APUV_ADL			2
+#define CLK_APUV_QOS			3
+#define CLK_APUV_NR_CLK			4
+
+/* APU0 */
+#define CLK_APU0_APU			0
+#define CLK_APU0_AXI_M			1
+#define CLK_APU0_JTAG			2
+#define CLK_APU0_NR_CLK			3
+
+/* APU1 */
+#define CLK_APU1_APU			0
+#define CLK_APU1_AXI_M			1
+#define CLK_APU1_JTAG			2
+#define CLK_APU1_NR_CLK			3
+
+/* APU2 */
+#define CLK_APU2_APU			0
+#define CLK_APU2_AXI_M			1
+#define CLK_APU2_JTAG			2
+#define CLK_APU2_NR_CLK			3
+
+/* APU_MDLA0 */
+#define CLK_APUM0_MDLA_CG0		0
+#define CLK_APUM0_MDLA_CG1		1
+#define CLK_APUM0_MDLA_CG2		2
+#define CLK_APUM0_MDLA_CG3		3
+#define CLK_APUM0_MDLA_CG4		4
+#define CLK_APUM0_MDLA_CG5		5
+#define CLK_APUM0_MDLA_CG6		6
+#define CLK_APUM0_MDLA_CG7		7
+#define CLK_APUM0_MDLA_CG8		8
+#define CLK_APUM0_MDLA_CG9		9
+#define CLK_APUM0_MDLA_CG10		10
+#define CLK_APUM0_MDLA_CG11		11
+#define CLK_APUM0_MDLA_CG12		12
+#define CLK_APUM0_APB			13
+#define CLK_APUM0_AXI_M			14
+#define CLK_APUM0_NR_CLK		15
+
+/* APU_MDLA1 */
+#define CLK_APUM1_MDLA_CG0		0
+#define CLK_APUM1_MDLA_CG1		1
+#define CLK_APUM1_MDLA_CG2		2
+#define CLK_APUM1_MDLA_CG3		3
+#define CLK_APUM1_MDLA_CG4		4
+#define CLK_APUM1_MDLA_CG5		5
+#define CLK_APUM1_MDLA_CG6		6
+#define CLK_APUM1_MDLA_CG7		7
+#define CLK_APUM1_MDLA_CG8		8
+#define CLK_APUM1_MDLA_CG9		9
+#define CLK_APUM1_MDLA_CG10		10
+#define CLK_APUM1_MDLA_CG11		11
+#define CLK_APUM1_MDLA_CG12		12
+#define CLK_APUM1_APB			13
+#define CLK_APUM1_AXI_M			14
+#define CLK_APUM1_NR_CLK		15
+
+/* CAMSYS_MAIN */
+#define CLK_CAM_M_LARB13		0
+#define CLK_CAM_M_DFP_VAD		1
+#define CLK_CAM_M_LARB14		2
+#define CLK_CAM_M_LARB15		3
+#define CLK_CAM_M_CAM			4
+#define CLK_CAM_M_CAMTG			5
+#define CLK_CAM_M_SENINF		6
+#define CLK_CAM_M_CAMSV0		7
+#define CLK_CAM_M_CAMSV1		8
+#define CLK_CAM_M_CAMSV2		9
+#define CLK_CAM_M_CAMSV3		10
+#define CLK_CAM_M_CCU0			11
+#define CLK_CAM_M_CCU1			12
+#define CLK_CAM_M_MRAW0			13
+#define CLK_CAM_M_MRAW1			14
+#define CLK_CAM_M_FAKE_ENG		15
+#define CLK_CAM_M_NR_CLK		16
+
+/* CAMSYS_RAWA */
+#define CLK_CAM_RA_LARBX		0
+#define CLK_CAM_RA_CAM			1
+#define CLK_CAM_RA_CAMTG		2
+#define CLK_CAM_RA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+#define CLK_CAM_RB_LARBX		0
+#define CLK_CAM_RB_CAM			1
+#define CLK_CAM_RB_CAMTG		2
+#define CLK_CAM_RB_NR_CLK		3
+
+/* CAMSYS_RAWC */
+#define CLK_CAM_RC_LARBX		0
+#define CLK_CAM_RC_CAM			1
+#define CLK_CAM_RC_CAMTG		2
+#define CLK_CAM_RC_NR_CLK		3
+
+/* IPESYS */
+#define CLK_IPE_LARB19			0
+#define CLK_IPE_LARB20			1
+#define CLK_IPE_SMI_SUBCOM		2
+#define CLK_IPE_FD			3
+#define CLK_IPE_FE			4
+#define CLK_IPE_RSC			5
+#define CLK_IPE_DPE			6
+#define CLK_IPE_NR_CLK			7
+
+/* MDPSYS_CONFIG */
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_FG0			1
+#define CLK_MDP_HDR0			2
+#define CLK_MDP_AAL0			3
+#define CLK_MDP_RSZ0			4
+#define CLK_MDP_TDSHP0			5
+#define CLK_MDP_TCC0			6
+#define CLK_MDP_WROT0			7
+#define CLK_MDP_RDMA2			8
+#define CLK_MDP_AAL2			9
+#define CLK_MDP_RSZ2			10
+#define CLK_MDP_COLOR0			11
+#define CLK_MDP_TDSHP2			12
+#define CLK_MDP_TCC2			13
+#define CLK_MDP_WROT2			14
+#define CLK_MDP_MUTEX0			15
+#define CLK_MDP_RDMA1			16
+#define CLK_MDP_FG1			17
+#define CLK_MDP_HDR1			18
+#define CLK_MDP_AAL1			19
+#define CLK_MDP_RSZ1			20
+#define CLK_MDP_TDSHP1			21
+#define CLK_MDP_TCC1			22
+#define CLK_MDP_WROT1			23
+#define CLK_MDP_RDMA3			24
+#define CLK_MDP_AAL3			25
+#define CLK_MDP_RSZ3			26
+#define CLK_MDP_COLOR1			27
+#define CLK_MDP_TDSHP3			28
+#define CLK_MDP_TCC3			29
+#define CLK_MDP_WROT3			30
+#define CLK_MDP_APB_BUS			31
+#define CLK_MDP_MMSYSRAM		32
+#define CLK_MDP_APMCU_GALS		33
+#define CLK_MDP_FAKE_ENG0		34
+#define CLK_MDP_FAKE_ENG1		35
+#define CLK_MDP_SMI0			36
+#define CLK_MDP_IMG_DL_ASYNC0		37
+#define CLK_MDP_IMG_DL_ASYNC1		38
+#define CLK_MDP_IMG_DL_ASYNC2		39
+#define CLK_MDP_SMI1			40
+#define CLK_MDP_IMG_DL_ASYNC3		41
+#define CLK_MDP_RESERVED42		42
+#define CLK_MDP_RESERVED43		43
+#define CLK_MDP_SMI2			44
+#define CLK_MDP_RESERVED45		45
+#define CLK_MDP_RESERVED46		46
+#define CLK_MDP_RESERVED47		47
+#define CLK_MDP_IMG0_IMG_DL_ASYNC0	48
+#define CLK_MDP_IMG0_IMG_DL_ASYNC1	49
+#define CLK_MDP_IMG1_IMG_DL_ASYNC2	50
+#define CLK_MDP_IMG1_IMG_DL_ASYNC3	51
+#define CLK_MDP_NR_CLK			52
+
+/* SCP_SYS */
+#define SCP_SYS_MD1	0
+#define SCP_SYS_CONN	1
+#define SCP_SYS_MFG0	2
+#define SCP_SYS_MFG1	3
+#define SCP_SYS_MFG2	4
+#define SCP_SYS_MFG3	5
+#define SCP_SYS_MFG4	6
+#define SCP_SYS_MFG5	7
+#define SCP_SYS_MFG6	8
+#define SCP_SYS_IFR	9
+#define SCP_SYS_IFR_SUB	10
+#define SCP_SYS_DPY	11
+#define SCP_SYS_ISP	12
+#define SCP_SYS_ISP2	13
+#define SCP_SYS_IPE	14
+#define SCP_SYS_VDEC	15
+#define SCP_SYS_VDEC2	16
+#define SCP_SYS_VENC	17
+#define SCP_SYS_VENC_CORE1	18
+#define SCP_SYS_MDP	19
+#define SCP_SYS_DIS	20
+#define SCP_SYS_AUDIO	21
+#define SCP_SYS_ADSP	22
+#define SCP_SYS_CAM	23
+#define SCP_SYS_CAM_RAWA	24
+#define SCP_SYS_CAM_RAWB	25
+#define SCP_SYS_CAM_RAWC	26
+#define SCP_SYS_DP_TX	27
+#define SCP_SYS_DPY2	28
+#define SCP_SYS_VPU		29
+#define SCP_NR_SYSS	30
+
+#endif /* _DT_BINDINGS_CLK_MT6893_H */

include/dt-bindings/clock/mt7622-clk.h

@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7622_H
+#define _DT_BINDINGS_CLK_MT7622_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_TO_U2_PHY		0
+#define CLK_TOP_TO_U2_PHY_1P		1
+#define CLK_TOP_PCIE0_PIPE_EN		2
+#define CLK_TOP_PCIE1_PIPE_EN		3
+#define CLK_TOP_SSUSB_TX250M		4
+#define CLK_TOP_SSUSB_EQ_RX250M		5
+#define CLK_TOP_SSUSB_CDR_REF		6
+#define CLK_TOP_SSUSB_CDR_FB		7
+#define CLK_TOP_SATA_ASIC		8
+#define CLK_TOP_SATA_RBC		9
+#define CLK_TOP_TO_USB3_SYS		10
+#define CLK_TOP_P1_1MHZ			11
+#define CLK_TOP_4MHZ			12
+#define CLK_TOP_P0_1MHZ			13
+#define CLK_TOP_TXCLK_SRC_PRE		14
+#define CLK_TOP_RTC			15
+#define CLK_TOP_MEMPLL			16
+#define CLK_TOP_DMPLL			17
+#define CLK_TOP_SYSPLL_D2		18
+#define CLK_TOP_SYSPLL1_D2		19
+#define CLK_TOP_SYSPLL1_D4		20
+#define CLK_TOP_SYSPLL1_D8		21
+#define CLK_TOP_SYSPLL2_D4		22
+#define CLK_TOP_SYSPLL2_D8		23
+#define CLK_TOP_SYSPLL_D5		24
+#define CLK_TOP_SYSPLL3_D2		25
+#define CLK_TOP_SYSPLL3_D4		26
+#define CLK_TOP_SYSPLL4_D2		27
+#define CLK_TOP_SYSPLL4_D4		28
+#define CLK_TOP_SYSPLL4_D16		29
+#define CLK_TOP_UNIVPLL			30
+#define CLK_TOP_UNIVPLL_D2		31
+#define CLK_TOP_UNIVPLL1_D2		32
+#define CLK_TOP_UNIVPLL1_D4		33
+#define CLK_TOP_UNIVPLL1_D8		34
+#define CLK_TOP_UNIVPLL1_D16		35
+#define CLK_TOP_UNIVPLL2_D2		36
+#define CLK_TOP_UNIVPLL2_D4		37
+#define CLK_TOP_UNIVPLL2_D8		38
+#define CLK_TOP_UNIVPLL2_D16		39
+#define CLK_TOP_UNIVPLL_D5		40
+#define CLK_TOP_UNIVPLL3_D2		41
+#define CLK_TOP_UNIVPLL3_D4		42
+#define CLK_TOP_UNIVPLL3_D16		43
+#define CLK_TOP_UNIVPLL_D7		44
+#define CLK_TOP_UNIVPLL_D80_D4		45
+#define CLK_TOP_UNIV48M			46
+#define CLK_TOP_SGMIIPLL		47
+#define CLK_TOP_SGMIIPLL_D2		48
+#define CLK_TOP_AUD1PLL			49
+#define CLK_TOP_AUD2PLL			50
+#define CLK_TOP_AUD_I2S2_MCK		51
+#define CLK_TOP_TO_USB3_REF		52
+#define CLK_TOP_PCIE1_MAC_EN		53
+#define CLK_TOP_PCIE0_MAC_EN		54
+#define CLK_TOP_ETH_500M		55
+#define CLK_TOP_AXI_SEL			56
+#define CLK_TOP_MEM_SEL			57
+#define CLK_TOP_DDRPHYCFG_SEL		58
+#define CLK_TOP_ETH_SEL			59
+#define CLK_TOP_PWM_SEL			60
+#define CLK_TOP_F10M_REF_SEL		61
+#define CLK_TOP_NFI_INFRA_SEL		62
+#define CLK_TOP_FLASH_SEL		63
+#define CLK_TOP_UART_SEL		64
+#define CLK_TOP_SPI0_SEL		65
+#define CLK_TOP_SPI1_SEL		66
+#define CLK_TOP_MSDC50_0_SEL		67
+#define CLK_TOP_MSDC30_0_SEL		68
+#define CLK_TOP_MSDC30_1_SEL		69
+#define CLK_TOP_A1SYS_HP_SEL		70
+#define CLK_TOP_A2SYS_HP_SEL		71
+#define CLK_TOP_INTDIR_SEL		72
+#define CLK_TOP_AUD_INTBUS_SEL		73
+#define CLK_TOP_PMICSPI_SEL		74
+#define CLK_TOP_SCP_SEL			75
+#define CLK_TOP_ATB_SEL			76
+#define CLK_TOP_HIF_SEL			77
+#define CLK_TOP_AUDIO_SEL		78
+#define CLK_TOP_U2_SEL			79
+#define CLK_TOP_AUD1_SEL		80
+#define CLK_TOP_AUD2_SEL		81
+#define CLK_TOP_IRRX_SEL		82
+#define CLK_TOP_IRTX_SEL		83
+#define CLK_TOP_ASM_L_SEL		84
+#define CLK_TOP_ASM_M_SEL		85
+#define CLK_TOP_ASM_H_SEL		86
+#define CLK_TOP_APLL1_SEL		87
+#define CLK_TOP_APLL2_SEL		88
+#define CLK_TOP_I2S0_MCK_SEL		89
+#define CLK_TOP_I2S1_MCK_SEL		90
+#define CLK_TOP_I2S2_MCK_SEL		91
+#define CLK_TOP_I2S3_MCK_SEL		92
+#define CLK_TOP_APLL1_DIV		93
+#define CLK_TOP_APLL2_DIV		94
+#define CLK_TOP_I2S0_MCK_DIV		95
+#define CLK_TOP_I2S1_MCK_DIV		96
+#define CLK_TOP_I2S2_MCK_DIV		97
+#define CLK_TOP_I2S3_MCK_DIV		98
+#define CLK_TOP_A1SYS_HP_DIV		99
+#define CLK_TOP_A2SYS_HP_DIV		100
+#define CLK_TOP_APLL1_DIV_PD		101
+#define CLK_TOP_APLL2_DIV_PD		102
+#define CLK_TOP_I2S0_MCK_DIV_PD		103
+#define CLK_TOP_I2S1_MCK_DIV_PD		104
+#define CLK_TOP_I2S2_MCK_DIV_PD		105
+#define CLK_TOP_I2S3_MCK_DIV_PD		106
+#define CLK_TOP_A1SYS_HP_DIV_PD		107
+#define CLK_TOP_A2SYS_HP_DIV_PD		108
+#define CLK_TOP_NR_CLK			109
+
+/* INFRACFG */
+
+#define CLK_INFRA_MUX1_SEL		0
+#define CLK_INFRA_DBGCLK_PD		1
+#define CLK_INFRA_AUDIO_PD		2
+#define CLK_INFRA_IRRX_PD		3
+#define CLK_INFRA_APXGPT_PD		4
+#define CLK_INFRA_PMIC_PD		5
+#define CLK_INFRA_TRNG			6
+#define CLK_INFRA_NR_CLK		7
+
+/* PERICFG */
+
+#define CLK_PERIBUS_SEL			0
+#define CLK_PERI_THERM_PD		1
+#define CLK_PERI_PWM1_PD		2
+#define CLK_PERI_PWM2_PD		3
+#define CLK_PERI_PWM3_PD		4
+#define CLK_PERI_PWM4_PD		5
+#define CLK_PERI_PWM5_PD		6
+#define CLK_PERI_PWM6_PD		7
+#define CLK_PERI_PWM7_PD		8
+#define CLK_PERI_PWM_PD			9
+#define CLK_PERI_AP_DMA_PD		10
+#define CLK_PERI_MSDC30_0_PD		11
+#define CLK_PERI_MSDC30_1_PD		12
+#define CLK_PERI_UART0_PD		13
+#define CLK_PERI_UART1_PD		14
+#define CLK_PERI_UART2_PD		15
+#define CLK_PERI_UART3_PD		16
+#define CLK_PERI_UART4_PD		17
+#define CLK_PERI_BTIF_PD		18
+#define CLK_PERI_I2C0_PD		19
+#define CLK_PERI_I2C1_PD		20
+#define CLK_PERI_I2C2_PD		21
+#define CLK_PERI_SPI1_PD		22
+#define CLK_PERI_AUXADC_PD		23
+#define CLK_PERI_SPI0_PD		24
+#define CLK_PERI_SNFI_PD		25
+#define CLK_PERI_NFI_PD			26
+#define CLK_PERI_NFIECC_PD		27
+#define CLK_PERI_FLASH_PD		28
+#define CLK_PERI_IRTX_PD		29
+#define CLK_PERI_NR_CLK			30
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIV2PLL		2
+#define CLK_APMIXED_ETH1PLL		3
+#define CLK_APMIXED_ETH2PLL		4
+#define CLK_APMIXED_AUD1PLL		5
+#define CLK_APMIXED_AUD2PLL		6
+#define CLK_APMIXED_TRGPLL		7
+#define CLK_APMIXED_SGMIPLL		8
+#define CLK_APMIXED_MAIN_CORE_EN	9
+#define CLK_APMIXED_NR_CLK		10
+
+/* AUDIOSYS */
+
+#define CLK_AUDIO_AFE			0
+#define CLK_AUDIO_HDMI			1
+#define CLK_AUDIO_SPDF			2
+#define CLK_AUDIO_APLL			3
+#define CLK_AUDIO_I2SIN1		4
+#define CLK_AUDIO_I2SIN2		5
+#define CLK_AUDIO_I2SIN3		6
+#define CLK_AUDIO_I2SIN4		7
+#define CLK_AUDIO_I2SO1			8
+#define CLK_AUDIO_I2SO2			9
+#define CLK_AUDIO_I2SO3			10
+#define CLK_AUDIO_I2SO4			11
+#define CLK_AUDIO_ASRCI1		12
+#define CLK_AUDIO_ASRCI2		13
+#define CLK_AUDIO_ASRCO1		14
+#define CLK_AUDIO_ASRCO2		15
+#define CLK_AUDIO_INTDIR		16
+#define CLK_AUDIO_A1SYS			17
+#define CLK_AUDIO_A2SYS			18
+#define CLK_AUDIO_UL1			19
+#define CLK_AUDIO_UL2			20
+#define CLK_AUDIO_UL3			21
+#define CLK_AUDIO_UL4			22
+#define CLK_AUDIO_UL5			23
+#define CLK_AUDIO_UL6			24
+#define CLK_AUDIO_DL1			25
+#define CLK_AUDIO_DL2			26
+#define CLK_AUDIO_DL3			27
+#define CLK_AUDIO_DL4			28
+#define CLK_AUDIO_DL5			29
+#define CLK_AUDIO_DL6			30
+#define CLK_AUDIO_DLMCH			31
+#define CLK_AUDIO_ARB1			32
+#define CLK_AUDIO_AWB			33
+#define CLK_AUDIO_AWB2			34
+#define CLK_AUDIO_DAI			35
+#define CLK_AUDIO_MOD			36
+#define CLK_AUDIO_ASRCI3		37
+#define CLK_AUDIO_ASRCI4		38
+#define CLK_AUDIO_ASRCO3		39
+#define CLK_AUDIO_ASRCO4		40
+#define CLK_AUDIO_MEM_ASRC1		41
+#define CLK_AUDIO_MEM_ASRC2		42
+#define CLK_AUDIO_MEM_ASRC3		43
+#define CLK_AUDIO_MEM_ASRC4		44
+#define CLK_AUDIO_MEM_ASRC5		45
+#define CLK_AUDIO_AFE_CONN		46
+#define CLK_AUDIO_NR_CLK		47
+
+/* SSUSBSYS */
+
+#define CLK_SSUSB_U2_PHY_1P_EN		0
+#define CLK_SSUSB_U2_PHY_EN		1
+#define CLK_SSUSB_REF_EN		2
+#define CLK_SSUSB_SYS_EN		3
+#define CLK_SSUSB_MCU_EN		4
+#define CLK_SSUSB_DMA_EN		5
+#define CLK_SSUSB_NR_CLK		6
+
+/* PCIESYS */
+
+#define CLK_PCIE_P1_AUX_EN		0
+#define CLK_PCIE_P1_OBFF_EN		1
+#define CLK_PCIE_P1_AHB_EN		2
+#define CLK_PCIE_P1_AXI_EN		3
+#define CLK_PCIE_P1_MAC_EN		4
+#define CLK_PCIE_P1_PIPE_EN		5
+#define CLK_PCIE_P0_AUX_EN		6
+#define CLK_PCIE_P0_OBFF_EN		7
+#define CLK_PCIE_P0_AHB_EN		8
+#define CLK_PCIE_P0_AXI_EN		9
+#define CLK_PCIE_P0_MAC_EN		10
+#define CLK_PCIE_P0_PIPE_EN		11
+#define CLK_SATA_AHB_EN			12
+#define CLK_SATA_AXI_EN			13
+#define CLK_SATA_ASIC_EN		14
+#define CLK_SATA_RBC_EN			15
+#define CLK_SATA_PM_EN			16
+#define CLK_PCIE_NR_CLK			17
+
+/* ETHSYS */
+
+#define CLK_ETH_HSDMA_EN		0
+#define CLK_ETH_ESW_EN			1
+#define CLK_ETH_GP2_EN			2
+#define CLK_ETH_GP1_EN			3
+#define CLK_ETH_GP0_EN			4
+#define CLK_ETH_NR_CLK			5
+
+/* SGMIISYS */
+
+#define CLK_SGMII_TX250M_EN		0
+#define CLK_SGMII_RX250M_EN		1
+#define CLK_SGMII_CDR_REF		2
+#define CLK_SGMII_CDR_FB		3
+#define CLK_SGMII_NR_CLK		4
+
+#endif /* _DT_BINDINGS_CLK_MT7622_H */
+

include/dt-bindings/clock/mt7629-clk.h

@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7629_H
+#define _DT_BINDINGS_CLK_MT7629_H
+
+/* TOPCKGEN */
+#define CLK_TOP_TO_U2_PHY		0
+#define CLK_TOP_TO_U2_PHY_1P		1
+#define CLK_TOP_PCIE0_PIPE_EN		2
+#define CLK_TOP_PCIE1_PIPE_EN		3
+#define CLK_TOP_SSUSB_TX250M		4
+#define CLK_TOP_SSUSB_EQ_RX250M		5
+#define CLK_TOP_SSUSB_CDR_REF		6
+#define CLK_TOP_SSUSB_CDR_FB		7
+#define CLK_TOP_SATA_ASIC		8
+#define CLK_TOP_SATA_RBC		9
+#define CLK_TOP_TO_USB3_SYS		10
+#define CLK_TOP_P1_1MHZ			11
+#define CLK_TOP_4MHZ			12
+#define CLK_TOP_P0_1MHZ			13
+#define CLK_TOP_ETH_500M		14
+#define CLK_TOP_TXCLK_SRC_PRE		15
+#define CLK_TOP_RTC			16
+#define CLK_TOP_PWM_QTR_26M		17
+#define CLK_TOP_CPUM_TCK_IN		18
+#define CLK_TOP_TO_USB3_DA_TOP		19
+#define CLK_TOP_MEMPLL			20
+#define CLK_TOP_DMPLL			21
+#define CLK_TOP_DMPLL_D4		22
+#define CLK_TOP_DMPLL_D8		23
+#define CLK_TOP_SYSPLL_D2		24
+#define CLK_TOP_SYSPLL1_D2		25
+#define CLK_TOP_SYSPLL1_D4		26
+#define CLK_TOP_SYSPLL1_D8		27
+#define CLK_TOP_SYSPLL1_D16		28
+#define CLK_TOP_SYSPLL2_D2		29
+#define CLK_TOP_SYSPLL2_D4		30
+#define CLK_TOP_SYSPLL2_D8		31
+#define CLK_TOP_SYSPLL_D5		32
+#define CLK_TOP_SYSPLL3_D2		33
+#define CLK_TOP_SYSPLL3_D4		34
+#define CLK_TOP_SYSPLL_D7		35
+#define CLK_TOP_SYSPLL4_D2		36
+#define CLK_TOP_SYSPLL4_D4		37
+#define CLK_TOP_SYSPLL4_D16		38
+#define CLK_TOP_UNIVPLL			39
+#define CLK_TOP_UNIVPLL1_D2		40
+#define CLK_TOP_UNIVPLL1_D4		41
+#define CLK_TOP_UNIVPLL1_D8		42
+#define CLK_TOP_UNIVPLL_D3		43
+#define CLK_TOP_UNIVPLL2_D2		44
+#define CLK_TOP_UNIVPLL2_D4		45
+#define CLK_TOP_UNIVPLL2_D8		46
+#define CLK_TOP_UNIVPLL2_D16		47
+#define CLK_TOP_UNIVPLL_D5		48
+#define CLK_TOP_UNIVPLL3_D2		49
+#define CLK_TOP_UNIVPLL3_D4		50
+#define CLK_TOP_UNIVPLL3_D16		51
+#define CLK_TOP_UNIVPLL_D7		52
+#define CLK_TOP_UNIVPLL_D80_D4		53
+#define CLK_TOP_UNIV48M			54
+#define CLK_TOP_SGMIIPLL_D2		55
+#define CLK_TOP_CLKXTAL_D4		56
+#define CLK_TOP_HD_FAXI			57
+#define CLK_TOP_FAXI			58
+#define CLK_TOP_F_FAUD_INTBUS		59
+#define CLK_TOP_AP2WBHIF_HCLK		60
+#define CLK_TOP_10M_INFRAO		61
+#define CLK_TOP_MSDC30_1		62
+#define CLK_TOP_SPI			63
+#define CLK_TOP_SF			64
+#define CLK_TOP_FLASH			65
+#define CLK_TOP_TO_USB3_REF		66
+#define CLK_TOP_TO_USB3_MCU		67
+#define CLK_TOP_TO_USB3_DMA		68
+#define CLK_TOP_FROM_TOP_AHB		69
+#define CLK_TOP_FROM_TOP_AXI		70
+#define CLK_TOP_PCIE1_MAC_EN		71
+#define CLK_TOP_PCIE0_MAC_EN		72
+#define CLK_TOP_AXI_SEL			73
+#define CLK_TOP_MEM_SEL			74
+#define CLK_TOP_DDRPHYCFG_SEL		75
+#define CLK_TOP_ETH_SEL			76
+#define CLK_TOP_PWM_SEL			77
+#define CLK_TOP_F10M_REF_SEL		78
+#define CLK_TOP_NFI_INFRA_SEL		79
+#define CLK_TOP_FLASH_SEL		80
+#define CLK_TOP_UART_SEL		81
+#define CLK_TOP_SPI0_SEL		82
+#define CLK_TOP_SPI1_SEL		83
+#define CLK_TOP_MSDC50_0_SEL		84
+#define CLK_TOP_MSDC30_0_SEL		85
+#define CLK_TOP_MSDC30_1_SEL		86
+#define CLK_TOP_AP2WBMCU_SEL		87
+#define CLK_TOP_AP2WBHIF_SEL		88
+#define CLK_TOP_AUDIO_SEL		89
+#define CLK_TOP_AUD_INTBUS_SEL		90
+#define CLK_TOP_PMICSPI_SEL		91
+#define CLK_TOP_SCP_SEL			92
+#define CLK_TOP_ATB_SEL			93
+#define CLK_TOP_HIF_SEL			94
+#define CLK_TOP_SATA_SEL		95
+#define CLK_TOP_U2_SEL			96
+#define CLK_TOP_AUD1_SEL		97
+#define CLK_TOP_AUD2_SEL		98
+#define CLK_TOP_IRRX_SEL		99
+#define CLK_TOP_IRTX_SEL		100
+#define CLK_TOP_SATA_MCU_SEL		101
+#define CLK_TOP_PCIE0_MCU_SEL		102
+#define CLK_TOP_PCIE1_MCU_SEL		103
+#define CLK_TOP_SSUSB_MCU_SEL		104
+#define CLK_TOP_CRYPTO_SEL		105
+#define CLK_TOP_SGMII_REF_1_SEL		106
+#define CLK_TOP_10M_SEL			107
+#define CLK_TOP_NR_CLK			108
+
+/* INFRACFG */
+#define CLK_INFRA_MUX1_SEL		0
+#define CLK_INFRA_DBGCLK_PD		1
+#define CLK_INFRA_TRNG_PD		2
+#define CLK_INFRA_DEVAPC_PD		3
+#define CLK_INFRA_APXGPT_PD		4
+#define CLK_INFRA_SEJ_PD		5
+#define CLK_INFRA_NR_CLK		6
+
+/* PERICFG */
+#define CLK_PERIBUS_SEL			0
+#define CLK_PERI_PWM1_PD		1
+#define CLK_PERI_PWM2_PD		2
+#define CLK_PERI_PWM3_PD		3
+#define CLK_PERI_PWM4_PD		4
+#define CLK_PERI_PWM5_PD		5
+#define CLK_PERI_PWM6_PD		6
+#define CLK_PERI_PWM7_PD		7
+#define CLK_PERI_PWM_PD			8
+#define CLK_PERI_AP_DMA_PD		9
+#define CLK_PERI_MSDC30_1_PD		10
+#define CLK_PERI_UART0_PD		11
+#define CLK_PERI_UART1_PD		12
+#define CLK_PERI_UART2_PD		13
+#define CLK_PERI_UART3_PD		14
+#define CLK_PERI_BTIF_PD		15
+#define CLK_PERI_I2C0_PD		16
+#define CLK_PERI_SPI0_PD		17
+#define CLK_PERI_SNFI_PD		18
+#define CLK_PERI_NFI_PD			19
+#define CLK_PERI_NFIECC_PD		20
+#define CLK_PERI_FLASH_PD		21
+#define CLK_PERI_NR_CLK			22
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIV2PLL		2
+#define CLK_APMIXED_ETH1PLL		3
+#define CLK_APMIXED_ETH2PLL		4
+#define CLK_APMIXED_SGMIPLL		5
+#define CLK_APMIXED_MAIN_CORE_EN	6
+#define CLK_APMIXED_NR_CLK		7
+
+/* SSUSBSYS */
+#define CLK_SSUSB_U2_PHY_1P_EN		0
+#define CLK_SSUSB_U2_PHY_EN		1
+#define CLK_SSUSB_REF_EN		2
+#define CLK_SSUSB_SYS_EN		3
+#define CLK_SSUSB_MCU_EN		4
+#define CLK_SSUSB_DMA_EN		5
+#define CLK_SSUSB_NR_CLK		6
+
+/* PCIESYS */
+#define CLK_PCIE_P1_AUX_EN		0
+#define CLK_PCIE_P1_OBFF_EN		1
+#define CLK_PCIE_P1_AHB_EN		2
+#define CLK_PCIE_P1_AXI_EN		3
+#define CLK_PCIE_P1_MAC_EN		4
+#define CLK_PCIE_P1_PIPE_EN		5
+#define CLK_PCIE_P0_AUX_EN		6
+#define CLK_PCIE_P0_OBFF_EN		7
+#define CLK_PCIE_P0_AHB_EN		8
+#define CLK_PCIE_P0_AXI_EN		9
+#define CLK_PCIE_P0_MAC_EN		10
+#define CLK_PCIE_P0_PIPE_EN		11
+#define CLK_PCIE_NR_CLK			12
+
+/* ETHSYS */
+#define CLK_ETH_FE_EN			0
+#define CLK_ETH_GP2_EN			1
+#define CLK_ETH_GP1_EN			2
+#define CLK_ETH_GP0_EN			3
+#define CLK_ETH_ESW_EN			4
+#define CLK_ETH_NR_CLK			5
+
+/* SGMIISYS */
+#define CLK_SGMII_TX_EN			0
+#define CLK_SGMII_RX_EN			1
+#define CLK_SGMII_CDR_REF		2
+#define CLK_SGMII_CDR_FB		3
+#define CLK_SGMII_NR_CLK		4
+
+#endif /* _DT_BINDINGS_CLK_MT7629_H */

include/dt-bindings/clock/mt8135-clk.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8135_H
+#define _DT_BINDINGS_CLK_MT8135_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_DSI0_LNTC_DSICLK	1
+#define CLK_TOP_HDMITX_CLKDIG_CTS	2
+#define CLK_TOP_CLKPH_MCK		3
+#define CLK_TOP_CPUM_TCK_IN		4
+#define CLK_TOP_MAINPLL_806M		5
+#define CLK_TOP_MAINPLL_537P3M		6
+#define CLK_TOP_MAINPLL_322P4M		7
+#define CLK_TOP_MAINPLL_230P3M		8
+#define CLK_TOP_UNIVPLL_624M		9
+#define CLK_TOP_UNIVPLL_416M		10
+#define CLK_TOP_UNIVPLL_249P6M		11
+#define CLK_TOP_UNIVPLL_178P3M		12
+#define CLK_TOP_UNIVPLL_48M		13
+#define CLK_TOP_MMPLL_D2		14
+#define CLK_TOP_MMPLL_D3		15
+#define CLK_TOP_MMPLL_D5		16
+#define CLK_TOP_MMPLL_D7		17
+#define CLK_TOP_MMPLL_D4		18
+#define CLK_TOP_MMPLL_D6		19
+#define CLK_TOP_SYSPLL_D2		20
+#define CLK_TOP_SYSPLL_D4		21
+#define CLK_TOP_SYSPLL_D6		22
+#define CLK_TOP_SYSPLL_D8		23
+#define CLK_TOP_SYSPLL_D10		24
+#define CLK_TOP_SYSPLL_D12		25
+#define CLK_TOP_SYSPLL_D16		26
+#define CLK_TOP_SYSPLL_D24		27
+#define CLK_TOP_SYSPLL_D3		28
+#define CLK_TOP_SYSPLL_D2P5		29
+#define CLK_TOP_SYSPLL_D5		30
+#define CLK_TOP_SYSPLL_D3P5		31
+#define CLK_TOP_UNIVPLL1_D2		32
+#define CLK_TOP_UNIVPLL1_D4		33
+#define CLK_TOP_UNIVPLL1_D6		34
+#define CLK_TOP_UNIVPLL1_D8		35
+#define CLK_TOP_UNIVPLL1_D10		36
+#define CLK_TOP_UNIVPLL2_D2		37
+#define CLK_TOP_UNIVPLL2_D4		38
+#define CLK_TOP_UNIVPLL2_D6		39
+#define CLK_TOP_UNIVPLL2_D8		40
+#define CLK_TOP_UNIVPLL_D3		41
+#define CLK_TOP_UNIVPLL_D5		42
+#define CLK_TOP_UNIVPLL_D7		43
+#define CLK_TOP_UNIVPLL_D10		44
+#define CLK_TOP_UNIVPLL_D26		45
+#define CLK_TOP_APLL			46
+#define CLK_TOP_APLL_D4			47
+#define CLK_TOP_APLL_D8			48
+#define CLK_TOP_APLL_D16		49
+#define CLK_TOP_APLL_D24		50
+#define CLK_TOP_LVDSPLL_D2		51
+#define CLK_TOP_LVDSPLL_D4		52
+#define CLK_TOP_LVDSPLL_D8		53
+#define CLK_TOP_LVDSTX_CLKDIG_CT	54
+#define CLK_TOP_VPLL_DPIX		55
+#define CLK_TOP_TVHDMI_H		56
+#define CLK_TOP_HDMITX_CLKDIG_D2	57
+#define CLK_TOP_HDMITX_CLKDIG_D3	58
+#define CLK_TOP_TVHDMI_D2		59
+#define CLK_TOP_TVHDMI_D4		60
+#define CLK_TOP_MEMPLL_MCK_D4		61
+#define CLK_TOP_AXI_SEL			62
+#define CLK_TOP_SMI_SEL			63
+#define CLK_TOP_MFG_SEL			64
+#define CLK_TOP_IRDA_SEL		65
+#define CLK_TOP_CAM_SEL			66
+#define CLK_TOP_AUD_INTBUS_SEL		67
+#define CLK_TOP_JPG_SEL			68
+#define CLK_TOP_DISP_SEL		69
+#define CLK_TOP_MSDC30_1_SEL		70
+#define CLK_TOP_MSDC30_2_SEL		71
+#define CLK_TOP_MSDC30_3_SEL		72
+#define CLK_TOP_MSDC30_4_SEL		73
+#define CLK_TOP_USB20_SEL		74
+#define CLK_TOP_VENC_SEL		75
+#define CLK_TOP_SPI_SEL			76
+#define CLK_TOP_UART_SEL		77
+#define CLK_TOP_MEM_SEL			78
+#define CLK_TOP_CAMTG_SEL		79
+#define CLK_TOP_AUDIO_SEL		80
+#define CLK_TOP_FIX_SEL			81
+#define CLK_TOP_VDEC_SEL		82
+#define CLK_TOP_DDRPHYCFG_SEL		83
+#define CLK_TOP_DPILVDS_SEL		84
+#define CLK_TOP_PMICSPI_SEL		85
+#define CLK_TOP_MSDC30_0_SEL		86
+#define CLK_TOP_SMI_MFG_AS_SEL		87
+#define CLK_TOP_GCPU_SEL		88
+#define CLK_TOP_DPI1_SEL		89
+#define CLK_TOP_CCI_SEL			90
+#define CLK_TOP_APLL_SEL		91
+#define CLK_TOP_HDMIPLL_SEL		92
+#define CLK_TOP_NR_CLK			93
+
+/* APMIXED_SYS */
+
+#define CLK_APMIXED_ARMPLL1		1
+#define CLK_APMIXED_ARMPLL2		2
+#define CLK_APMIXED_MAINPLL		3
+#define CLK_APMIXED_UNIVPLL		4
+#define CLK_APMIXED_MMPLL		5
+#define CLK_APMIXED_MSDCPLL		6
+#define CLK_APMIXED_TVDPLL		7
+#define CLK_APMIXED_LVDSPLL		8
+#define CLK_APMIXED_AUDPLL		9
+#define CLK_APMIXED_VDECPLL		10
+#define CLK_APMIXED_NR_CLK		11
+
+/* INFRA_SYS */
+
+#define CLK_INFRA_PMIC_WRAP		1
+#define CLK_INFRA_PMICSPI		2
+#define CLK_INFRA_CCIF1_AP_CTRL		3
+#define CLK_INFRA_CCIF0_AP_CTRL		4
+#define CLK_INFRA_KP			5
+#define CLK_INFRA_CPUM			6
+#define CLK_INFRA_M4U			7
+#define CLK_INFRA_MFGAXI		8
+#define CLK_INFRA_DEVAPC		9
+#define CLK_INFRA_AUDIO			10
+#define CLK_INFRA_MFG_BUS		11
+#define CLK_INFRA_SMI			12
+#define CLK_INFRA_DBGCLK		13
+#define CLK_INFRA_NR_CLK		14
+
+/* PERI_SYS */
+
+#define CLK_PERI_I2C5			1
+#define CLK_PERI_I2C4			2
+#define CLK_PERI_I2C3			3
+#define CLK_PERI_I2C2			4
+#define CLK_PERI_I2C1			5
+#define CLK_PERI_I2C0			6
+#define CLK_PERI_UART3			7
+#define CLK_PERI_UART2			8
+#define CLK_PERI_UART1			9
+#define CLK_PERI_UART0			10
+#define CLK_PERI_IRDA			11
+#define CLK_PERI_NLI			12
+#define CLK_PERI_MD_HIF			13
+#define CLK_PERI_AP_HIF			14
+#define CLK_PERI_MSDC30_3		15
+#define CLK_PERI_MSDC30_2		16
+#define CLK_PERI_MSDC30_1		17
+#define CLK_PERI_MSDC20_2		18
+#define CLK_PERI_MSDC20_1		19
+#define CLK_PERI_AP_DMA			20
+#define CLK_PERI_USB1			21
+#define CLK_PERI_USB0			22
+#define CLK_PERI_PWM			23
+#define CLK_PERI_PWM7			24
+#define CLK_PERI_PWM6			25
+#define CLK_PERI_PWM5			26
+#define CLK_PERI_PWM4			27
+#define CLK_PERI_PWM3			28
+#define CLK_PERI_PWM2			29
+#define CLK_PERI_PWM1			30
+#define CLK_PERI_THERM			31
+#define CLK_PERI_NFI			32
+#define CLK_PERI_USBSLV			33
+#define CLK_PERI_USB1_MCU		34
+#define CLK_PERI_USB0_MCU		35
+#define CLK_PERI_GCPU			36
+#define CLK_PERI_FHCTL			37
+#define CLK_PERI_SPI1			38
+#define CLK_PERI_AUXADC			39
+#define CLK_PERI_PERI_PWRAP		40
+#define CLK_PERI_I2C6			41
+#define CLK_PERI_UART0_SEL		42
+#define CLK_PERI_UART1_SEL		43
+#define CLK_PERI_UART2_SEL		44
+#define CLK_PERI_UART3_SEL		45
+#define CLK_PERI_NR_CLK			46
+
+#endif /* _DT_BINDINGS_CLK_MT8135_H */

include/dt-bindings/clock/mt8173-clk.h

@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8173_H
+#define _DT_BINDINGS_CLK_MT8173_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLKPH_MCK_O		1
+#define CLK_TOP_USB_SYSPLL_125M		3
+#define CLK_TOP_HDMITX_DIG_CTS		4
+#define CLK_TOP_ARMCA7PLL_754M		5
+#define CLK_TOP_ARMCA7PLL_502M		6
+#define CLK_TOP_MAIN_H546M		7
+#define CLK_TOP_MAIN_H364M		8
+#define CLK_TOP_MAIN_H218P4M		9
+#define CLK_TOP_MAIN_H156M		10
+#define CLK_TOP_TVDPLL_445P5M		11
+#define CLK_TOP_TVDPLL_594M		12
+#define CLK_TOP_UNIV_624M		13
+#define CLK_TOP_UNIV_416M		14
+#define CLK_TOP_UNIV_249P6M		15
+#define CLK_TOP_UNIV_178P3M		16
+#define CLK_TOP_UNIV_48M		17
+#define CLK_TOP_CLKRTC_EXT		18
+#define CLK_TOP_CLKRTC_INT		19
+#define CLK_TOP_FPC			20
+#define CLK_TOP_HDMITXPLL_D2		21
+#define CLK_TOP_HDMITXPLL_D3		22
+#define CLK_TOP_ARMCA7PLL_D2		23
+#define CLK_TOP_ARMCA7PLL_D3		24
+#define CLK_TOP_APLL1			25
+#define CLK_TOP_APLL2			26
+#define CLK_TOP_DMPLL			27
+#define CLK_TOP_DMPLL_D2		28
+#define CLK_TOP_DMPLL_D4		29
+#define CLK_TOP_DMPLL_D8		30
+#define CLK_TOP_DMPLL_D16		31
+#define CLK_TOP_LVDSPLL_D2		32
+#define CLK_TOP_LVDSPLL_D4		33
+#define CLK_TOP_LVDSPLL_D8		34
+#define CLK_TOP_MMPLL			35
+#define CLK_TOP_MMPLL_D2		36
+#define CLK_TOP_MSDCPLL			37
+#define CLK_TOP_MSDCPLL_D2		38
+#define CLK_TOP_MSDCPLL_D4		39
+#define CLK_TOP_MSDCPLL2		40
+#define CLK_TOP_MSDCPLL2_D2		41
+#define CLK_TOP_MSDCPLL2_D4		42
+#define CLK_TOP_SYSPLL_D2		43
+#define CLK_TOP_SYSPLL1_D2		44
+#define CLK_TOP_SYSPLL1_D4		45
+#define CLK_TOP_SYSPLL1_D8		46
+#define CLK_TOP_SYSPLL1_D16		47
+#define CLK_TOP_SYSPLL_D3		48
+#define CLK_TOP_SYSPLL2_D2		49
+#define CLK_TOP_SYSPLL2_D4		50
+#define CLK_TOP_SYSPLL_D5		51
+#define CLK_TOP_SYSPLL3_D2		52
+#define CLK_TOP_SYSPLL3_D4		53
+#define CLK_TOP_SYSPLL_D7		54
+#define CLK_TOP_SYSPLL4_D2		55
+#define CLK_TOP_SYSPLL4_D4		56
+#define CLK_TOP_TVDPLL			57
+#define CLK_TOP_TVDPLL_D2		58
+#define CLK_TOP_TVDPLL_D4		59
+#define CLK_TOP_TVDPLL_D8		60
+#define CLK_TOP_TVDPLL_D16		61
+#define CLK_TOP_UNIVPLL_D2		62
+#define CLK_TOP_UNIVPLL1_D2		63
+#define CLK_TOP_UNIVPLL1_D4		64
+#define CLK_TOP_UNIVPLL1_D8		65
+#define CLK_TOP_UNIVPLL_D3		66
+#define CLK_TOP_UNIVPLL2_D2		67
+#define CLK_TOP_UNIVPLL2_D4		68
+#define CLK_TOP_UNIVPLL2_D8		69
+#define CLK_TOP_UNIVPLL_D5		70
+#define CLK_TOP_UNIVPLL3_D2		71
+#define CLK_TOP_UNIVPLL3_D4		72
+#define CLK_TOP_UNIVPLL3_D8		73
+#define CLK_TOP_UNIVPLL_D7		74
+#define CLK_TOP_UNIVPLL_D26		75
+#define CLK_TOP_UNIVPLL_D52		76
+#define CLK_TOP_VCODECPLL		77
+#define CLK_TOP_VCODECPLL_370P5		78
+#define CLK_TOP_VENCPLL			79
+#define CLK_TOP_VENCPLL_D2		80
+#define CLK_TOP_VENCPLL_D4		81
+#define CLK_TOP_AXI_SEL			82
+#define CLK_TOP_MEM_SEL			83
+#define CLK_TOP_DDRPHYCFG_SEL		84
+#define CLK_TOP_MM_SEL			85
+#define CLK_TOP_PWM_SEL			86
+#define CLK_TOP_VDEC_SEL		87
+#define CLK_TOP_VENC_SEL		88
+#define CLK_TOP_MFG_SEL			89
+#define CLK_TOP_CAMTG_SEL		90
+#define CLK_TOP_UART_SEL		91
+#define CLK_TOP_SPI_SEL			92
+#define CLK_TOP_USB20_SEL		93
+#define CLK_TOP_USB30_SEL		94
+#define CLK_TOP_MSDC50_0_H_SEL		95
+#define CLK_TOP_MSDC50_0_SEL		96
+#define CLK_TOP_MSDC30_1_SEL		97
+#define CLK_TOP_MSDC30_2_SEL		98
+#define CLK_TOP_MSDC30_3_SEL		99
+#define CLK_TOP_AUDIO_SEL		100
+#define CLK_TOP_AUD_INTBUS_SEL		101
+#define CLK_TOP_PMICSPI_SEL		102
+#define CLK_TOP_SCP_SEL			103
+#define CLK_TOP_ATB_SEL			104
+#define CLK_TOP_VENC_LT_SEL		105
+#define CLK_TOP_DPI0_SEL		106
+#define CLK_TOP_IRDA_SEL		107
+#define CLK_TOP_CCI400_SEL		108
+#define CLK_TOP_AUD_1_SEL		109
+#define CLK_TOP_AUD_2_SEL		110
+#define CLK_TOP_MEM_MFG_IN_SEL		111
+#define CLK_TOP_AXI_MFG_IN_SEL		112
+#define CLK_TOP_SCAM_SEL		113
+#define CLK_TOP_SPINFI_IFR_SEL		114
+#define CLK_TOP_HDMI_SEL		115
+#define CLK_TOP_DPILVDS_SEL		116
+#define CLK_TOP_MSDC50_2_H_SEL		117
+#define CLK_TOP_HDCP_SEL		118
+#define CLK_TOP_HDCP_24M_SEL		119
+#define CLK_TOP_RTC_SEL			120
+#define CLK_TOP_APLL1_DIV0		121
+#define CLK_TOP_APLL1_DIV1		122
+#define CLK_TOP_APLL1_DIV2		123
+#define CLK_TOP_APLL1_DIV3		124
+#define CLK_TOP_APLL1_DIV4		125
+#define CLK_TOP_APLL1_DIV5		126
+#define CLK_TOP_APLL2_DIV0		127
+#define CLK_TOP_APLL2_DIV1		128
+#define CLK_TOP_APLL2_DIV2		129
+#define CLK_TOP_APLL2_DIV3		130
+#define CLK_TOP_APLL2_DIV4		131
+#define CLK_TOP_APLL2_DIV5		132
+#define CLK_TOP_I2S0_M_SEL		133
+#define CLK_TOP_I2S1_M_SEL		134
+#define CLK_TOP_I2S2_M_SEL		135
+#define CLK_TOP_I2S3_M_SEL		136
+#define CLK_TOP_I2S3_B_SEL		137
+#define CLK_TOP_DSI0_DIG		138
+#define CLK_TOP_DSI1_DIG		139
+#define CLK_TOP_LVDS_PXL		140
+#define CLK_TOP_LVDS_CTS		141
+#define CLK_TOP_NR_CLK			142
+
+/* APMIXED_SYS */
+
+#define CLK_APMIXED_ARMCA15PLL		1
+#define CLK_APMIXED_ARMCA7PLL		2
+#define CLK_APMIXED_MAINPLL		3
+#define CLK_APMIXED_UNIVPLL		4
+#define CLK_APMIXED_MMPLL		5
+#define CLK_APMIXED_MSDCPLL		6
+#define CLK_APMIXED_VENCPLL		7
+#define CLK_APMIXED_TVDPLL		8
+#define CLK_APMIXED_MPLL		9
+#define CLK_APMIXED_VCODECPLL		10
+#define CLK_APMIXED_APLL1		11
+#define CLK_APMIXED_APLL2		12
+#define CLK_APMIXED_LVDSPLL		13
+#define CLK_APMIXED_MSDCPLL2		14
+#define CLK_APMIXED_REF2USB_TX		15
+#define CLK_APMIXED_HDMI_REF		16
+#define CLK_APMIXED_NR_CLK		17
+
+/* INFRA_SYS */
+
+#define CLK_INFRA_DBGCLK		1
+#define CLK_INFRA_SMI			2
+#define CLK_INFRA_AUDIO			3
+#define CLK_INFRA_GCE			4
+#define CLK_INFRA_L2C_SRAM		5
+#define CLK_INFRA_M4U			6
+#define CLK_INFRA_CPUM			7
+#define CLK_INFRA_KP			8
+#define CLK_INFRA_CEC			9
+#define CLK_INFRA_PMICSPI		10
+#define CLK_INFRA_PMICWRAP		11
+#define CLK_INFRA_CLK_13M		12
+#define CLK_INFRA_CA53SEL               13
+#define CLK_INFRA_CA57SEL               14
+#define CLK_INFRA_NR_CLK                15
+
+/* PERI_SYS */
+
+#define CLK_PERI_NFI			1
+#define CLK_PERI_THERM			2
+#define CLK_PERI_PWM1			3
+#define CLK_PERI_PWM2			4
+#define CLK_PERI_PWM3			5
+#define CLK_PERI_PWM4			6
+#define CLK_PERI_PWM5			7
+#define CLK_PERI_PWM6			8
+#define CLK_PERI_PWM7			9
+#define CLK_PERI_PWM			10
+#define CLK_PERI_USB0			11
+#define CLK_PERI_USB1			12
+#define CLK_PERI_AP_DMA			13
+#define CLK_PERI_MSDC30_0		14
+#define CLK_PERI_MSDC30_1		15
+#define CLK_PERI_MSDC30_2		16
+#define CLK_PERI_MSDC30_3		17
+#define CLK_PERI_NLI_ARB		18
+#define CLK_PERI_IRDA			19
+#define CLK_PERI_UART0			20
+#define CLK_PERI_UART1			21
+#define CLK_PERI_UART2			22
+#define CLK_PERI_UART3			23
+#define CLK_PERI_I2C0			24
+#define CLK_PERI_I2C1			25
+#define CLK_PERI_I2C2			26
+#define CLK_PERI_I2C3			27
+#define CLK_PERI_I2C4			28
+#define CLK_PERI_AUXADC			29
+#define CLK_PERI_SPI0			30
+#define CLK_PERI_I2C5			31
+#define CLK_PERI_NFIECC			32
+#define CLK_PERI_SPI			33
+#define CLK_PERI_IRRX			34
+#define CLK_PERI_I2C6			35
+#define CLK_PERI_UART0_SEL		36
+#define CLK_PERI_UART1_SEL		37
+#define CLK_PERI_UART2_SEL		38
+#define CLK_PERI_UART3_SEL		39
+#define CLK_PERI_NR_CLK			40
+
+/* IMG_SYS */
+
+#define CLK_IMG_LARB2_SMI		1
+#define CLK_IMG_CAM_SMI			2
+#define CLK_IMG_CAM_CAM			3
+#define CLK_IMG_SEN_TG			4
+#define CLK_IMG_SEN_CAM			5
+#define CLK_IMG_CAM_SV			6
+#define CLK_IMG_FD			7
+#define CLK_IMG_NR_CLK			8
+
+/* MM_SYS */
+
+#define CLK_MM_SMI_COMMON		1
+#define CLK_MM_SMI_LARB0		2
+#define CLK_MM_CAM_MDP			3
+#define CLK_MM_MDP_RDMA0		4
+#define CLK_MM_MDP_RDMA1		5
+#define CLK_MM_MDP_RSZ0			6
+#define CLK_MM_MDP_RSZ1			7
+#define CLK_MM_MDP_RSZ2			8
+#define CLK_MM_MDP_TDSHP0		9
+#define CLK_MM_MDP_TDSHP1		10
+#define CLK_MM_MDP_WDMA			11
+#define CLK_MM_MDP_WROT0		12
+#define CLK_MM_MDP_WROT1		13
+#define CLK_MM_FAKE_ENG			14
+#define CLK_MM_MUTEX_32K		15
+#define CLK_MM_DISP_OVL0		16
+#define CLK_MM_DISP_OVL1		17
+#define CLK_MM_DISP_RDMA0		18
+#define CLK_MM_DISP_RDMA1		19
+#define CLK_MM_DISP_RDMA2		20
+#define CLK_MM_DISP_WDMA0		21
+#define CLK_MM_DISP_WDMA1		22
+#define CLK_MM_DISP_COLOR0		23
+#define CLK_MM_DISP_COLOR1		24
+#define CLK_MM_DISP_AAL			25
+#define CLK_MM_DISP_GAMMA		26
+#define CLK_MM_DISP_UFOE		27
+#define CLK_MM_DISP_SPLIT0		28
+#define CLK_MM_DISP_SPLIT1		29
+#define CLK_MM_DISP_MERGE		30
+#define CLK_MM_DISP_OD			31
+#define CLK_MM_DISP_PWM0MM		32
+#define CLK_MM_DISP_PWM026M		33
+#define CLK_MM_DISP_PWM1MM		34
+#define CLK_MM_DISP_PWM126M		35
+#define CLK_MM_DSI0_ENGINE		36
+#define CLK_MM_DSI0_DIGITAL		37
+#define CLK_MM_DSI1_ENGINE		38
+#define CLK_MM_DSI1_DIGITAL		39
+#define CLK_MM_DPI_PIXEL		40
+#define CLK_MM_DPI_ENGINE		41
+#define CLK_MM_DPI1_PIXEL		42
+#define CLK_MM_DPI1_ENGINE		43
+#define CLK_MM_HDMI_PIXEL		44
+#define CLK_MM_HDMI_PLLCK		45
+#define CLK_MM_HDMI_AUDIO		46
+#define CLK_MM_HDMI_SPDIF		47
+#define CLK_MM_LVDS_PIXEL		48
+#define CLK_MM_LVDS_CTS			49
+#define CLK_MM_SMI_LARB4		50
+#define CLK_MM_HDMI_HDCP		51
+#define CLK_MM_HDMI_HDCP24M		52
+#define CLK_MM_NR_CLK			53
+
+/* VDEC_SYS */
+
+#define CLK_VDEC_CKEN			1
+#define CLK_VDEC_LARB_CKEN		2
+#define CLK_VDEC_NR_CLK			3
+
+/* VENC_SYS */
+
+#define CLK_VENC_CKE0			1
+#define CLK_VENC_CKE1			2
+#define CLK_VENC_CKE2			3
+#define CLK_VENC_CKE3			4
+#define CLK_VENC_NR_CLK			5
+
+/* VENCLT_SYS */
+
+#define CLK_VENCLT_CKE0			1
+#define CLK_VENCLT_CKE1			2
+#define CLK_VENCLT_NR_CLK		3
+
+#endif /* _DT_BINDINGS_CLK_MT8173_H */

include/dt-bindings/clock/nuvoton,npcm7xx-clock.h

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC  7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI  9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX  17
+#define NPCM7XX_CLK_SU   18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+
+#define NPCM7XX_NUM_CLOCKS	 (NPCM7XX_CLK_MCBYPCK+1)
+
+#endif