352 lines
12 KiB
Plaintext
352 lines
12 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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&clkitg {
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status = "okay";
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bring-up {
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compatible = "mediatek,clk-bring-up";
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clocks =
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<&clk26m>,
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<&apmixed APMIXED_MAINPLL>,
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<&apmixed APMIXED_UNIV2PLL>,
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<&apmixed APMIXED_MFGPLL>,
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<&apmixed APMIXED_MSDCPLL>,
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<&apmixed APMIXED_ADSPPLL>,
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<&apmixed APMIXED_MMPLL>,
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<&apmixed APMIXED_APLL1>,
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<&apmixed APMIXED_APLL2>,
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<&topckgen TOP_MUX_AXI>,
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<&topckgen TOP_MUX_SCP>,
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<&topckgen TOP_MUX_MFG>,
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<&topckgen TOP_MUX_CAMTG>,
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<&topckgen TOP_MUX_CAMTG1>,
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<&topckgen TOP_MUX_CAMTG2>,
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<&topckgen TOP_MUX_CAMTG3>,
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<&topckgen TOP_MUX_CAMTG4>,
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<&topckgen TOP_MUX_CAMTG5>,
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<&topckgen TOP_MUX_CAMTG6>,
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<&topckgen TOP_MUX_UART>,
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<&topckgen TOP_MUX_SPI>,
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<&topckgen TOP_MUX_MSDC50_0_HCLK>,
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<&topckgen TOP_MUX_MSDC50_0>,
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<&topckgen TOP_MUX_MSDC30_1>,
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<&topckgen TOP_MUX_AUDIO>,
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<&topckgen TOP_MUX_AUD_INTBUS>,
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<&topckgen TOP_MUX_AUD_1>,
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<&topckgen TOP_MUX_AUD_2>,
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<&topckgen TOP_MUX_AUD_ENG1>,
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<&topckgen TOP_MUX_AUD_ENG2>,
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<&topckgen TOP_MUX_DISP_PWM>,
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<&topckgen TOP_MUX_SSPM>,
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<&topckgen TOP_MUX_DXCC>,
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<&topckgen TOP_MUX_USB_TOP>,
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<&topckgen TOP_MUX_SRCK>,
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<&topckgen TOP_MUX_SPM>,
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<&topckgen TOP_MUX_I2C>,
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<&topckgen TOP_MUX_PWM>,
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<&topckgen TOP_MUX_SENINF>,
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<&topckgen TOP_MUX_SENINF1>,
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<&topckgen TOP_MUX_SENINF2>,
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<&topckgen TOP_MUX_SENINF3>,
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<&topckgen TOP_MUX_AES_MSDCFDE>,
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<&topckgen TOP_MUX_FPWRAP_ULPOSC>,
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<&topckgen TOP_MUX_CAMTM>,
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<&topckgen TOP_MUX_VENC>,
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<&topckgen TOP_MUX_CAM>,
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<&topckgen TOP_MUX_IMG1>,
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<&topckgen TOP_MUX_IPE>,
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<&topckgen TOP_MUX_DPMAIF>,
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<&topckgen TOP_MUX_VDEC>,
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<&topckgen TOP_MUX_DISP>,
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<&topckgen TOP_MUX_MDP>,
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<&topckgen TOP_MUX_AUDIO_H>,
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<&topckgen TOP_MUX_UFS>,
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<&topckgen TOP_MUX_AES_FDE>,
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<&topckgen TOP_MUX_ADSP>,
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<&topckgen TOP_MUX_DVFSRC>,
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<&topckgen TOP_MUX_DSI_OCC>,
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<&topckgen TOP_MUX_SPMI_MST>,
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<&topckgen TOP_APLL12_DIV0>,
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<&topckgen TOP_APLL12_DIV1>,
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<&topckgen TOP_APLL12_DIV2>,
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<&topckgen TOP_APLL12_DIV3>,
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<&topckgen TOP_APLL12_DIV4>,
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<&topckgen TOP_APLL12_DIVB>,
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<&topckgen TOP_APLL12_DIV5>,
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<&scpsys SCP_SYS_DIS>,
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<&scpsys SCP_SYS_CAM>,
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<&scpsys SCP_SYS_ISP>,
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<&scpsys SCP_SYS_VEN>,
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<&scpsys SCP_SYS_VDE>,
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<&scpsys SCP_SYS_MFG0>,
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<&scpsys SCP_SYS_MFG1>,
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<&scpsys SCP_SYS_MFG2>,
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<&scpsys SCP_SYS_MFG3>,
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<&scpsys SCP_SYS_ISP2>,
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<&scpsys SCP_SYS_CAM_RAWA>,
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<&scpsys SCP_SYS_CAM_RAWB>,
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<&scpsys SCP_SYS_IPE>,
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<&infracfg_ao INFRACFG_AO_PMIC_CG_TMR>,
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<&infracfg_ao INFRACFG_AO_PMIC_CG_AP>,
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<&infracfg_ao INFRACFG_AO_PMIC_CG_MD>,
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<&infracfg_ao INFRACFG_AO_PMIC_CG_CONN>,
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<&infracfg_ao INFRACFG_AO_SCPSYS_CG>,
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<&infracfg_ao INFRACFG_AO_SEJ_CG>,
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<&infracfg_ao INFRACFG_AO_APXGPT_CG>,
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<&infracfg_ao INFRACFG_AO_ICUSB_CG>,
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<&infracfg_ao INFRACFG_AO_THERM_CG>,
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<&infracfg_ao INFRACFG_AO_I2C_AP_CG>,
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<&infracfg_ao INFRACFG_AO_I2C_CCU_CG>,
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<&infracfg_ao INFRACFG_AO_I2C_SSPM_CG>,
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<&infracfg_ao INFRACFG_AO_I2C_RSV_CG>,
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<&infracfg_ao INFRACFG_AO_PWM_HCLK_CG>,
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<&infracfg_ao INFRACFG_AO_PWM1_CG>,
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<&infracfg_ao INFRACFG_AO_PWM2_CG>,
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<&infracfg_ao INFRACFG_AO_PWM3_CG>,
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<&infracfg_ao INFRACFG_AO_PWM4_CG>,
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<&infracfg_ao INFRACFG_AO_PWM5_CG>,
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<&infracfg_ao INFRACFG_AO_PWM_CG>,
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<&infracfg_ao INFRACFG_AO_UART0_CG>,
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<&infracfg_ao INFRACFG_AO_UART1_CG>,
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<&infracfg_ao INFRACFG_AO_UART2_CG>,
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<&infracfg_ao INFRACFG_AO_UART3_CG>,
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<&infracfg_ao INFRACFG_AO_CQ_DMA_FPC_CG>,
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<&infracfg_ao INFRACFG_AO_BTIF_CG>,
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<&infracfg_ao INFRACFG_AO_SPI0_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC0_CG>,
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<&infracfg_ao INFRACFG_AO_MSDCFDE_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC1_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC2_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC0_SCK_CG>,
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<&infracfg_ao INFRACFG_AO_DVFSRC_CG>,
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<&infracfg_ao INFRACFG_AO_GCPU_CG>,
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<&infracfg_ao INFRACFG_AO_TRNG_CG>,
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<&infracfg_ao INFRACFG_AO_AUXADC_CG>,
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<&infracfg_ao INFRACFG_AO_CPUM_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF1_AP_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF1_MD_CG>,
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<&infracfg_ao INFRACFG_AO_AUXADC_MD_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC1_SCK_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC2_SCK_CG>,
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<&infracfg_ao INFRACFG_AO_AP_DMA_CG>,
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<&infracfg_ao INFRACFG_AO_XIU_CG>,
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<&infracfg_ao INFRACFG_AO_DEVICE_APC_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF_AP_CG>,
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<&infracfg_ao INFRACFG_AO_DEBUGSYS_CG>,
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<&infracfg_ao INFRACFG_AO_AUDIO_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF_MD_CG>,
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<&infracfg_ao INFRACFG_AO_DXCC_SEC_CORE_CG>,
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<&infracfg_ao INFRACFG_AO_DXCC_AO_CG>,
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<&infracfg_ao INFRACFG_AO_IMP_IIC_CG>,
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<&infracfg_ao INFRACFG_AO_DEVMPU_BCLK_CG>,
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<&infracfg_ao INFRACFG_AO_DRAMC_F26M_CG>,
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<&infracfg_ao INFRACFG_AO_PWM_BCLK6_CG>,
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<&infracfg_ao INFRACFG_AO_USB_CG>,
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<&infracfg_ao INFRACFG_AO_DISP_PWM_CG>,
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<&infracfg_ao INFRACFG_AO_CLDMA_BCLK_CG>,
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<&infracfg_ao INFRACFG_AO_AUDIO_26M_BCLK_CK>,
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<&infracfg_ao INFRACFG_AO_SPI1_CG>,
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<&infracfg_ao INFRACFG_AO_I2C4_CG>,
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<&infracfg_ao INFRACFG_AO_MODEM_TEMP_SHARE_CG>,
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<&infracfg_ao INFRACFG_AO_SPI2_CG>,
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<&infracfg_ao INFRACFG_AO_SPI3_CG>,
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<&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
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<&infracfg_ao INFRACFG_AO_UNIPRO_TICK_CG>,
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<&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>,
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<&infracfg_ao INFRACFG_AO_MD32_BCLK_CG>,
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<&infracfg_ao INFRACFG_AO_SSPM_CG>,
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<&infracfg_ao INFRACFG_AO_UNIPRO_MBIST_CG>,
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<&infracfg_ao INFRACFG_AO_SSPM_BUS_HCLK_CG>,
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<&infracfg_ao INFRACFG_AO_I2C5_CG>,
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<&infracfg_ao INFRACFG_AO_I2C5_ARBITER_CG>,
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<&infracfg_ao INFRACFG_AO_I2C5_IMM_CG>,
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<&infracfg_ao INFRACFG_AO_I2C1_ARBITER_CG>,
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<&infracfg_ao INFRACFG_AO_I2C1_IMM_CG>,
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<&infracfg_ao INFRACFG_AO_I2C2_ARBITER_CG>,
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<&infracfg_ao INFRACFG_AO_I2C2_IMM_CG>,
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<&infracfg_ao INFRACFG_AO_SPI4_CG>,
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<&infracfg_ao INFRACFG_AO_SPI5_CG>,
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<&infracfg_ao INFRACFG_AO_CQ_DMA_CG>,
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<&infracfg_ao INFRACFG_AO_BIST2FPC_CG>,
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<&infracfg_ao INFRACFG_AO_AES_UFS_CG>,
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<&infracfg_ao INFRACFG_AO_UFS_CG>,
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<&infracfg_ao INFRACFG_AO_UFS_TICK_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC0_SELF_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC1_SELF_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC2_SELF_CG>,
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<&infracfg_ao INFRACFG_AO_SSPM_26M_SELF_CG>,
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<&infracfg_ao INFRACFG_AO_SSPM_32K_SELF_CG>,
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<&infracfg_ao INFRACFG_AO_UFS_AXI_CG>,
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<&infracfg_ao INFRACFG_AO_I2C6_CG>,
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<&infracfg_ao INFRACFG_AO_AP_MSDC0_CG>,
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<&infracfg_ao INFRACFG_AO_MD_MSDC0_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC0_SRCLK_CG>,
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<&infracfg_ao INFRACFG_AO_MSDC1_SRCLK_CG>,
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<&infracfg_ao INFRACFG_AO_PWRAP_TMR_FO_CG>,
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<&infracfg_ao INFRACFG_AO_PWRAP_SPI_FO_CG>,
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<&infracfg_ao INFRACFG_AO_PWRAP_SYS_FO_CG>,
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<&infracfg_ao INFRACFG_AO_SEJ_F13M_CG>,
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<&infracfg_ao INFRACFG_AO_AES_TOP0_BCLK_CG>,
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<&infracfg_ao INFRACFG_AO_MCUPM_BCLK_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF2_AP_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF2_MD_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF3_AP_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF3_MD_CG>,
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<&infracfg_ao INFRACFG_AO_FADSP_26M_CG>,
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<&infracfg_ao INFRACFG_AO_FADSP_32K_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF4_AP_CG>,
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<&infracfg_ao INFRACFG_AO_CCIF4_MD_CG>,
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<&infracfg_ao INFRACFG_AO_DPMAIF_CK>,
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<&infracfg_ao INFRACFG_AO_FADSP_CG>,
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<&apmixed APMIXED_SSUSB26M>,
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<&apmixed APMIXED_APPLL26M>,
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<&apmixed APMIXED_MIPIC0_26M>,
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<&apmixed APMIXED_MDPLLGP26M>,
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<&apmixed APMIXED_MMSYS_F26M>,
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<&apmixed APMIXED_UFS26M>,
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<&apmixed APMIXED_MIPIC1_26M>,
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<&apmixed APMIXED_MEMPLL26M>,
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<&apmixed APMIXED_CLKSQ_LVPLL_26M>,
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<&apmixed APMIXED_MIPID0_26M>,
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<&apmixed APMIXED_MIPID1_26M>,
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<&mfgcfg MFGCFG_BG3D>,
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<&audio AUDIO_AFE>,
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<&audio AUDIO_22M>,
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<&audio AUDIO_24M>,
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<&audio AUDIO_APLL2_TUNER>,
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<&audio AUDIO_APLL_TUNER>,
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<&audio AUDIO_TDM>,
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<&audio AUDIO_ADC>,
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<&audio AUDIO_DAC>,
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<&audio AUDIO_DAC_PREDIS>,
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<&audio AUDIO_TML>,
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<&audio AUDIO_NLE>,
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<&audio AUDIO_I2S1_BCLK_SW>,
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<&audio AUDIO_I2S2_BCLK_SW>,
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<&audio AUDIO_I2S3_BCLK_SW>,
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<&audio AUDIO_I2S4_BCLK_SW>,
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<&audio AUDIO_I2S5_BCLK_SW>,
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<&audio AUDIO_CONN_I2S_ASRC>,
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<&audio AUDIO_GENERAL1_ASRC>,
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<&audio AUDIO_GENERAL2_ASRC>,
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<&audio AUDIO_DAC_HIRES>,
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<&audio AUDIO_ADC_HIRES>,
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<&audio AUDIO_ADC_HIRES_TML>,
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<&audio AUDIO_PDN_ADDA6_ADC>,
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<&audio AUDIO_ADDA6_ADC_HIRES>,
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<&audio AUDIO_3RD_DAC>,
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<&audio AUDIO_3RD_DAC_PREDIS>,
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<&audio AUDIO_3RD_DAC_TML>,
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<&audio AUDIO_3RD_DAC_HIRES>,
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<&audio AUDIO_ETDM_IN1_BCLK_SW>,
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<&audio AUDIO_ETDM_OUT1_BCLK_SW>,
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<&camsys CLK_CAM_M_LARB13>,
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<&camsys CLK_CAM_M_DFP_VAD>,
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<&camsys CLK_CAM_M_LARB14>,
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<&camsys CLK_CAM_M_RESERVED0>,
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<&camsys CLK_CAM_M_CAM>,
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<&camsys CLK_CAM_M_CAMTG>,
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<&camsys CLK_CAM_M_SENINF>,
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<&camsys CLK_CAM_M_CAMSV1>,
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<&camsys CLK_CAM_M_CAMSV2>,
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<&camsys CLK_CAM_M_CAMSV3>,
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<&camsys CLK_CAM_M_CCU0>,
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<&camsys CLK_CAM_M_CCU1>,
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<&camsys CLK_CAM_M_MRAW0>,
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<&camsys CLK_CAM_M_RESERVED2>,
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<&camsys CLK_CAM_M_FAKE_ENG>,
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<&camsys CLK_CAM_M_CCU_GALS>,
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<&camsys CLK_CAM_M_CAM2MM_GALS>,
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<&camsys_rawa CLK_CAM_RA_LARBX>,
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<&camsys_rawa CLK_CAM_RA_CAM>,
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<&camsys_rawa CLK_CAM_RA_CAMTG>,
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<&camsys_rawb CLK_CAM_RB_LARBX>,
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<&camsys_rawb CLK_CAM_RB_CAM>,
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<&camsys_rawb CLK_CAM_RB_CAMTG>,
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<&imgsys1 CLK_IMGSYS1_LARB9>,
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<&imgsys1 CLK_IMGSYS1_LARB10>,
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<&imgsys1 CLK_IMGSYS1_DIP>,
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<&imgsys1 CLK_IMGSYS1_GALS>,
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<&imgsys2 CLK_IMGSYS2_LARB9>,
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<&imgsys2 CLK_IMGSYS2_LARB10>,
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<&imgsys2 CLK_IMGSYS2_MFB>,
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<&imgsys2 CLK_IMGSYS2_WPE>,
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<&imgsys2 CLK_IMGSYS2_MSS>,
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<&imgsys2 CLK_IMGSYS2_GALS>,
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<&ipesys CLK_IPE_LARB19>,
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<&ipesys CLK_IPE_LARB20>,
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<&ipesys CLK_IPE_SMI_SUBCOM>,
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<&ipesys CLK_IPE_FD>,
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<&ipesys CLK_IPE_FE>,
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<&ipesys CLK_IPE_RSC>,
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<&ipesys CLK_IPE_DPE>,
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<&ipesys CLK_IPE_GALS>,
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<&mmsys_config CLK_MM_DISP_MUTEX0>,
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<&mmsys_config CLK_MM_APB_BUS>,
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<&mmsys_config CLK_MM_DISP_OVL0>,
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<&mmsys_config CLK_MM_DISP_RDMA0>,
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<&mmsys_config CLK_MM_DISP_OVL0_2L>,
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<&mmsys_config CLK_MM_DISP_WDMA0>,
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<&mmsys_config CLK_MM_DISP_CCORR1>,
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<&mmsys_config CLK_MM_DISP_RSZ0>,
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<&mmsys_config CLK_MM_DISP_AAL0>,
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<&mmsys_config CLK_MM_DISP_CCORR0>,
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<&mmsys_config CLK_MM_DISP_COLOR0>,
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<&mmsys_config CLK_MM_SMI_INFRA>,
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<&mmsys_config CLK_MM_DISP_DSC_WRAP>,
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<&mmsys_config CLK_MM_DISP_GAMMA0>,
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<&mmsys_config CLK_MM_DISP_POSTMASK0>,
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<&mmsys_config CLK_MM_DISP_SPR0>,
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<&mmsys_config CLK_MM_DISP_DITHER0>,
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<&mmsys_config CLK_MM_SMI_COMMON>,
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<&mmsys_config CLK_MM_DISP_CM0>,
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<&mmsys_config CLK_MM_DSI0>,
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<&mmsys_config CLK_MM_DISP_FAKE_ENG0>,
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<&mmsys_config CLK_MM_DISP_FAKE_ENG1>,
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<&mmsys_config CLK_MM_SMI_GALS>,
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<&mmsys_config CLK_MM_SMI_IOMMU>,
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<&mmsys_config CLK_MM_DSI0_DSI_CK_DOMAIN>,
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<&mmsys_config CLK_MM_DISP_26M>,
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<&mdpsys_config CLK_MDP_RDMA0>,
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<&mdpsys_config CLK_MDP_TDSHP0>,
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<&mdpsys_config CLK_MDP_IMG_DL_ASYNC0>,
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<&mdpsys_config CLK_MDP_IMG_DL_ASYNC1>,
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<&mdpsys_config CLK_MDP_RDMA1>,
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<&mdpsys_config CLK_MDP_TDSHP1>,
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<&mdpsys_config CLK_MDP_SMI0>,
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<&mdpsys_config CLK_MDP_APB_BUS>,
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<&mdpsys_config CLK_MDP_WROT0>,
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<&mdpsys_config CLK_MDP_RSZ0>,
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<&mdpsys_config CLK_MDP_HDR0>,
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<&mdpsys_config CLK_MDP_MUTEX0>,
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<&mdpsys_config CLK_MDP_WROT1>,
|
|
<&mdpsys_config CLK_MDP_RSZ1>,
|
|
<&mdpsys_config CLK_MDP_FAKE_ENG0>,
|
|
<&mdpsys_config CLK_MDP_AAL0>,
|
|
<&mdpsys_config CLK_MDP_AAL1>,
|
|
<&mdpsys_config CLK_MDP_COLOR0>,
|
|
<&mdpsys_config CLK_MDP_IMG_DL_RELAY0_ASYNC0>,
|
|
<&mdpsys_config CLK_MDP_IMG_DL_RELAY1_ASYNC1>,
|
|
<&vdec_gcon VDEC_VDEC>,
|
|
<&vdec_gcon VDEC_LARB1>,
|
|
<&vdec_gcon VDEC_LAT>,
|
|
<&venc_gcon VENC_GCON_LARB>,
|
|
<&venc_gcon VENC_GCON_VENC>,
|
|
<&venc_gcon VENC_GCON_JPGENC>,
|
|
<&venc_gcon VENC_GCON_GALS>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C0>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C1>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C2>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C3>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C4>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C5>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C6>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C7>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C8>,
|
|
<&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C9>;
|
|
};
|
|
};
|