592 lines
19 KiB
C
592 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MPU_PLATFORM_H__
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#define __MPU_PLATFORM_H__
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enum {
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MT6785_M4_AXI_MST_QP_DLCH,
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MT6785_M4_AXI_MST_BR_DMA,
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MT6785_M2_AXI_MST_CCU,
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MT6785_M2_AXI_MST_SMI_LARB0,
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MT6785_M4_AXI_MST_DCXO,
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MT6785_M4_AXI_MST_MRSG0,
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MT6785_M7_AXI_MST_IPU,
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MT6785_M7_AXI_MST_CCU,
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MT6785_M4_AXI_MST_IRDMA,
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MT6785_M7_AXI_MST_MSDC0,
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MT6785_M2_AXI_MST_SMI_LARB2,
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MT6785_M4_AXI_MST_TRACE_TOP,
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MT6785_M4_AXI_MST_CSH0,
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MT6785_M4_AXI_MST_DMA_WR,
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MT6785_M7_AXI_MST_APU,
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MT6785_M7_AXI_MST_SPI1,
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MT6785_M4_AXI_MST_SSPM,
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MT6785_M2_AXI_MST_SMI_LARB6,
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MT6785_M7_AXI_MST_SPI3,
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MT6785_M3_AXI_MST_MMU,
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MT6785_M7_AXI_MST_SPI5,
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MT6785_M4_AXI_MST_IPSEC,
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MT6785_M4_AXI_MST_CNWDMA,
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MT6785_M7_AXI_MST_SPI7,
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MT6785_M5_AXI_MST_SMI_LARB1,
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MT6785_M7_AXI_MST_UFS,
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MT6785_M7_AXI_MST_DX_CC,
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MT6785_M4_AXI_MST_MMU,
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MT6785_M7_AXI_MST_APU_IOMMU_P1,
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MT6785_M1_AXI_MST_MP1,
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MT6785_M3_AXI_MST_USIP_0_DPERI,
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MT6785_M5_AXI_MST_SMI_LARB3,
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MT6785_M4_AXI_MST_HRQ_RD,
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MT6785_M4_AXI_MST_LOG_TOP_MCU,
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MT6785_M3_AXI_MST_USIP_1_I,
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MT6785_M5_AXI_MST_SMI_LARB5,
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MT6785_M5_AXI_MST_MM_IOMMU,
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MT6785_M4_AXI_MST_DBGSYS_DSP,
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MT6785_M3_AXI_MST_USIP_1_DPERI,
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MT6785_M4_AXI_MST_GDMA,
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MT6785_M4_AXI_MST_LOG_TOP_DSP,
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MT6785_M7_AXI_MST_DEVICE_MPU,
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MT6785_M7_AXI_MST_DMA_EXT,
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MT6785_M4_AXI_MST_HRQ_RD1,
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MT6785_M3_AXI_MST_USIP_0_I,
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MT6785_M4_AXI_MST_DMA_RD_DLCH,
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MT6785_M4_AXI_MST_TXBSRP,
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MT6785_M6_AXI_MST_APU_IOMMU,
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MT6785_M7_AXI_MST_CQ_DMA,
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MT6785_M2_AXI_MST_SMI_LARB1,
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MT6785_M7_AXI_MST_PWM,
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MT6785_M4_AXI_MST_,
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MT6785_M4_AXI_MST_MRSG1,
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MT6785_M2_AXI_MST_SMI_LARB3,
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MT6785_M7_AXI_MST_MSDC1,
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MT6785_M7_AXI_MST_SPI0,
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MT6785_M7_AXI_MST_NA,
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MT6785_M4_AXI_MST_IPF,
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MT6785_M4_AXI_MST_DMA_RD,
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MT6785_M4_AXI_MST_XDMA,
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MT6785_M7_AXI_MST_AUDIO,
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MT6785_M2_AXI_MST_SMI_LARB5,
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MT6785_M4_AXI_MST_TPC,
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MT6785_M7_AXI_MST_THERM,
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MT6785_M7_AXI_MST_SPI2,
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MT6785_M5_AXI_MST_CCU,
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MT6785_M4_AXI_MST_VTB,
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MT6785_M7_AXI_MST_SPM,
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MT6785_M0_AXI_MST_MP0,
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MT6785_M3_AXI_MST_MM,
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MT6785_M7_AXI_MST_MFG_M1,
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MT6785_M7_AXI_MST_SPI4,
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MT6785_M4_AXI_MST_CLDMA,
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MT6785_M4_AXI_MST_PPPHA,
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MT6785_M3_AXI_MST_USIP_1_DLONG,
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MT6785_M7_AXI_MST_SSUSB,
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MT6785_M4_AXI_MST_SCP,
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MT6785_M4_AXI_MST_HIFI3,
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MT6785_M4_AXI_MST_QP,
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MT6785_M3_AXI_MST_USIP_0_DLONG,
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MT6785_M7_AXI_MST_GCE_M,
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MT6785_M7_AXI_MST_SPI6,
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MT6785_M5_AXI_MST_SMI_LARB0,
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MT6785_M6_AXI_MST_MFG,
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MT6785_M7_AXI_MST_DEBUGTOP,
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MT6785_M5_AXI_MST_SMI_LARB2,
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MT6785_M4_AXI_MST_MCUSYS_DFD,
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MT6785_M4_AXI_MST_HRQ_WR,
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MT6785_M6_AXI_MST_APU,
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MT6785_M4_AXI_MST_TBO,
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MT6785_M2_AXI_MST_MM_IOMMU,
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MT6785_M5_AXI_MST_SMI_LARB6,
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MT6785_M4_AXI_MST_HRQ_WR1,
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MT6785_M4_AXI_MST_CONNSYS,
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MST_INVALID,
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NR_MST
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};
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static const struct mst_tbl_entry mst_tbl[] = {
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1EF8,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1EF8,
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.id_val = 0x20,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1E80,
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.id_val = 0x80,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DF8,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DF8,
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.id_val = 0x20,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DFF,
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.id_val = 0x40,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DFF,
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.id_val = 0x41,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1D80,
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.id_val = 0x80,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1D00,
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.id_val = 0x100,
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.note = "",
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.name = "MT6785_M0_AXI_MST_MP0"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1EF8,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1EF8,
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.id_val = 0x20,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1E80,
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.id_val = 0x80,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DF8,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DF8,
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.id_val = 0x20,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DFF,
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.id_val = 0x40,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DFF,
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.id_val = 0x41,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1D80,
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.id_val = 0x80,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1D00,
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.id_val = 0x100,
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.note = "",
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.name = "MT6785_M1_AXI_MST_MP1"},
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{.master = MT6785_M2_AXI_MST_MM_IOMMU, .port = 2, .id_mask = 0x1FFF,
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.id_val = 0xFFC,
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.note = "",
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.name = "MT6785_M2_AXI_MST_MM_IOMMU"},
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{.master = MT6785_M2_AXI_MST_MM_IOMMU, .port = 2, .id_mask = 0x1FFF,
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.id_val = 0xFFD,
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.note = "",
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.name = "MT6785_M2_AXI_MST_MM_IOMMU"},
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{.master = MT6785_M2_AXI_MST_SMI_LARB0, .port = 2, .id_mask = 0x1F80,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M2_AXI_MST_SMI_LARB0"},
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{.master = MT6785_M2_AXI_MST_SMI_LARB1, .port = 2, .id_mask = 0x1F80,
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.id_val = 0x200,
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.note = "",
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.name = "MT6785_M2_AXI_MST_SMI_LARB1"},
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{.master = MT6785_M2_AXI_MST_SMI_LARB2, .port = 2, .id_mask = 0x1F80,
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.id_val = 0x400,
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.note = "",
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.name = "MT6785_M2_AXI_MST_SMI_LARB2"},
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{.master = MT6785_M2_AXI_MST_SMI_LARB3, .port = 2, .id_mask = 0x1F80,
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.id_val = 0x600,
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.note = "",
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.name = "MT6785_M2_AXI_MST_SMI_LARB3"},
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{.master = MT6785_M2_AXI_MST_SMI_LARB5, .port = 2, .id_mask = 0x1F80,
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.id_val = 0x800,
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.note = "",
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.name = "MT6785_M2_AXI_MST_SMI_LARB5"},
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{.master = MT6785_M2_AXI_MST_SMI_LARB6, .port = 2, .id_mask = 0x1F80,
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.id_val = 0xE00,
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.note = "",
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.name = "MT6785_M2_AXI_MST_SMI_LARB6"},
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{.master = MT6785_M2_AXI_MST_CCU, .port = 2, .id_mask = 0x1F80,
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.id_val = 0xC00,
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.note = "",
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.name = "MT6785_M2_AXI_MST_CCU"},
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{.master = MT6785_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
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.id_val = 0xFFC,
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.note = "",
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.name = "MT6785_M5_AXI_MST_MM_IOMMU"},
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{.master = MT6785_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
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.id_val = 0xFFD,
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.note = "",
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.name = "MT6785_M5_AXI_MST_MM_IOMMU"},
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{.master = MT6785_M5_AXI_MST_SMI_LARB0, .port = 5, .id_mask = 0x1F80,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M5_AXI_MST_SMI_LARB0"},
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{.master = MT6785_M5_AXI_MST_SMI_LARB1, .port = 5, .id_mask = 0x1F80,
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.id_val = 0x200,
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.note = "",
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.name = "MT6785_M5_AXI_MST_SMI_LARB1"},
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{.master = MT6785_M5_AXI_MST_SMI_LARB2, .port = 5, .id_mask = 0x1F80,
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.id_val = 0x400,
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.note = "",
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.name = "MT6785_M5_AXI_MST_SMI_LARB2"},
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{.master = MT6785_M5_AXI_MST_SMI_LARB3, .port = 5, .id_mask = 0x1F80,
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.id_val = 0x600,
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.note = "",
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.name = "MT6785_M5_AXI_MST_SMI_LARB3"},
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{.master = MT6785_M5_AXI_MST_SMI_LARB5, .port = 5, .id_mask = 0x1F80,
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.id_val = 0x800,
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.note = "",
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.name = "MT6785_M5_AXI_MST_SMI_LARB5"},
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{.master = MT6785_M5_AXI_MST_SMI_LARB6, .port = 5, .id_mask = 0x1F80,
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.id_val = 0xE00,
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.note = "",
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.name = "MT6785_M5_AXI_MST_SMI_LARB6"},
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{.master = MT6785_M5_AXI_MST_CCU, .port = 5, .id_mask = 0x1F80,
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.id_val = 0xC00,
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.note = "",
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.name = "MT6785_M5_AXI_MST_CCU"},
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{.master = MT6785_M6_AXI_MST_APU_IOMMU, .port = 6, .id_mask = 0x1FFF,
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.id_val = 0x7FC,
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.note = "",
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.name = "MT6785_M6_AXI_MST_APU_IOMMU"},
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{.master = MT6785_M6_AXI_MST_APU_IOMMU, .port = 6, .id_mask = 0x1FFF,
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.id_val = 0x7FD,
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.note = "",
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.name = "MT6785_M6_AXI_MST_APU_IOMMU"},
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{.master = MT6785_M6_AXI_MST_APU, .port = 6, .id_mask = 0x1C00,
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.id_val = 0x400,
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.note = "",
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.name = "MT6785_M6_AXI_MST_APU"},
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{.master = MT6785_M6_AXI_MST_MFG, .port = 6, .id_mask = 0x1FC0,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M6_AXI_MST_MFG"},
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{.master = MT6785_M7_AXI_MST_SSUSB, .port = 7, .id_mask = 0x1FCF,
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.id_val = 0x0,
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.note = "",
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.name = "MT6785_M7_AXI_MST_SSUSB"},
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{.master = MT6785_M7_AXI_MST_PWM, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x8,
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.note = "",
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.name = "MT6785_M7_AXI_MST_PWM"},
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{.master = MT6785_M7_AXI_MST_MSDC1, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x18,
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.note = "",
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.name = "MT6785_M7_AXI_MST_MSDC1"},
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{.master = MT6785_M7_AXI_MST_SPI6, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x28,
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.note = "",
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.name = "MT6785_M7_AXI_MST_SPI6"},
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{.master = MT6785_M7_AXI_MST_SPI0, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x38,
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.note = "",
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.name = "MT6785_M7_AXI_MST_SPI0"},
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{.master = MT6785_M7_AXI_MST_DEBUGTOP, .port = 7, .id_mask = 0x1FBF,
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.id_val = 0x4,
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.note = "",
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.name = "MT6785_M7_AXI_MST_DEBUGTOP"},
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{.master = MT6785_M7_AXI_MST_AUDIO, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x20C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_AUDIO"},
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{.master = MT6785_M7_AXI_MST_IPU, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x40C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_IPU"},
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{.master = MT6785_M7_AXI_MST_SPI1, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x60C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_SPI1"},
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{.master = MT6785_M7_AXI_MST_SPI7, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0xC,
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.note = "",
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.name = "MT6785_M7_AXI_MST_SPI7"},
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{.master = MT6785_M7_AXI_MST_CCU, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x4C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_CCU"},
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{.master = MT6785_M7_AXI_MST_SPM, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x24C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_SPM"},
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{.master = MT6785_M7_AXI_MST_NA, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x44C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_NA"},
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{.master = MT6785_M7_AXI_MST_THERM, .port = 7, .id_mask = 0x1FFF,
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.id_val = 0x64C,
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.note = "",
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.name = "MT6785_M7_AXI_MST_THERM"},
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{.master = MT6785_M7_AXI_MST_UFS, .port = 7, .id_mask = 0x19FF,
|
|
.id_val = 0x8C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_UFS"},
|
|
{.master = MT6785_M7_AXI_MST_DMA_EXT, .port = 7, .id_mask = 0x1DFF,
|
|
.id_val = 0xCC,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_DMA_EXT"},
|
|
{.master = MT6785_M7_AXI_MST_SPI2, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x14C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_SPI2"},
|
|
{.master = MT6785_M7_AXI_MST_SPI3, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x34C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_SPI3"},
|
|
{.master = MT6785_M7_AXI_MST_SPI4, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x54C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_SPI4"},
|
|
{.master = MT6785_M7_AXI_MST_SPI5, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x74C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_SPI5"},
|
|
{.master = MT6785_M7_AXI_MST_MSDC0, .port = 7, .id_mask = 0x11FF,
|
|
.id_val = 0x18C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_MSDC0"},
|
|
{.master = MT6785_M7_AXI_MST_DX_CC, .port = 7, .id_mask = 0x1C3F,
|
|
.id_val = 0x14,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_DX_CC"},
|
|
{.master = MT6785_M7_AXI_MST_CQ_DMA, .port = 7, .id_mask = 0x1E3F,
|
|
.id_val = 0x1C,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_CQ_DMA"},
|
|
{.master = MT6785_M7_AXI_MST_GCE_M, .port = 7, .id_mask = 0x1F3F,
|
|
.id_val = 0x24,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_GCE_M"},
|
|
{.master = MT6785_M7_AXI_MST_APU_IOMMU_P1, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x1FF1,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_APU_IOMMU_P1"},
|
|
{.master = MT6785_M7_AXI_MST_APU_IOMMU_P1, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x1FF5,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_APU_IOMMU_P1"},
|
|
{.master = MT6785_M7_AXI_MST_APU, .port = 7, .id_mask = 0x1003,
|
|
.id_val = 0x1001,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_APU"},
|
|
{.master = MT6785_M7_AXI_MST_MFG_M1, .port = 7, .id_mask = 0x1F03,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_MFG_M1"},
|
|
{.master = MT6785_M7_AXI_MST_DEVICE_MPU, .port = 7, .id_mask = 0x1803,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6785_M7_AXI_MST_DEVICE_MPU"},
|
|
{.master = MT6785_M3_AXI_MST_MM, .port = 3, .id_mask = 0x1F83,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_MM"},
|
|
{.master = MT6785_M3_AXI_MST_MMU, .port = 3, .id_mask = 0x1F83,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_MMU"},
|
|
{.master = MT6785_M3_AXI_MST_USIP_0_I, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_USIP_0_I"},
|
|
{.master = MT6785_M3_AXI_MST_USIP_0_DLONG, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x12,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_USIP_0_DLONG"},
|
|
{.master = MT6785_M3_AXI_MST_USIP_0_DPERI, .port = 3, .id_mask = 0x1E0F,
|
|
.id_val = 0x6,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_USIP_0_DPERI"},
|
|
{.master = MT6785_M3_AXI_MST_USIP_1_I, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0xA,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_USIP_1_I"},
|
|
{.master = MT6785_M3_AXI_MST_USIP_1_DLONG, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x1A,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_USIP_1_DLONG"},
|
|
{.master = MT6785_M3_AXI_MST_USIP_1_DPERI, .port = 3, .id_mask = 0x1E0F,
|
|
.id_val = 0xE,
|
|
.note = "",
|
|
.name = "MT6785_M3_AXI_MST_USIP_1_DPERI"},
|
|
{.master = MT6785_M4_AXI_MST_HRQ_RD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1001,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_HRQ_RD"},
|
|
{.master = MT6785_M4_AXI_MST_HRQ_RD1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1009,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_HRQ_RD1"},
|
|
{.master = MT6785_M4_AXI_MST_HRQ_WR, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1003,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_HRQ_WR"},
|
|
{.master = MT6785_M4_AXI_MST_HRQ_WR1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x100B,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_HRQ_WR1"},
|
|
{.master = MT6785_M4_AXI_MST_VTB, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1005,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_VTB"},
|
|
{.master = MT6785_M4_AXI_MST_TBO, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x100D,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_TBO"},
|
|
{.master = MT6785_M4_AXI_MST_BR_DMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x807,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_BR_DMA"},
|
|
{.master = MT6785_M4_AXI_MST_IRDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xF,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_IRDMA"},
|
|
{.master = MT6785_M4_AXI_MST_TPC, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x6F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_TPC"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xEF,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_TXBSRP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x2F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_TXBSRP"},
|
|
{.master = MT6785_M4_AXI_MST_XDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x3F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_XDMA"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x13F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_MRSG0, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x7F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_MRSG0"},
|
|
{.master = MT6785_M4_AXI_MST_MRSG1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xBF,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_MRSG1"},
|
|
{.master = MT6785_M4_AXI_MST_CNWDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x9F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_CNWDMA"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x19F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_CSH0, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x5F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_CSH0"},
|
|
{.master = MT6785_M4_AXI_MST_DCXO, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1F,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_DCXO"},
|
|
{.master = MT6785_M4_AXI_MST_DMA_RD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1805,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_DMA_RD"},
|
|
{.master = MT6785_M4_AXI_MST_DMA_WR, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1801,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_DMA_WR"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1809,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_MMU, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1809,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_MMU"},
|
|
{.master = MT6785_M4_AXI_MST_QP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1801,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_QP"},
|
|
{.master = MT6785_M4_AXI_MST_QP_DLCH, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1803,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_QP_DLCH"},
|
|
{.master = MT6785_M4_AXI_MST_DMA_RD_DLCH, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1807,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_DMA_RD_DLCH"},
|
|
{.master = MT6785_M4_AXI_MST_IPF, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x180D,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_IPF"},
|
|
{.master = MT6785_M4_AXI_MST_LOG_TOP_MCU, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x15,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_LOG_TOP_MCU"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x15,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_LOG_TOP_DSP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x7,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_LOG_TOP_DSP"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x7,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_TRACE_TOP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x9,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_TRACE_TOP"},
|
|
{.master = MT6785_M4_AXI_MST_PPPHA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x3,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_PPPHA"},
|
|
{.master = MT6785_M4_AXI_MST_IPSEC, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xB,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_IPSEC"},
|
|
{.master = MT6785_M4_AXI_MST_DBGSYS_DSP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1D,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_DBGSYS_DSP"},
|
|
{.master = MT6785_M4_AXI_MST_GDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xD,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_GDMA"},
|
|
{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xED,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_"},
|
|
{.master = MT6785_M4_AXI_MST_HIFI3, .port = 4, .id_mask = 0x1F07,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_HIFI3"},
|
|
{.master = MT6785_M4_AXI_MST_CLDMA, .port = 4, .id_mask = 0x1F87,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_CLDMA"},
|
|
{.master = MT6785_M4_AXI_MST_CONNSYS, .port = 4, .id_mask = 0x1FC7,
|
|
.id_val = 0x4,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_CONNSYS"},
|
|
{.master = MT6785_M4_AXI_MST_SSPM, .port = 4, .id_mask = 0x1FCF,
|
|
.id_val = 0xE,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_SSPM"},
|
|
{.master = MT6785_M4_AXI_MST_SCP, .port = 4, .id_mask = 0x1FCF,
|
|
.id_val = 0x6,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_SCP"},
|
|
{.master = MT6785_M4_AXI_MST_MCUSYS_DFD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1000,
|
|
.note = "",
|
|
.name = "MT6785_M4_AXI_MST_MCUSYS_DFD"},
|
|
};
|
|
|
|
#endif /* __MPU_PLATFORM_H__ */
|