435 lines
16 KiB
C
435 lines
16 KiB
C
#ifndef CMDQ_EVENT_COMMON
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#define CMDQ_EVENT_COMMON
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/* Define CMDQ events
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*
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* For hardware event must define in device tree.
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* For SW event assign event ID here directly.
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*
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* Note: event name must sync to cmdq_events table in cmdq_event_common.c
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*/
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enum CMDQ_EVENT_ENUM {
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/* MDP start frame */
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CMDQ_EVENT_MDP_RDMA0_SOF = 0,
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CMDQ_EVENT_MDP_RDMA1_SOF, /* 1 */
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CMDQ_EVENT_MDP_RSZ0_SOF, /* 2 */
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CMDQ_EVENT_MDP_RSZ1_SOF, /* 3 */
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CMDQ_EVENT_MDP_RSZ2_SOF, /* 4 */
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CMDQ_EVENT_MDP_TDSHP_SOF, /* 5 */
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CMDQ_EVENT_MDP_TDSHP0_SOF, /* 6 */
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CMDQ_EVENT_MDP_TDSHP1_SOF, /* 7 */
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CMDQ_EVENT_MDP_WDMA_SOF, /* 8 */
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CMDQ_EVENT_MDP_WROT_SOF, /* 9 */
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CMDQ_EVENT_MDP_WROT0_SOF, /* 10 */
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CMDQ_EVENT_MDP_WROT1_SOF, /* 11 */
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CMDQ_EVENT_MDP_COLOR_SOF, /* 12 */
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CMDQ_EVENT_MDP_MVW_SOF, /* 13 */
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CMDQ_EVENT_MDP_CROP_SOF, /* 14 */
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/* Display start frame */
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CMDQ_EVENT_DISP_OVL0_SOF, /* 15 */
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CMDQ_EVENT_DISP_OVL1_SOF, /* 16 */
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CMDQ_EVENT_DISP_2L_OVL0_SOF, /* 17 */
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CMDQ_EVENT_DISP_2L_OVL1_SOF, /* 18 */
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CMDQ_EVENT_DISP_RDMA0_SOF, /* 19 */
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CMDQ_EVENT_DISP_RDMA1_SOF, /* 20 */
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CMDQ_EVENT_DISP_RDMA2_SOF, /* 21 */
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CMDQ_EVENT_DISP_WDMA0_SOF, /* 22 */
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CMDQ_EVENT_DISP_WDMA1_SOF, /* 23 */
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CMDQ_EVENT_DISP_COLOR_SOF, /* 24 */
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CMDQ_EVENT_DISP_COLOR0_SOF, /* 25 */
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CMDQ_EVENT_DISP_COLOR1_SOF, /* 26 */
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CMDQ_EVENT_DISP_CCORR_SOF, /* 27 */
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CMDQ_EVENT_DISP_CCORR0_SOF, /* 28 */
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CMDQ_EVENT_DISP_CCORR1_SOF, /* 29 */
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CMDQ_EVENT_DISP_AAL_SOF, /* 30 */
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CMDQ_EVENT_DISP_AAL0_SOF, /* 31 */
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CMDQ_EVENT_DISP_AAL1_SOF, /* 32 */
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CMDQ_EVENT_DISP_GAMMA_SOF, /* 33 */
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CMDQ_EVENT_DISP_GAMMA0_SOF, /* 34 */
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CMDQ_EVENT_DISP_GAMMA1_SOF, /* 35 */
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CMDQ_EVENT_DISP_DITHER_SOF, /* 36 */
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CMDQ_EVENT_DISP_DITHER0_SOF, /* 37 */
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CMDQ_EVENT_DISP_DITHER1_SOF, /* 38 */
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CMDQ_EVENT_DISP_UFOE_SOF, /* 39 */
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CMDQ_EVENT_DISP_PWM0_SOF, /* 40 */
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CMDQ_EVENT_DISP_PWM1_SOF, /* 41 */
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CMDQ_EVENT_DISP_OD_SOF, /* 42 */
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CMDQ_EVENT_DISP_DSC_SOF, /* 43 */
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CMDQ_EVENT_UFOD_RAMA0_L0_SOF, /* 44 */
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CMDQ_EVENT_UFOD_RAMA0_L1_SOF, /* 45 */
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CMDQ_EVENT_UFOD_RAMA0_L2_SOF, /* 46 */
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CMDQ_EVENT_UFOD_RAMA0_L3_SOF, /* 47 */
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CMDQ_EVENT_UFOD_RAMA1_L0_SOF, /* 48 */
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CMDQ_EVENT_UFOD_RAMA1_L1_SOF, /* 49 */
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CMDQ_EVENT_UFOD_RAMA1_L2_SOF, /* 50 */
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CMDQ_EVENT_UFOD_RAMA1_L3_SOF, /* 51 */
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/* MDP frame done */
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CMDQ_EVENT_MDP_RDMA0_EOF, /* 52 */
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CMDQ_EVENT_MDP_RDMA1_EOF, /* 53 */
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CMDQ_EVENT_MDP_RSZ0_EOF, /* 54 */
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CMDQ_EVENT_MDP_RSZ1_EOF, /* 55 */
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CMDQ_EVENT_MDP_RSZ2_EOF, /* 56 */
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CMDQ_EVENT_MDP_TDSHP_EOF, /* 57 */
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CMDQ_EVENT_MDP_TDSHP0_EOF, /* 58 */
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CMDQ_EVENT_MDP_TDSHP1_EOF, /* 59 */
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CMDQ_EVENT_MDP_WDMA_EOF, /* 60 */
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CMDQ_EVENT_MDP_WROT_WRITE_EOF, /* 61 */
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CMDQ_EVENT_MDP_WROT_READ_EOF, /* 62 */
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CMDQ_EVENT_MDP_WROT0_WRITE_EOF, /* 63 */
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CMDQ_EVENT_MDP_WROT0_READ_EOF, /* 64 */
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CMDQ_EVENT_MDP_WROT1_WRITE_EOF, /* 65 */
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CMDQ_EVENT_MDP_WROT1_READ_EOF, /* 66 */
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CMDQ_EVENT_MDP_WROT0_W_EOF, /* 67 */
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CMDQ_EVENT_MDP_WROT0_R_EOF, /* 68 */
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CMDQ_EVENT_MDP_WROT1_W_EOF, /* 69 */
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CMDQ_EVENT_MDP_WROT1_R_EOF, /* 70 */
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CMDQ_EVENT_MDP_COLOR_EOF, /* 71 */
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CMDQ_EVENT_MDP_CROP_EOF, /* 72 */
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/* Display frame done */
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CMDQ_EVENT_DISP_OVL0_EOF, /* 73 */
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CMDQ_EVENT_DISP_OVL1_EOF, /* 74 */
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CMDQ_EVENT_DISP_2L_OVL0_EOF, /* 75 */
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CMDQ_EVENT_DISP_2L_OVL1_EOF, /* 76 */
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CMDQ_EVENT_DISP_RDMA0_EOF, /* 77 */
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CMDQ_EVENT_DISP_RDMA1_EOF, /* 78 */
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CMDQ_EVENT_DISP_RDMA2_EOF, /* 79 */
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CMDQ_EVENT_DISP_WDMA0_EOF, /* 80 */
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CMDQ_EVENT_DISP_WDMA1_EOF, /* 81 */
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CMDQ_EVENT_DISP_COLOR_EOF, /* 82 */
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CMDQ_EVENT_DISP_COLOR0_EOF, /* 83 */
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CMDQ_EVENT_DISP_COLOR1_EOF, /* 84 */
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CMDQ_EVENT_DISP_CCORR_EOF, /* 85 */
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CMDQ_EVENT_DISP_CCORR0_EOF, /* 86 */
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CMDQ_EVENT_DISP_CCORR1_EOF, /* 87 */
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CMDQ_EVENT_DISP_AAL_EOF, /* 88 */
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CMDQ_EVENT_DISP_AAL0_EOF, /* 89 */
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CMDQ_EVENT_DISP_AAL1_EOF, /* 90 */
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CMDQ_EVENT_DISP_GAMMA_EOF, /* 91 */
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CMDQ_EVENT_DISP_GAMMA0_EOF, /* 92 */
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CMDQ_EVENT_DISP_GAMMA1_EOF, /* 93 */
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CMDQ_EVENT_DISP_DITHER_EOF, /* 94 */
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CMDQ_EVENT_DISP_DITHER0_EOF, /* 95 */
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CMDQ_EVENT_DISP_DITHER1_EOF, /* 96 */
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CMDQ_EVENT_DISP_UFOE_EOF, /* 97 */
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CMDQ_EVENT_DISP_OD_EOF, /* 98 */
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CMDQ_EVENT_DISP_OD_RDMA_EOF, /* 99 */
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CMDQ_EVENT_DISP_OD_WDMA_EOF, /* 100 */
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CMDQ_EVENT_DISP_DSC_EOF, /* 101 */
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CMDQ_EVENT_DISP_DSI0_EOF, /* 102 */
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CMDQ_EVENT_DISP_DSI1_EOF, /* 103 */
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CMDQ_EVENT_DISP_DPI0_EOF, /* 104 */
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CMDQ_EVENT_UFOD_RAMA0_L0_EOF, /* 105 */
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CMDQ_EVENT_UFOD_RAMA0_L1_EOF, /* 106 */
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CMDQ_EVENT_UFOD_RAMA0_L2_EOF, /* 107 */
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CMDQ_EVENT_UFOD_RAMA0_L3_EOF, /* 108 */
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CMDQ_EVENT_UFOD_RAMA1_L0_EOF, /* 109 */
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CMDQ_EVENT_UFOD_RAMA1_L1_EOF, /* 110 */
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CMDQ_EVENT_UFOD_RAMA1_L2_EOF, /* 111 */
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CMDQ_EVENT_UFOD_RAMA1_L3_EOF, /* 112 */
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/* Mutex frame done */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX0_STREAM_EOF, /* 113 */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX1_STREAM_EOF, /* 114 */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX2_STREAM_EOF, /* 115 */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX3_STREAM_EOF, /* 116 */
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/* DISPSYS, please refer to disp_hal.h */
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CMDQ_EVENT_MUTEX4_STREAM_EOF, /* 117 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX5_STREAM_EOF, /* 118 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX6_STREAM_EOF, /* 119 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX7_STREAM_EOF, /* 120 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX8_STREAM_EOF, /* 121 */
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/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
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CMDQ_EVENT_MUTEX9_STREAM_EOF, /* 122 */
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CMDQ_EVENT_MUTEX10_STREAM_EOF, /* 123 */
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CMDQ_EVENT_MUTEX11_STREAM_EOF, /* 124 */
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CMDQ_EVENT_MUTEX12_STREAM_EOF, /* 125 */
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CMDQ_EVENT_MUTEX13_STREAM_EOF, /* 126 */
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CMDQ_EVENT_MUTEX14_STREAM_EOF, /* 127 */
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CMDQ_EVENT_MUTEX15_STREAM_EOF, /* 128 */
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/* Display underrun */
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CMDQ_EVENT_DISP_RDMA0_UNDERRUN, /* 129 */
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CMDQ_EVENT_DISP_RDMA1_UNDERRUN, /* 130 */
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CMDQ_EVENT_DISP_RDMA2_UNDERRUN, /* 131 */
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/* Display TE */
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CMDQ_EVENT_DSI_TE, /* 132 */
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CMDQ_EVENT_DSI0_TE, /* 133 */
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CMDQ_EVENT_DSI1_TE, /* 134 */
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CMDQ_EVENT_MDP_DSI0_TE_SOF, /* 135 */
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CMDQ_EVENT_MDP_DSI1_TE_SOF, /* 136 */
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CMDQ_EVENT_DISP_DSI0_SOF, /* 137 */
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CMDQ_EVENT_DISP_DSI1_SOF, /* 138 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK0, /* 139 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK1, /* 140 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK2, /* 141 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK3, /* 142 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK4, /* 143 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK0, /* 144 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK1, /* 145 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK2, /* 146 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK3, /* 147 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK4, /* 148 */
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/* Reset Event */
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CMDQ_EVENT_DISP_WDMA0_RST_DONE, /* 149 */
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CMDQ_EVENT_DISP_WDMA1_RST_DONE, /* 150 */
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CMDQ_EVENT_MDP_WROT0_RST_DONE, /* 151 */
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CMDQ_EVENT_MDP_WROT1_RST_DONE, /* 152 */
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CMDQ_EVENT_MDP_WDMA_RST_DONE, /* 153 */
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CMDQ_EVENT_MDP_RDMA0_RST_DONE, /* 154 */
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CMDQ_EVENT_MDP_RDMA1_RST_DONE, /* 155 */
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/* Display Mutex */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD0, /* 156 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD1, /* 157 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD2, /* 158 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD3, /* 159 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD4, /* 160 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD5, /* 161 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD6, /* 162 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD7, /* 163 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD8, /* 164 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD9, /* 165 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD10, /* 166 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD11, /* 167 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD12, /* 168 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD13, /* 169 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD14, /* 170 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD15, /* 171 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE0, /* 172 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE1, /* 173 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE2, /* 174 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE3, /* 175 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE4, /* 176 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE5, /* 177 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE6, /* 178 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE7, /* 179 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE8, /* 180 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE9, /* 181 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE10, /* 182 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE11, /* 183 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE12, /* 184 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE13, /* 185 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE14, /* 186 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE15, /* 187 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE16, /* 188 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE17, /* 189 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE18, /* 190 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE19, /* 191 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE20, /* 192 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE21, /* 193 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE22, /* 194 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE23, /* 195 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE24, /* 196 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE25, /* 197 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE26, /* 198 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE27, /* 199 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE28, /* 200 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE29, /* 201 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE30, /* 202 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE31, /* 203 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE32, /* 204 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE33, /* 205 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE34, /* 206 */
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/* ISP frame done */
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CMDQ_EVENT_ISP_PASS2_2_EOF, /* 207 */
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CMDQ_EVENT_ISP_PASS2_1_EOF, /* 208 */
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CMDQ_EVENT_ISP_PASS2_0_EOF, /* 209 */
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CMDQ_EVENT_ISP_PASS1_1_EOF, /* 210 */
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CMDQ_EVENT_ISP_PASS1_0_EOF, /* 211 */
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/* ISP (IMGSYS) frame done */
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CMDQ_EVENT_DIP_CQ_THREAD0_EOF, /* 212 */
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CMDQ_EVENT_DIP_CQ_THREAD1_EOF, /* 213 */
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CMDQ_EVENT_DIP_CQ_THREAD2_EOF, /* 214 */
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CMDQ_EVENT_DIP_CQ_THREAD3_EOF, /* 215 */
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CMDQ_EVENT_DIP_CQ_THREAD4_EOF, /* 216 */
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CMDQ_EVENT_DIP_CQ_THREAD5_EOF, /* 217 */
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CMDQ_EVENT_DIP_CQ_THREAD6_EOF, /* 218 */
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CMDQ_EVENT_DIP_CQ_THREAD7_EOF, /* 219 */
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CMDQ_EVENT_DIP_CQ_THREAD8_EOF, /* 220 */
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CMDQ_EVENT_DIP_CQ_THREAD9_EOF, /* 221 */
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CMDQ_EVENT_DIP_CQ_THREAD10_EOF, /* 222 */
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CMDQ_EVENT_DIP_CQ_THREAD11_EOF, /* 223 */
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CMDQ_EVENT_DIP_CQ_THREAD12_EOF, /* 224 */
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CMDQ_EVENT_DIP_CQ_THREAD13_EOF, /* 225 */
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CMDQ_EVENT_DIP_CQ_THREAD14_EOF, /* 226 */
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CMDQ_EVENT_DPE_EOF, /* 227 */
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CMDQ_EVENT_DVE_EOF, /* 228 */
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CMDQ_EVENT_WMF_EOF, /* 229 */
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CMDQ_EVENT_GEPF_EOF, /* 230 */
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CMDQ_EVENT_GEPF_TEMP_EOF, /* 231 */
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CMDQ_EVENT_GEPF_BYPASS_EOF, /* 232 */
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CMDQ_EVENT_RSC_EOF, /* 233 */
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/* ISP (IMGSYS) engine events */
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CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, /* 234 */
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CMDQ_EVENT_ISP_SENINF_CAM0_FULL, /* 235 */
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/* VENC frame done */
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CMDQ_EVENT_VENC_EOF, /* 236 */
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/* JPEG frame done */
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CMDQ_EVENT_JPEG_ENC_EOF, /* 237 */
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CMDQ_EVENT_JPEG_ENC_PASS2_EOF, /* 238 */
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CMDQ_EVENT_JPEG_ENC_PASS1_EOF, /* 239 */
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CMDQ_EVENT_JPEG_DEC_EOF, /* 240 */
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/* VENC engine events */
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CMDQ_EVENT_VENC_MB_DONE, /* 241 */
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CMDQ_EVENT_VENC_128BYTE_CNT_DONE, /* 242 */
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/* ISP (CAMSYS) frame done */
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CMDQ_EVENT_ISP_FRAME_DONE_A, /* 243 */
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CMDQ_EVENT_ISP_FRAME_DONE_B, /* 244 */
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CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE, /* 245 */
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CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, /* 246 */
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CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, /* 247 */
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CMDQ_EVENT_ISP_TSF_DONE, /* 248 */
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/* ISP (CAMSYS) engine events */
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CMDQ_EVENT_SENINF_0_FIFO_FULL, /* 249 */
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CMDQ_EVENT_SENINF_1_FIFO_FULL, /* 250 */
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CMDQ_EVENT_SENINF_2_FIFO_FULL, /* 251 */
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CMDQ_EVENT_SENINF_3_FIFO_FULL, /* 252 */
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CMDQ_EVENT_SENINF_4_FIFO_FULL, /* 253 */
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CMDQ_EVENT_SENINF_5_FIFO_FULL, /* 254 */
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CMDQ_EVENT_SENINF_6_FIFO_FULL, /* 255 */
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CMDQ_EVENT_SENINF_7_FIFO_FULL, /* 256 */
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/* DPI1 frame done */
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CMDQ_EVENT_DISP_DPI1_EOF, /* 257 */
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/* Keep this at the end of HW events */
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CMDQ_MAX_HW_EVENT_COUNT = 400,
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/* SW Sync Tokens (Pre-defined) */
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/* Config thread notify trigger thread */
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CMDQ_SYNC_TOKEN_CONFIG_DIRTY = 401,
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/* Trigger thread notify config thread */
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CMDQ_SYNC_TOKEN_STREAM_EOF = 402,
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/* Block Trigger thread until the ESD check finishes. */
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CMDQ_SYNC_TOKEN_ESD_EOF = 403,
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/* check CABC setup finish */
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CMDQ_SYNC_TOKEN_CABC_EOF = 404,
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/* Block Trigger thread until the path freeze finishes */
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CMDQ_SYNC_TOKEN_FREEZE_EOF = 405,
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/* Pass-2 notifies VENC frame is ready to be encoded */
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CMDQ_SYNC_TOKEN_VENC_INPUT_READY = 406,
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/* VENC notifies Pass-2 encode done so next frame may start */
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CMDQ_SYNC_TOKEN_VENC_EOF = 407,
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/* Notify normal CMDQ there are some secure task done */
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CMDQ_SYNC_SECURE_THR_EOF = 408,
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/* Lock WSM resource */
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CMDQ_SYNC_SECURE_WSM_LOCK = 409,
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/* SW Sync Tokens (User-defined) */
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CMDQ_SYNC_TOKEN_USER_0 = 410,
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CMDQ_SYNC_TOKEN_USER_1 = 411,
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CMDQ_SYNC_TOKEN_POLL_MONITOR = 412,
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|
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/* Secure video path notify SW token */
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CMDQ_SYNC_DISP_OVL0_2NONSEC_END = 420,
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CMDQ_SYNC_DISP_OVL1_2NONSEC_END = 421,
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CMDQ_SYNC_DISP_2LOVL0_2NONSEC_END = 422,
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CMDQ_SYNC_DISP_2LOVL1_2NONSEC_END = 423,
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CMDQ_SYNC_DISP_RDMA0_2NONSEC_END = 424,
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CMDQ_SYNC_DISP_RDMA1_2NONSEC_END = 425,
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CMDQ_SYNC_DISP_WDMA0_2NONSEC_END = 426,
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CMDQ_SYNC_DISP_WDMA1_2NONSEC_END = 427,
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CMDQ_SYNC_DISP_EXT_STREAM_EOF = 428,
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|
|
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/* Event for CMDQ to block executing command when append command
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* Plz sync CMDQ_SYNC_TOKEN_APPEND_THR(id) in cmdq_core source file.
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*/
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CMDQ_SYNC_TOKEN_APPEND_THR0 = 432,
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CMDQ_SYNC_TOKEN_APPEND_THR1 = 433,
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CMDQ_SYNC_TOKEN_APPEND_THR2 = 434,
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CMDQ_SYNC_TOKEN_APPEND_THR3 = 435,
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CMDQ_SYNC_TOKEN_APPEND_THR4 = 436,
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CMDQ_SYNC_TOKEN_APPEND_THR5 = 437,
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CMDQ_SYNC_TOKEN_APPEND_THR6 = 438,
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CMDQ_SYNC_TOKEN_APPEND_THR7 = 439,
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CMDQ_SYNC_TOKEN_APPEND_THR8 = 440,
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CMDQ_SYNC_TOKEN_APPEND_THR9 = 441,
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CMDQ_SYNC_TOKEN_APPEND_THR10 = 442,
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CMDQ_SYNC_TOKEN_APPEND_THR11 = 443,
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CMDQ_SYNC_TOKEN_APPEND_THR12 = 444,
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CMDQ_SYNC_TOKEN_APPEND_THR13 = 445,
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CMDQ_SYNC_TOKEN_APPEND_THR14 = 446,
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CMDQ_SYNC_TOKEN_APPEND_THR15 = 447,
|
|
|
|
/* GPR access tokens (for HW register backup) */
|
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/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for
|
|
* value)
|
|
*/
|
|
CMDQ_SYNC_TOKEN_GPR_SET_0 = 450,
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CMDQ_SYNC_TOKEN_GPR_SET_1 = 451,
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CMDQ_SYNC_TOKEN_GPR_SET_2 = 452,
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|
CMDQ_SYNC_TOKEN_GPR_SET_3 = 453,
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|
CMDQ_SYNC_TOKEN_GPR_SET_4 = 454,
|
|
|
|
/* Resource lock event to control resource in GCE thread */
|
|
CMDQ_SYNC_RESOURCE_WROT0 = 460,
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|
CMDQ_SYNC_RESOURCE_WROT1 = 461,
|
|
|
|
/* Event for CMDQ delay implement
|
|
* Plz sync CMDQ_SYNC_TOKEN_DELAY_THR(id) in cmdq_core source file.
|
|
*/
|
|
CMDQ_SYNC_TOKEN_DELAY_THR0 = 470,
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|
CMDQ_SYNC_TOKEN_DELAY_THR1 = 471,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR2 = 472,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR3 = 473,
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|
CMDQ_SYNC_TOKEN_DELAY_THR4 = 474,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR5 = 475,
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|
CMDQ_SYNC_TOKEN_DELAY_THR6 = 476,
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|
CMDQ_SYNC_TOKEN_DELAY_THR7 = 477,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR8 = 478,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR9 = 479,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR10 = 480,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR11 = 481,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR12 = 482,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR13 = 483,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR14 = 484,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR15 = 485,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR16 = 486,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR17 = 487,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR18 = 488,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR19 = 489,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR20 = 490,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR21 = 491,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR22 = 492,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR23 = 493,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR24 = 494,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR25 = 495,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR26 = 496,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR27 = 497,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR28 = 498,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR29 = 499,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR30 = 500,
|
|
CMDQ_SYNC_TOKEN_DELAY_THR31 = 501,
|
|
CMDQ_SYNC_TOKEN_TIMER = 502,
|
|
|
|
/* event id is 9 bit */
|
|
CMDQ_SYNC_TOKEN_MAX = 0x1FF,
|
|
CMDQ_SYNC_TOKEN_INVALID = -1,
|
|
};
|
|
|
|
#endif |